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-rw-r--r--host/lib/usrp/common/ad9361_ctrl.cpp11
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_device.cpp42
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_device.h3
3 files changed, 36 insertions, 20 deletions
diff --git a/host/lib/usrp/common/ad9361_ctrl.cpp b/host/lib/usrp/common/ad9361_ctrl.cpp
index bf0bb75d2..be97efb19 100644
--- a/host/lib/usrp/common/ad9361_ctrl.cpp
+++ b/host/lib/usrp/common/ad9361_ctrl.cpp
@@ -31,6 +31,8 @@ public:
virtual boost::uint8_t peek8(boost::uint32_t reg)
{
+ boost::lock_guard<boost::mutex> lock(_mutex);
+
uhd::spi_config_t config;
config.mosi_edge = uhd::spi_config_t::EDGE_FALL;
config.miso_edge = uhd::spi_config_t::EDGE_FALL; //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE
@@ -46,6 +48,8 @@ public:
virtual void poke8(boost::uint32_t reg, boost::uint8_t val)
{
+ boost::lock_guard<boost::mutex> lock(_mutex);
+
uhd::spi_config_t config;
config.mosi_edge = uhd::spi_config_t::EDGE_FALL;
config.miso_edge = uhd::spi_config_t::EDGE_FALL; //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE
@@ -54,15 +58,12 @@ public:
((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK) |
((boost::uint32_t(val) << AD9361_SPI_DATA_SHIFT) & AD9361_SPI_DATA_MASK);
_spi_iface->write_spi(_slave_num, config, wr_word, AD9361_SPI_NUM_BITS);
-
- //TODO (Ashish): Is this necessary? The FX3 firmware does it right now but for
- //networked devices, it makes writes blocking which will considerably slow down the programming
- peek8(reg);
}
private:
uhd::spi_iface::sptr _spi_iface;
- boost::uint32_t _slave_num;
+ boost::uint32_t _slave_num;
+ boost::mutex _mutex;
static const boost::uint32_t AD9361_SPI_WRITE_CMD = 0x00800000;
static const boost::uint32_t AD9361_SPI_READ_CMD = 0x00000000;
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index d0410bc9f..276176a94 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -44,21 +44,6 @@ namespace uhd { namespace usrp {
/* for upto 8-bit binary constants */
#define B8(d) ((unsigned char)B8__(HEX__(d)))
-void ad9361_device_t::output_test_tone()
-{
- /* Output a 480 kHz tone at 800 MHz */
- _io_iface->poke8(0x3F4, 0x0B);
- _io_iface->poke8(0x3FC, 0xFF);
- _io_iface->poke8(0x3FD, 0xFF);
- _io_iface->poke8(0x3FE, 0x3F);
-}
-
-void ad9361_device_t::data_port_loopback(const bool loopback_enabled)
-{
- debug_msg("[data_port_loopback] Enabled: %d", loopback_enabled);
- _io_iface->poke8(0x3F5, (loopback_enabled ? 0x01 : 0x00));
-}
-
/* This is a simple comparison for very large double-precision floating
* point numbers. It is used to prevent re-tunes for frequencies that are
* the same but not 'exactly' because of data precision issues. */
@@ -1373,6 +1358,8 @@ double ad9361_device_t::_setup_rates(const double rate)
**********************************************************************/
void ad9361_device_t::initialize()
{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+
/* Initialize shadow registers. */
_regs.vcodivs = 0x00;
_regs.inputsel = 0x30;
@@ -1603,6 +1590,8 @@ void ad9361_device_t::initialize()
* This is the only clock setting function that is exposed to the outside. */
double ad9361_device_t::set_clock_rate(const double req_rate)
{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+
if (req_rate > 61.44e6) {
throw uhd::runtime_error("[ad9361_device_t] Requested master clock rate outside range");
}
@@ -1737,6 +1726,8 @@ double ad9361_device_t::set_clock_rate(const double req_rate)
*/
void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2)
{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+
/* Clear out the current active chain settings. */
_regs.txfilt = _regs.txfilt & 0x3F;
_regs.rxfilt = _regs.rxfilt & 0x3F;
@@ -1787,6 +1778,8 @@ void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2)
* After tuning, it runs any appropriate calibrations. */
double ad9361_device_t::tune(direction_t direction, const double value)
{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+
if (direction == RX) {
if (freq_is_nearly_equal(value, _req_rx_freq)) {
return _rx_freq;
@@ -1841,6 +1834,8 @@ double ad9361_device_t::tune(direction_t direction, const double value)
* are done in terms of attenuation. */
double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const double value)
{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+
if (direction == RX) {
/* Indexing the gain tables requires an offset from the requested
* amount of total gain in dB:
@@ -1898,4 +1893,21 @@ double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const dou
}
}
+void ad9361_device_t::output_test_tone()
+{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+ /* Output a 480 kHz tone at 800 MHz */
+ _io_iface->poke8(0x3F4, 0x0B);
+ _io_iface->poke8(0x3FC, 0xFF);
+ _io_iface->poke8(0x3FD, 0xFF);
+ _io_iface->poke8(0x3FE, 0x3F);
+}
+
+void ad9361_device_t::data_port_loopback(const bool loopback_enabled)
+{
+ boost::lock_guard<boost::recursive_mutex> lock(_mutex);
+ _io_iface->poke8(0x3F5, (loopback_enabled ? 0x01 : 0x00));
+}
+
+
}}
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
index 079f5dc1d..2d067fa7d 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
@@ -7,6 +7,7 @@
#include <ad9361_client.h>
#include <boost/noncopyable.hpp>
+#include <boost/thread/recursive_mutex.hpp>
namespace uhd { namespace usrp {
@@ -115,6 +116,8 @@ private: //Members
boost::int32_t _tfir_factor;
//Register soft-copies
chip_regs_t _regs;
+ //Synchronization
+ boost::recursive_mutex _mutex;
};
}} //namespace
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 15:05:38 +0000