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-rw-r--r--host/lib/usrp/common/adf435x_common.cpp3
-rw-r--r--host/lib/usrp/x300/x300_fw_ctrl.cpp22
-rw-r--r--host/lib/usrp/x300/x300_impl.cpp13
-rw-r--r--host/lib/usrp/x300/x300_impl.hpp2
4 files changed, 19 insertions, 21 deletions
diff --git a/host/lib/usrp/common/adf435x_common.cpp b/host/lib/usrp/common/adf435x_common.cpp
index 972a69388..9b362a4d9 100644
--- a/host/lib/usrp/common/adf435x_common.cpp
+++ b/host/lib/usrp/common/adf435x_common.cpp
@@ -17,6 +17,7 @@
#include "adf435x_common.hpp"
+#include <boost/math/special_functions/round.hpp>
#include <uhd/types/tune_request.hpp>
#include <uhd/utils/log.hpp>
#include <cmath>
@@ -96,7 +97,7 @@ adf435x_tuning_settings tune_adf435x_synth(
//Fractional-N calculation
MOD = 4095; //max fractional accuracy
- FRAC = static_cast<boost::uint16_t>((feedback_freq/pfd_freq - N)*MOD);
+ FRAC = static_cast<boost::uint16_t>(boost::math::round((feedback_freq/pfd_freq - N)*MOD));
if (constraints.force_frac0) {
if (FRAC > (MOD / 2)) { //Round integer such that actual freq is closest to target
N++;
diff --git a/host/lib/usrp/x300/x300_fw_ctrl.cpp b/host/lib/usrp/x300/x300_fw_ctrl.cpp
index 804d23f51..3a8d984fb 100644
--- a/host/lib/usrp/x300/x300_fw_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_fw_ctrl.cpp
@@ -187,16 +187,16 @@ private:
class x300_ctrl_iface_pcie : public x300_ctrl_iface
{
public:
- x300_ctrl_iface_pcie(niriok_proxy& drv_proxy):
+ x300_ctrl_iface_pcie(niriok_proxy::sptr drv_proxy):
_drv_proxy(drv_proxy)
{
nirio_status status = 0;
- nirio_status_chain(_drv_proxy.set_attribute(ADDRESS_SPACE, BUS_INTERFACE), status);
+ nirio_status_chain(_drv_proxy->set_attribute(RIO_ADDRESS_SPACE, BUS_INTERFACE), status);
//Verify that the Ettus FPGA loaded in the device. This may not be true if the
//user is switching to UHD after using LabVIEW FPGA.
boost::uint32_t pcie_fpga_signature = 0;
- _drv_proxy.peek(FPGA_PCIE_SIG_REG, pcie_fpga_signature);
+ _drv_proxy->peek(FPGA_PCIE_SIG_REG, pcie_fpga_signature);
if (pcie_fpga_signature != FPGA_X3xx_SIG_VALUE)
throw uhd::io_error("cannot create x300_ctrl_iface_pcie. incorrect/no fpga image");
@@ -209,7 +209,7 @@ public:
do {
boost::this_thread::sleep(boost::posix_time::microsec(500)); //Avoid flooding the bus
elapsed = boost::posix_time::microsec_clock::local_time() - start_time;
- nirio_status_chain(_drv_proxy.peek(PCIE_ZPU_STATUS_REG(0), reg_data), status);
+ nirio_status_chain(_drv_proxy->peek(PCIE_ZPU_STATUS_REG(0), reg_data), status);
} while (
nirio_status_not_fatal(status) &&
(reg_data & PCIE_ZPU_STATUS_SUSPENDED) &&
@@ -232,12 +232,12 @@ protected:
boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
boost::posix_time::time_duration elapsed;
- nirio_status_chain(_drv_proxy.poke(PCIE_ZPU_DATA_REG(addr), data), status);
+ nirio_status_chain(_drv_proxy->poke(PCIE_ZPU_DATA_REG(addr), data), status);
if (nirio_status_not_fatal(status)) {
do {
boost::this_thread::sleep(boost::posix_time::microsec(50)); //Avoid flooding the bus
elapsed = boost::posix_time::microsec_clock::local_time() - start_time;
- nirio_status_chain(_drv_proxy.peek(PCIE_ZPU_STATUS_REG(addr), reg_data), status);
+ nirio_status_chain(_drv_proxy->peek(PCIE_ZPU_STATUS_REG(addr), reg_data), status);
} while (
nirio_status_not_fatal(status) &&
((reg_data & (PCIE_ZPU_STATUS_BUSY | PCIE_ZPU_STATUS_SUSPENDED)) != 0) &&
@@ -257,18 +257,18 @@ protected:
boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
boost::posix_time::time_duration elapsed;
- nirio_status_chain(_drv_proxy.poke(PCIE_ZPU_READ_REG(addr), PCIE_ZPU_READ_START), status);
+ nirio_status_chain(_drv_proxy->poke(PCIE_ZPU_READ_REG(addr), PCIE_ZPU_READ_START), status);
if (nirio_status_not_fatal(status)) {
do {
boost::this_thread::sleep(boost::posix_time::microsec(50)); //Avoid flooding the bus
elapsed = boost::posix_time::microsec_clock::local_time() - start_time;
- nirio_status_chain(_drv_proxy.peek(PCIE_ZPU_STATUS_REG(addr), reg_data), status);
+ nirio_status_chain(_drv_proxy->peek(PCIE_ZPU_STATUS_REG(addr), reg_data), status);
} while (
nirio_status_not_fatal(status) &&
((reg_data & (PCIE_ZPU_STATUS_BUSY | PCIE_ZPU_STATUS_SUSPENDED)) != 0) &&
elapsed.total_milliseconds() < READ_TIMEOUT_IN_MS);
}
- nirio_status_chain(_drv_proxy.peek(PCIE_ZPU_DATA_REG(addr), reg_data), status);
+ nirio_status_chain(_drv_proxy->peek(PCIE_ZPU_DATA_REG(addr), reg_data), status);
if (nirio_status_fatal(status))
throw uhd::io_error("x300 fw peek32 - hardware IO error");
@@ -284,7 +284,7 @@ protected:
}
private:
- niriok_proxy& _drv_proxy;
+ niriok_proxy::sptr _drv_proxy;
static const boost::uint32_t READ_TIMEOUT_IN_MS = 10;
static const boost::uint32_t INIT_TIMEOUT_IN_MS = 5000;
};
@@ -294,7 +294,7 @@ wb_iface::sptr x300_make_ctrl_iface_enet(uhd::transport::udp_simple::sptr udp)
return wb_iface::sptr(new x300_ctrl_iface_enet(udp));
}
-wb_iface::sptr x300_make_ctrl_iface_pcie(niriok_proxy& drv_proxy)
+wb_iface::sptr x300_make_ctrl_iface_pcie(niriok_proxy::sptr drv_proxy)
{
return wb_iface::sptr(new x300_ctrl_iface_pcie(drv_proxy));
}
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 1494a100e..b4286ee79 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -171,8 +171,8 @@ static device_addrs_t x300_find_pcie(const device_addr_t &hint, bool explicit_qu
default:
continue;
}
-
- niriok_proxy kernel_proxy;
+
+ niriok_proxy::sptr kernel_proxy = niriok_proxy::make_and_open(dev_info.interface_path);
//Attempt to read the name from the EEPROM and perform filtering.
//This operation can throw due to compatibility mismatch.
@@ -192,7 +192,6 @@ static device_addrs_t x300_find_pcie(const device_addr_t &hint, bool explicit_qu
if (get_pcie_zpu_iface_registry().has_key(resource_d)) {
zpu_ctrl = get_pcie_zpu_iface_registry()[resource_d].lock();
} else {
- kernel_proxy.open(dev_info.interface_path);
zpu_ctrl = x300_make_ctrl_iface_pcie(kernel_proxy);
//We don't put this zpu_ctrl in the registry because we need
//a persistent niriok_proxy associated with the object
@@ -220,7 +219,6 @@ static device_addrs_t x300_find_pcie(const device_addr_t &hint, bool explicit_qu
new_addr["name"] = "";
new_addr["serial"] = "";
}
- kernel_proxy.close();
//filter the discovered device below by matching optional keys
std::string resource_i = hint.has_key("resource") ? hint["resource"] : "";
@@ -403,7 +401,6 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
have a valid USRP X3x0, NI USRP-294xR or NI USRP-295xR device and that all the device \
driver have been loaded.");
}
-
//Load the lvbitx onto the device
UHD_MSG(status) << boost::format("Using LVBITX bitfile %s...\n") % lvbitx->get_bitfile_path();
mb.rio_fpga_interface.reset(new niusrprio_session(dev_addr["resource"], rpc_port_name));
@@ -412,7 +409,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
//Tell the quirks object which FIFOs carry TX stream data
const boost::uint32_t tx_data_fifos[2] = {X300_RADIO_DEST_PREFIX_TX, X300_RADIO_DEST_PREFIX_TX + 3};
- mb.rio_fpga_interface->get_kernel_proxy().get_rio_quirks().register_tx_streams(tx_data_fifos);
+ mb.rio_fpga_interface->get_kernel_proxy()->get_rio_quirks().register_tx_streams(tx_data_fifos);
_tree->create<double>(mb_path / "link_max_rate").set(X300_MAX_RATE_PCIE);
}
@@ -1303,7 +1300,7 @@ boost::uint32_t x300_impl::allocate_sid(mboard_members_t &mb, const sid_config_t
if (xport_path == "nirio") {
boost::uint32_t router_config_word = ((_sid_framer & 0xff) << 16) | //Return SID
get_pcie_dma_channel(config.router_dst_there, config.dst_prefix); //Dest
- mb.rio_fpga_interface->get_kernel_proxy().poke(PCIE_ROUTER_REG(0), router_config_word);
+ mb.rio_fpga_interface->get_kernel_proxy()->poke(PCIE_ROUTER_REG(0), router_config_word);
}
UHD_LOG << std::hex
@@ -1683,7 +1680,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
niriok_proxy::sptr discovery_proxy =
niusrprio_session::create_kernel_proxy(resource, rpc_port);
if (discovery_proxy) {
- nirio_status_chain(discovery_proxy->get_attribute(PRODUCT_NUMBER, pid), status);
+ nirio_status_chain(discovery_proxy->get_attribute(RIO_PRODUCT_NUMBER, pid), status);
discovery_proxy->close();
if (nirio_status_not_fatal(status)) {
//The PCIe ID -> MB mapping may be different from the EEPROM -> MB mapping
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp
index 8abdee48c..924cb61a4 100644
--- a/host/lib/usrp/x300/x300_impl.hpp
+++ b/host/lib/usrp/x300/x300_impl.hpp
@@ -137,7 +137,7 @@ uhd::usrp::dboard_iface::sptr x300_make_dboard_iface(const x300_dboard_iface_con
uhd::uart_iface::sptr x300_make_uart_iface(uhd::wb_iface::sptr iface);
uhd::wb_iface::sptr x300_make_ctrl_iface_enet(uhd::transport::udp_simple::sptr udp);
-uhd::wb_iface::sptr x300_make_ctrl_iface_pcie(uhd::niusrprio::niriok_proxy& drv_proxy);
+uhd::wb_iface::sptr x300_make_ctrl_iface_pcie(uhd::niusrprio::niriok_proxy::sptr drv_proxy);
class x300_impl : public uhd::device
{
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 10:37:49 +0000