4 files changed, 195 insertions, 2 deletions
diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp
new file mode 100644
index 000000000..5f6fb4bfb
--- /dev/null
+++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp
@@ -0,0 +1,129 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "clock_ctrl.hpp"
+#include "ad9522_regs.hpp"
+#include <boost/cstdint.hpp>
+#include "usrp_e_regs.hpp" //spi slave constants
+#include <boost/assign/list_of.hpp>
+#include <boost/foreach.hpp>
+#include <utility>
+
+using namespace uhd;
+
+/***********************************************************************
+ * Clock Control Implementation
+ **********************************************************************/
+class clock_ctrl_impl : public clock_ctrl{
+public:
+    //structors
+    clock_ctrl_impl(usrp_e_iface::sptr iface);
+    ~clock_ctrl_impl(void);
+
+    void enable_rx_dboard_clock(bool enb);
+    void enable_tx_dboard_clock(bool enb);
+
+private:
+    usrp_e_iface::sptr _iface;
+    ad9522_regs_t _ad9522_regs;
+
+    void latch_regs(void){
+        _ad9522_regs.io_update = 1;
+        this->send_reg(0x232);
+    }
+    void send_reg(boost::uint16_t addr);
+};
+
+/***********************************************************************
+ * Clock Control Methods
+ **********************************************************************/
+clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){
+    _iface = iface;
+
+    //init the clock gen registers
+    //Note: out0 should already be clocking the FPGA or this isnt going to work
+    _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO;
+    _ad9522_regs.status_pin_control = 0x1; //n divider
+    _ad9522_regs.ld_pin_control = 0x32; //show ref2
+    _ad9522_regs.refmon_pin_control = 0x12; //show ref2
+
+    _ad9522_regs.enable_ref2 = 1;
+    _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2;
+
+    _ad9522_regs.r_counter_lsb = 1;
+    _ad9522_regs.r_counter_msb = 0;
+    _ad9522_regs.a_counter = 0;
+    _ad9522_regs.b_counter_lsb = 20;
+    _ad9522_regs.b_counter_msb = 0;
+    _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9;
+
+    _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL;
+    _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_3_0MA;
+
+    _ad9522_regs.vco_calibration_now = 1; //calibrate it!
+    _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5;
+    _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO;
+
+    _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
+    _ad9522_regs.divider0_low_cycles = 2; //3 low
+    _ad9522_regs.divider0_high_cycles = 1; //2 high
+
+    //setup a list of register ranges to write
+    typedef std::pair<boost::uint16_t, boost::uint16_t> range_t;
+    static const std::vector<range_t> ranges = boost::assign::list_of
+        (range_t(0x000, 0x000)) (range_t(0x010, 0x01F))
+        (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B))
+        (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230))
+    ;
+
+    //write initial register values and latch/update
+    BOOST_FOREACH(const range_t &range, ranges){
+        for(boost::uint16_t addr = range.first; addr <= range.second; addr++){
+            this->send_reg(addr);
+        }
+    }
+    this->latch_regs();
+}
+
+clock_ctrl_impl::~clock_ctrl_impl(void){
+    this->enable_rx_dboard_clock(false);
+    this->enable_tx_dboard_clock(false);
+}
+
+void clock_ctrl_impl::enable_rx_dboard_clock(bool enb){
+    
+}
+
+void clock_ctrl_impl::enable_tx_dboard_clock(bool enb){
+    
+}
+
+void clock_ctrl_impl::send_reg(boost::uint16_t addr){
+    _iface->transact_spi(
+        UE_SPI_SS_AD9522,
+        spi_config_t::EDGE_RISE,
+        _ad9522_regs.get_write_reg(addr),
+        24, false /*no rb*/
+    );
+}
+
+/***********************************************************************
+ * Clock Control Make
+ **********************************************************************/
+clock_ctrl::sptr clock_ctrl::make(usrp_e_iface::sptr iface){
+    return sptr(new clock_ctrl_impl(iface));
+}
diff --git a/host/lib/usrp/usrp_e/clock_ctrl.hpp b/host/lib/usrp/usrp_e/clock_ctrl.hpp
new file mode 100644
index 000000000..d0b896a8f
--- /dev/null
+++ b/host/lib/usrp/usrp_e/clock_ctrl.hpp
@@ -0,0 +1,55 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_USRP_E_CLOCK_CTRL_HPP
+#define INCLUDED_USRP_E_CLOCK_CTRL_HPP
+
+#include "usrp_e_iface.hpp"
+#include <boost/shared_ptr.hpp>
+#include <boost/utility.hpp>
+
+/*!
+ * The usrp-e clock control:
+ * - Setup system clocks.
+ * - Disable/enable clock lines.
+ */
+class clock_ctrl : boost::noncopyable{
+public:
+    typedef boost::shared_ptr<clock_ctrl> sptr;
+
+    /*!
+     * Make a new clock control object.
+     * \param iface the usrp_e iface object
+     * \return the clock control object
+     */
+    static sptr make(usrp_e_iface::sptr iface);
+
+    /*!
+     * Enable/disable the rx dboard clock.
+     * \param enb true to enable
+     */
+    virtual void enable_rx_dboard_clock(bool enb) = 0;
+
+    /*!
+     * Enable/disable the tx dboard clock.
+     * \param enb true to enable
+     */
+    virtual void enable_tx_dboard_clock(bool enb) = 0;
+
+};
+
+#endif /* INCLUDED_USRP_E_CLOCK_CTRL_HPP */
diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp
index f69cdd2b4..2a3976ba1 100644
--- a/host/lib/usrp/usrp_e/dboard_iface.cpp
+++ b/host/lib/usrp/usrp_e/dboard_iface.cpp
@@ -143,8 +143,8 @@ void usrp_e_dboard_iface::set_atr_reg(unit_t bank, atr_reg_t atr, boost::uint16_
  */
 static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){
     switch(unit){
-    case dboard_iface::UNIT_TX: return UE_SPI_CTRL_TXNEG;
-    case dboard_iface::UNIT_RX: return UE_SPI_CTRL_RXNEG;
+    case dboard_iface::UNIT_TX: return UE_SPI_SS_TX_DB;
+    case dboard_iface::UNIT_RX: return UE_SPI_SS_RX_DB;
     }
     throw std::invalid_argument("unknown unit type");
 }
diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
index e7f89db7b..46df8d089 100644
--- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp
+++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
@@ -50,6 +50,15 @@
 
 #define UE_REG_SPI_BASE UE_REG_SLAVE(2)
 
+//spi slave constants (copied from usrp2, TODO FIXME)
+#define UE_SPI_SS_AD9522    1
+#define UE_SPI_SS_AD9777    2
+#define UE_SPI_SS_RX_DAC    4
+#define UE_SPI_SS_RX_ADC    8
+#define UE_SPI_SS_RX_DB    16
+#define UE_SPI_SS_TX_DAC   32
+#define UE_SPI_SS_TX_ADC   64
+#define UE_SPI_SS_TX_DB   128
 
 ////////////////////////////////////////////////
 // Slave 3 -- I2C Core