diff options
Diffstat (limited to 'host/lib/usrp/x300')
| -rw-r--r-- | host/lib/usrp/x300/x300_fw_ctrl.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.cpp | 8 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 21 |
3 files changed, 17 insertions, 14 deletions
diff --git a/host/lib/usrp/x300/x300_fw_ctrl.cpp b/host/lib/usrp/x300/x300_fw_ctrl.cpp index 1df0fa611..5ff40c966 100644 --- a/host/lib/usrp/x300/x300_fw_ctrl.cpp +++ b/host/lib/usrp/x300/x300_fw_ctrl.cpp @@ -292,7 +292,7 @@ protected: private: niriok_proxy::sptr _drv_proxy; - static const uint32_t READ_TIMEOUT_IN_MS = 10; + static const uint32_t READ_TIMEOUT_IN_MS = 100; static const uint32_t INIT_TIMEOUT_IN_MS = 5000; }; diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index 785f7b4a3..ac08cf565 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -1128,14 +1128,14 @@ uhd::both_xports_t x300_impl::make_transport( ? X300_PCIE_RX_DATA_FRAME_SIZE : X300_PCIE_MSG_FRAME_SIZE; - default_buff_args.num_send_frames = - (xport_type == TX_DATA) - ? X300_PCIE_DATA_NUM_FRAMES + default_buff_args.num_send_frames = + (xport_type == TX_DATA) + ? X300_PCIE_TX_DATA_NUM_FRAMES : X300_PCIE_MSG_NUM_FRAMES; default_buff_args.num_recv_frames = (xport_type == RX_DATA) - ? X300_PCIE_DATA_NUM_FRAMES + ? X300_PCIE_RX_DATA_NUM_FRAMES : X300_PCIE_MSG_NUM_FRAMES; xports.recv = nirio_zero_copy::make( diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index 2de295bd9..27f3f130e 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -52,15 +52,18 @@ static const size_t X300_RX_SW_BUFF_SIZE_ETH = 0x2000000;//32MiB For a static const size_t X300_RX_SW_BUFF_SIZE_ETH_MACOS = 0x100000; //1Mib //The FIFO closest to the DMA controller is 1023 elements deep for RX and 1029 elements deep for TX -//where an element is 8 bytes. For best throughput ensure that the data frame fits in these buffers. -//Also ensure that the kernel has enough frames to hold buffered TX and RX data -static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 8184; //bytes -static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 8184; //bytes -static const size_t X300_PCIE_DATA_NUM_FRAMES = 2048; -static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes -static const size_t X300_PCIE_MSG_NUM_FRAMES = 64; -static const size_t X300_PCIE_MAX_CHANNELS = 6; -static const size_t X300_PCIE_MAX_MUXED_XPORTS = 32; +//where an element is 8 bytes. The buffers (number of frames * frame size) must be aligned to the +//memory page size. For the control, we are getting lucky because 64 frames * 256 bytes each aligns +//with the typical page size of 4096 bytes. Since most page sizes are 4096 bytes or some multiple of +//that, keep the number of frames * frame size aligned to it. +static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 4096; //bytes +static const size_t X300_PCIE_RX_DATA_NUM_FRAMES = 4096; +static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 4096; //bytes +static const size_t X300_PCIE_TX_DATA_NUM_FRAMES = 4096; +static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes +static const size_t X300_PCIE_MSG_NUM_FRAMES = 64; +static const size_t X300_PCIE_MAX_CHANNELS = 6; +static const size_t X300_PCIE_MAX_MUXED_XPORTS = 32; static const size_t X300_10GE_DATA_FRAME_MAX_SIZE = 8000; // CHDR packet size in bytes static const size_t X300_1GE_DATA_FRAME_MAX_SIZE = 1472; // CHDR packet size in bytes |