diff options
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index b59247d53..3aebfea68 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -287,6 +287,8 @@ void set_master_clock_rate(double clock_rate) { this->write_regs(0); _lmk04816_regs.CLKout0_1_DIV = vco_div; _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_EV_X; + _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_BOTH; + _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_BOTH; this->write_regs(0); // Register 1 @@ -309,9 +311,12 @@ void set_master_clock_rate(double clock_rate) { _lmk04816_regs.CLKout1_TYPE = lmk04816_regs_t::CLKOUT1_TYPE_P_DOWN; //CPRI feedback clock, use LVDS _lmk04816_regs.CLKout2_TYPE = lmk04816_regs_t::CLKOUT2_TYPE_LVPECL_700MVPP; //DB_0_RX _lmk04816_regs.CLKout3_TYPE = lmk04816_regs_t::CLKOUT3_TYPE_LVPECL_700MVPP; //DB_1_RX - // Analog delay of 900ps to synchronize the radio clock with the source synchronous ADC clocks. + // Delay the FPGA_CLK by 900ps to ensure a safe ADC_SSCLK -> RADIO_CLK crossing. + // If the FPGA_CLK is delayed, we also need to delay the reference clocks going to the DAC + // because the data interface clock is generated from FPGA_CLK. // This delay may need to vary due to temperature. Tested and verified at room temperature only. _lmk04816_regs.CLKout0_1_ADLY = 0x10; + _lmk04816_regs.CLKout6_7_ADLY = _lmk04816_regs.CLKout0_1_ADLY; // Register 7 _lmk04816_regs.CLKout4_TYPE = lmk04816_regs_t::CLKOUT4_TYPE_LVPECL_700MVPP; //DB_1_TX |