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-rw-r--r--host/lib/usrp/usrp_e/dboard_iface.cpp50
-rw-r--r--host/lib/usrp/usrp_e/usrp_e_impl.cpp14
-rw-r--r--host/lib/usrp/usrp_e/usrp_e_impl.hpp6
-rw-r--r--host/lib/usrp/usrp_e/usrp_e_regs.hpp12
4 files changed, 47 insertions, 35 deletions
diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp
index e70934b8c..23255b58c 100644
--- a/host/lib/usrp/usrp_e/dboard_iface.cpp
+++ b/host/lib/usrp/usrp_e/dboard_iface.cpp
@@ -49,8 +49,10 @@ public:
void write_aux_dac(unit_t, int, float);
float read_aux_adc(unit_t, int);
+ void set_pin_ctrl(unit_t, boost::uint16_t);
void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t);
void set_gpio_ddr(unit_t, boost::uint16_t);
+ void write_gpio(unit_t, boost::uint16_t);
boost::uint16_t read_gpio(unit_t);
void write_i2c(boost::uint8_t, const byte_vector_t &);
@@ -111,29 +113,41 @@ void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){
/***********************************************************************
* GPIO
**********************************************************************/
-void usrp_e_dboard_iface::set_gpio_ddr(unit_t bank, boost::uint16_t value){
- //define mapping of gpio bank to register address
- static const uhd::dict<unit_t, boost::uint32_t> bank_to_addr = map_list_of
- (UNIT_RX, UE_REG_GPIO_RX_DDR)
- (UNIT_TX, UE_REG_GPIO_TX_DDR)
- ;
- _iface->poke16(bank_to_addr[bank], value);
+void usrp_e_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){
+ UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption
+ switch(unit){
+ case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_SEL, value); return;
+ case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_SEL, value); return;
+ }
}
-boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t bank){
- //define mapping of gpio bank to register address
- static const uhd::dict<unit_t, boost::uint32_t> bank_to_addr = map_list_of
- (UNIT_RX, UE_REG_GPIO_RX_IO)
- (UNIT_TX, UE_REG_GPIO_TX_IO)
- ;
- return _iface->peek16(bank_to_addr[bank]);
+void usrp_e_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){
+ switch(unit){
+ case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_DDR, value); return;
+ case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_DDR, value); return;
+ }
+}
+
+void usrp_e_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){
+ switch(unit){
+ case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_IO, value); return;
+ case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_IO, value); return;
+ }
+}
+
+boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t unit){
+ switch(unit){
+ case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO);
+ case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO);
+ }
+ UHD_ASSERT_THROW(false);
}
-void usrp_e_dboard_iface::set_atr_reg(unit_t bank, atr_reg_t atr, boost::uint16_t value){
- //define mapping of bank to atr regs to register address
+void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){
+ //define mapping of unit to atr regs to register address
static const uhd::dict<
unit_t, uhd::dict<atr_reg_t, boost::uint32_t>
- > bank_to_atr_to_addr = map_list_of
+ > unit_to_atr_to_addr = map_list_of
(UNIT_RX, map_list_of
(ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE)
(ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE)
@@ -147,7 +161,7 @@ void usrp_e_dboard_iface::set_atr_reg(unit_t bank, atr_reg_t atr, boost::uint16_
(ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE)
)
;
- _iface->poke16(bank_to_atr_to_addr[bank][atr], value);
+ _iface->poke16(unit_to_atr_to_addr[unit][atr], value);
}
/***********************************************************************
diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp
index 4f7361eca..4a398e21c 100644
--- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp
+++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp
@@ -117,14 +117,6 @@ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){
val = prop_names_t(1, ""); //vector of size 1 with empty string
return;
- case DEVICE_PROP_MAX_RX_SAMPLES:
- val = size_t(_max_num_samples);
- return;
-
- case DEVICE_PROP_MAX_TX_SAMPLES:
- val = size_t(_max_num_samples);
- return;
-
default: UHD_THROW_PROP_GET_ERROR();
}
}
@@ -142,7 +134,8 @@ void usrp_e_impl::set(const wax::obj &, const wax::obj &){
size_t usrp_e_impl::send(
const boost::asio::const_buffer &,
const uhd::tx_metadata_t &,
- const io_type_t &
+ const io_type_t &,
+ send_mode_t
){
if (true){
throw std::runtime_error(str(boost::format("usrp-e send: cannot handle type \"%s\"") % ""));
@@ -153,7 +146,8 @@ size_t usrp_e_impl::send(
size_t usrp_e_impl::recv(
const boost::asio::mutable_buffer &,
uhd::rx_metadata_t &,
- const io_type_t &
+ const io_type_t &,
+ recv_mode_t
){
if (true){
throw std::runtime_error(str(boost::format("usrp-e recv: cannot handle type \"%s\"") % ""));
diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp
index 59f80c70c..a2cdbc31e 100644
--- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp
+++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp
@@ -89,8 +89,10 @@ public:
~usrp_e_impl(void);
//the io interface
- size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const uhd::io_type_t &);
- size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const uhd::io_type_t &);
+ size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t);
+ size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t);
+ size_t get_max_send_samps_per_packet(void) const{return _max_num_samples;}
+ size_t get_max_recv_samps_per_packet(void) const{return _max_num_samples;}
private:
static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t);
diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
index 7f35212f4..51a47f061 100644
--- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp
+++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
@@ -78,11 +78,13 @@
#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12
#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14
-// each 2-bit sel field is layed out this way
-#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
-#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
-#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
-#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
+//possible bit values for sel when dbg is 0:
+#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg
+#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
+
+//possible bit values for sel when dbg is 1:
+#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric
////////////////////////////////////////////////////
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 16:27:47 +0000