4 files changed, 22 insertions, 8 deletions
diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp
index 17262d358..a728d7e46 100644
--- a/host/lib/usrp/usrp_e/codec_ctrl.cpp
+++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp
@@ -29,7 +29,7 @@
 
 using namespace uhd;
 
-static const bool codec_debug = true;
+static const bool codec_debug = false;
 
 const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1));
 const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1);
@@ -133,19 +133,23 @@ usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){
 /***********************************************************************
  * Codec Control Gain Control Methods
  **********************************************************************/
+static const int mtpgw = 255; //maximum tx pga gain word
+
 void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){
-    int gain_word = int(255*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min));
-    _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, 255);
+    int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min));
+    _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw);
     this->send_reg(16);
 }
 
 float usrp_e_codec_ctrl_impl::get_tx_pga_gain(void){
-    return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/63) + tx_pga_gain_range.min;
+    return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min;
 }
 
+static const int mrpgw = 0x14; //maximum rx pga gain word
+
 void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){
-    int gain_word = int(0x14*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min));
-    gain_word = std::clip(gain_word, 0, 0x14);
+    int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min));
+    gain_word = std::clip(gain_word, 0, mrpgw);
     switch(which){
     case 'A':
         _ad9862_regs.rx_pga_a = gain_word;
@@ -166,7 +170,7 @@ float usrp_e_codec_ctrl_impl::get_rx_pga_gain(char which){
     case 'B': gain_word = _ad9862_regs.rx_pga_b; break;
     default: UHD_THROW_INVALID_CODE_PATH();
     }
-    return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/0x14) + rx_pga_gain_range.min;
+    return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/mrpgw) + rx_pga_gain_range.min;
 }
 
 /***********************************************************************
diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp
index eaa45d60c..1bb67d9aa 100644
--- a/host/lib/usrp/usrp_e/io_impl.cpp
+++ b/host/lib/usrp/usrp_e/io_impl.cpp
@@ -33,7 +33,7 @@ using namespace uhd::usrp;
  * Constants
  **********************************************************************/
 static const size_t MAX_BUFF_SIZE = 2048;
-static const bool usrp_e_io_impl_verbose = true;
+static const bool usrp_e_io_impl_verbose = false;
 
 /***********************************************************************
  * Data Transport (phony zero-copy with read/write)
diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp
index 3d4cef069..047db3f7c 100644
--- a/host/lib/usrp/usrp_e/mboard_impl.cpp
+++ b/host/lib/usrp/usrp_e/mboard_impl.cpp
@@ -41,6 +41,10 @@ void usrp_e_impl::mboard_init(void){
     _clock_config.pps_source = clock_config_t::PPS_SMA;
 
     //TODO poke the clock config regs
+
+    //setup the tx policy
+    _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, 1);
+    _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET);
 }
 
 /***********************************************************************
diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
index 41cbfa1e2..a4f42093e 100644
--- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp
+++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
@@ -151,6 +151,12 @@
 ////////////////////////////////////////////////
 #define UE_REG_CTRL_TX_NCHANNELS         UE_REG_SR_ADDR(24)
 #define UE_REG_CTRL_TX_CLEAR_UNDERRUN    UE_REG_SR_ADDR(25)
+#define UE_REG_CTRL_TX_REPORT_SID        UE_REG_SR_ADDR(26)
+#define UE_REG_CTRL_TX_POLICY            UE_REG_SR_ADDR(27)
+
+#define UE_FLAG_CTRL_TX_POLICY_WAIT          (0x1 << 0)
+#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET   (0x1 << 1)
+#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST    (0x1 << 2)
 
 /////////////////////////////////////////////////
 // VITA49 64 bit time (write only)