1 files changed, 32 insertions, 3 deletions

diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp
index a430f2c6f..3f3523ddf 100644
--- a/host/lib/usrp/usrp_e/codec_ctrl.cpp
+++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp
@@ -29,6 +29,8 @@
 
 using namespace uhd;
 
+static const bool codec_debug = true;
+
 /***********************************************************************
  * Codec Control Implementation
  **********************************************************************/
@@ -56,6 +58,9 @@ private:
 codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){
     _iface = iface;
 
+    //FIXME temp poke !!!
+    _iface->poke16(UE_REG_MISC_TEST, 0x0f00);
+
     //soft reset
     _ad9862_regs.soft_reset = 1;
     this->send_reg(0);
@@ -65,6 +70,28 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){
     _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB;
     _ad9862_regs.soft_reset = 0;
 
+    //setup rx side of codec
+    _ad9862_regs.byp_buffer_a = 1;
+    _ad9862_regs.byp_buffer_b = 1;
+    _ad9862_regs.buffer_a_pd = 1;
+    _ad9862_regs.buffer_b_pd = 1;
+    _ad9862_regs.rx_pga_a = 0x1f;  //TODO bring under api control
+    _ad9862_regs.rx_pga_b = 0x1f;  //TODO bring under api control
+    _ad9862_regs.rx_twos_comp = 1;
+    _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS;
+
+    //setup tx side of codec
+    _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH;
+    _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_SINGLE; //FIXME should be interleaved
+    _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control
+    _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS;
+    _ad9862_regs.interp = ad9862_regs_t::INTERP_4;
+    _ad9862_regs.tx_twos_comp = 1;
+    _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS;
+    _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS;
+    _ad9862_regs.dac_a_coarse_gain = 0x3;
+    _ad9862_regs.dac_b_coarse_gain = 0x3;
+
     //write the register settings to the codec
     for (uint8_t addr = 0; addr <= 50; addr++){
         this->send_reg(addr);
@@ -72,6 +99,8 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){
 }
 
 codec_ctrl_impl::~codec_ctrl_impl(void){
+    return; //FIXME remove this later
+
     //set aux dacs to zero
     this->write_aux_dac(AUX_DAC_A, 0);
     this->write_aux_dac(AUX_DAC_B, 0);
@@ -181,7 +210,7 @@ void codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){
  **********************************************************************/
 void codec_ctrl_impl::send_reg(boost::uint8_t addr){
     boost::uint32_t reg = _ad9862_regs.get_write_reg(addr);
-    //std::cout << "codec control write reg: " << std::hex << reg << std::endl;
+    if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl;
     _iface->transact_spi(
         UE_SPI_SS_AD9862,
         spi_config_t::EDGE_RISE,
@@ -191,13 +220,13 @@ void codec_ctrl_impl::send_reg(boost::uint8_t addr){
 
 void codec_ctrl_impl::recv_reg(boost::uint8_t addr){
     boost::uint32_t reg = _ad9862_regs.get_read_reg(addr);
-    //std::cout << "codec control read reg: " << std::hex << reg << std::endl;
+    if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl;
     boost::uint32_t ret = _iface->transact_spi(
         UE_SPI_SS_AD9862,
         spi_config_t::EDGE_RISE,
         reg, 16, true /*rb*/
     );
-    //std::cout << "codec control read ret: " << std::hex << ret << std::endl;
+    if (codec_debug) std::cout << "codec control read ret: " << std::hex << ret << std::endl;
     _ad9862_regs.set_reg(addr, boost::uint16_t(ret));
 }