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Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp15
1 files changed, 14 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 1a5864c85..9d306090b 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -107,6 +107,7 @@
#define U2_REG_TIME64_SECS_RB (0xCC00 + 4*10)
#define U2_REG_TIME64_TICKS_RB (0xCC00 + 4*11)
+#define U2_REG_COMPAT_NUM_RB (0xCC00 + 4*12)
//pps flags (see above)
#define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
@@ -226,7 +227,7 @@
#define U2_REG_ATR_FULL_RXSIDE U2_REG_ATR_BASE + 14
///////////////////////////////////////////////////
-// VITA RX CTRL regs
+// RX CTRL regs
///////////////////////////////////////////////////
// The following 3 are logically a single command register.
// They are clocked into the underlying fifo when time_ticks is written.
@@ -241,4 +242,16 @@
#define U2_REG_RX_CTRL_NSAMPS_PER_PKT _SR_ADDR(SR_RX_CTRL + 7)
#define U2_REG_RX_CTRL_NCHANNELS _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources
+///////////////////////////////////////////////////
+// TX CTRL regs
+///////////////////////////////////////////////////
+#define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0)
+#define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1)
+#define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2)
+#define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3)
+
+#define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0)
+#define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1)
+#define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2)
+
#endif /* INCLUDED_USRP2_REGS_HPP */