diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/lib/control/Makefile.srcs | 1 | ||||
| -rw-r--r-- | fpga/usrp3/lib/control/glitch_free_mux.v | 29 |
2 files changed, 30 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/control/Makefile.srcs b/fpga/usrp3/lib/control/Makefile.srcs index 7388eb8cb..9a24f44fa 100644 --- a/fpga/usrp3/lib/control/Makefile.srcs +++ b/fpga/usrp3/lib/control/Makefile.srcs @@ -61,4 +61,5 @@ map/axis_muxed_kv_map.v \ axil_ctrlport_master.v\ handshake.v\ ctrlport_to_regport.v \ +glitch_free_mux.v \ )) diff --git a/fpga/usrp3/lib/control/glitch_free_mux.v b/fpga/usrp3/lib/control/glitch_free_mux.v new file mode 100644 index 000000000..e2f4dc177 --- /dev/null +++ b/fpga/usrp3/lib/control/glitch_free_mux.v @@ -0,0 +1,29 @@ +// +// Copyright 2020 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: glitch_free_mux +// +// Description: +// This module implements a 2:1 mux in a LUT explicitly to avoid glitches +// which can be introduced by unexpected Vivado synthesis. +// + +module glitch_free_mux ( + input wire select, + input wire signal0, + input wire signal1, + output wire muxed_signal +); + + (* dont_touch = "TRUE" *) LUT3 #( + .INIT(8'hCA) // Specify LUT Contents. O = ~I2&I0 | I2&I1 + ) mux_out_i ( + .O (muxed_signal), // LUT general output. Mux output + .I0(signal0), // LUT input. Input 1 + .I1(signal1), // LUT input. Input 2 + .I2(select) // LUT input. Select bit + ); + +endmodule |