1 files changed, 23 insertions, 2 deletions
diff --git a/fpga/usrp3/lib/timing/pps_generator.v b/fpga/usrp3/lib/timing/pps_generator.v
index 9142c3a48..288fdccb9 100644
--- a/fpga/usrp3/lib/timing/pps_generator.v
+++ b/fpga/usrp3/lib/timing/pps_generator.v
@@ -7,7 +7,8 @@
 
 module pps_generator #(
    parameter CLK_FREQ   = 32'd10_000_000, //Min:10kHz, Max:4GHz
-   parameter DUTY_CYCLE = 25
+   parameter DUTY_CYCLE = 25,
+   parameter PIPELINE   = "NONE" // Optional register on output? {"NONE", "OUT"}
 ) (
    input  clk,
    input  reset,
@@ -25,5 +26,25 @@ module pps_generator #(
         end
     end
 
-    assign pps = (count < ((CLK_FREQ / 100) * DUTY_CYCLE));
+    wire pps_int;
+    assign pps_int = (count < ((CLK_FREQ / 100) * DUTY_CYCLE));
+
+    generate
+      if (PIPELINE == "OUT") begin : gen_pipeline_out
+        // create output register and assign to output
+        reg pps_reg = 1'b0;
+        assign pps = pps_reg;
+
+        always @(posedge clk) begin
+          if (reset) begin
+            pps_reg <= 1'b0;
+          end else begin
+            pps_reg <= pps_int;
+          end
+        end
+      end else begin : gen_pipeline_none
+        // no output register
+        assign pps = pps_int;
+      end
+    endgenerate
 endmodule //pps_generator