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-rw-r--r--fpga/usrp3/top/x400/x410_100_rfnoc_image_core.yml116
-rw-r--r--fpga/usrp3/top/x400/x410_200_rfnoc_image_core.yml104
-rw-r--r--fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.yml72
-rw-r--r--fpga/usrp3/top/x400/x410_400_rfnoc_image_core.yml70
4 files changed, 188 insertions, 174 deletions
diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.yml
index 54ac97a29..69f53ea7f 100644
--- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.yml
@@ -1,8 +1,10 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
-copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
-license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
+copyright: >- # Copyright information used in file headers
+ Ettus Research, A National Instruments Brand
+license: >- # License information used in file headers
+ SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
rfnoc_version: '1.0' # RFNoC protocol version
chdr_width: 64 # Bit width of the CHDR bus for this image
@@ -13,10 +15,10 @@ default_target: 'X410_XG_100' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
- ep0: # Stream endpoint name
- ctrl: True # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 262144 # Ingress buffer size for data
+ ep0: # Stream endpoint name
+ ctrl: True # Endpoint passes control traffic
+ data: True # Endpoint passes data traffic
+ buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
ctrl: False
data: True
@@ -49,8 +51,8 @@ stream_endpoints:
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
- duc0: # NoC block name
- block_desc: 'duc.yml' # Block device descriptor file
+ duc0: # NoC block name
+ block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 2
ddc0:
@@ -85,63 +87,63 @@ noc_blocks:
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
-# - srcblk = Source block to connect
-# - srcport = Port on the source block to connect
-# - dstblk = Destination block to connect
-# - dstport = Port on the destination block to connect
+# - srcblk = Source block to connect
+# - srcport = Port on the source block to connect
+# - dstblk = Destination block to connect
+# - dstport = Port on the destination block to connect
connections:
- # ep0 to radio0(0) - RFA:0 TX
- - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
- # radio0(0) to ep0 - RFA:0 RX
- - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
- # ep1 to radio0(1) - RFA:1 TX
- - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
- - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
- # radio0(1) to ep1 - RFA:1 RX
- - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
+ # RF A:0 TX
+ - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
+ - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
+ # RF A:0 RX
+ - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
+ - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
+ # RF A:1 TX
+ - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
+ - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
+ # RF A:1 RX
+ - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
+ - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
- # ep2 to radio1(0) - RFB:0 TX
- - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
- # radio1(0) to ep2 - RFB:0 RX
- - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
- # ep3 to radio1(1) - RFB:1 TX
- - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
- - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
- # radio1(1) to ep3 - RFB:1 RX
- - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
+ # RF B:0 TX
+ - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
+ - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
+ # RF B:0 RX
+ - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
+ - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
+ # RF B:1 TX
+ - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
+ - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
+ # RF B:1 RX
+ - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
+ - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
- # Replay
- - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- - { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
- - { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
- - { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
- - { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
+ # Replay Connections
+ - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
+ - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
+ - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
+ - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
+ - { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
+ - { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
+ - { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
+ - { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
+ - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
+ - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
+ - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
+ - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
+ - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
+ - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
+ - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
-# ------------------------------------------
+# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
-# - srcblk = Source block to connect (Always "_device"_)
-# - srcport = Clock domain on the source block to connect
-# - dstblk = Destination block to connect
-# - dstport = Clock domain on the destination block to connect
+# - srcblk = Source block to connect (Always "_device"_)
+# - srcport = Clock domain on the source block to connect
+# - dstblk = Destination block to connect
+# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce }
diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.yml
index ddc028b0c..fcad44768 100644
--- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.yml
@@ -1,8 +1,10 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
-copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
-license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
+copyright: >- # Copyright information used in file headers
+ Ettus Research, A National Instruments Brand
+license: >- # License information used in file headers
+ SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
rfnoc_version: '1.0' # RFNoC protocol version
chdr_width: 64 # Bit width of the CHDR bus for this image
@@ -13,10 +15,10 @@ default_target: 'X410_X4_200' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
- ep0: # Stream endpoint name
- ctrl: True # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 262144 # Ingress buffer size for data
+ ep0: # Stream endpoint name
+ ctrl: True # Endpoint passes control traffic
+ data: True # Endpoint passes data traffic
+ buff_size_bytes: 262144 # Ingress buffer size for data
ep1:
ctrl: False
data: True
@@ -49,8 +51,8 @@ stream_endpoints:
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
- duc0: # NoC block name
- block_desc: 'duc.yml' # Block device descriptor file
+ duc0: # NoC block name
+ block_desc: 'duc.yml' # Block device descriptor file
parameters:
NUM_PORTS: 2
ddc0:
@@ -85,63 +87,63 @@ noc_blocks:
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
-# - srcblk = Source block to connect
-# - srcport = Port on the source block to connect
-# - dstblk = Destination block to connect
-# - dstport = Port on the destination block to connect
+# - srcblk = Source block to connect
+# - srcport = Port on the source block to connect
+# - dstblk = Destination block to connect
+# - dstport = Port on the destination block to connect
connections:
- # ep0 to radio0(0) - RFA:0 TX
- - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
- - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
- # radio0(0) to ep0 - RFA:0 RX
- - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
- # ep1 to radio0(1) - RFA:1 TX
- - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
- - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
- # radio0(1) to ep1 - RFA:1 RX
- - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
- - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
+ # RF A:0 TX
+ - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
+ - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
+ # RF A:0 RX
+ - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
+ - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
+ # RF A:1 TX
+ - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
+ - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
+ # RF A:1 RX
+ - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
+ - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
- # ep2 to radio1(0) - RFB:0 TX
- - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
- - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
- # radio1(0) to ep2 - RFB:0 RX
- - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
- - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
- # ep3 to radio1(1) - RFB:1 TX
- - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
- - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
- # radio1(1) to ep3 - RFB:1 RX
- - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
- - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
+ # RF B:0 TX
+ - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
+ - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
+ # RF B:0 RX
+ - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
+ - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
+ # RF B:1 TX
+ - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
+ - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
+ # RF B:1 RX
+ - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
+ - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
- # Replay
- - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- - { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
- - { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
- - { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
- - { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
+ # Replay Connections
+ - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
+ - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
+ - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
+ - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
+ - { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
+ - { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
+ - { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
+ - { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
+ - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
-# ------------------------------------------
+# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
-# - srcblk = Source block to connect (Always "_device"_)
-# - srcport = Clock domain on the source block to connect
-# - dstblk = Destination block to connect
-# - dstport = Clock domain on the destination block to connect
+# - srcblk = Source block to connect (Always "_device"_)
+# - srcport = Clock domain on the source block to connect
+# - dstblk = Destination block to connect
+# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio_2x, dstblk: duc0, dstport: ce }
diff --git a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.yml
index 4c6f4a62e..a2a86e6a1 100644
--- a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.yml
@@ -1,22 +1,24 @@
# General parameters
# -----------------------------------------
-schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
-copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
-license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
-version: '1.0' # File version
-rfnoc_version: '1.0' # RFNoC protocol version
-chdr_width: 128 # Bit width of the CHDR bus for this image
-device: 'x410' # USRP type
-image_core_name: 'x410_400_128' # Name to use for the RFNoC Image Core files
-default_target: 'X410_X4_400' # Default make target
+schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
+copyright: >- # Copyright information used in file headers
+ Ettus Research, A National Instruments Brand
+license: >- # License information used in file headers
+ SPDX-License-Identifier: LGPL-3.0-or-later
+version: '1.0' # File version
+rfnoc_version: '1.0' # RFNoC protocol version
+chdr_width: 128 # Bit width of the CHDR bus for this image
+device: 'x410' # USRP type
+image_core_name: 'x410_400_128' # Name to use for the RFNoC Image Core files
+default_target: 'X410_X4_400' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
- ep0: # Stream endpoint name
- ctrl: True # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 32768 # Stream endpoint buffer size
+ ep0: # Stream endpoint name
+ ctrl: True # Endpoint passes control traffic
+ data: True # Endpoint passes data traffic
+ buff_size_bytes: 32768 # Stream endpoint buffer size
ep1:
ctrl: False
data: True
@@ -69,24 +71,30 @@ noc_blocks:
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
-# - srcblk = Source block to connect
-# - srcport = Port on the source block to connect
-# - dstblk = Destination block to connect
-# - dstport = Port on the destination block to connect
+# - srcblk = Source block to connect
+# - srcport = Port on the source block to connect
+# - dstblk = Destination block to connect
+# - dstport = Port on the destination block to connect
connections:
- # Daughter Board 0 Radio
- - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
- - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
- - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
- - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
+ # RF A:0 TX
+ - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
+ # RF A:0 RX
+ - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
+ # RF A:1 TX
+ - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
+ # RF A:1 RX
+ - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
- # Daughter Board 1 Radio
- - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
- - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
- - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
- - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
+ # RF B:0 TX
+ - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
+ # RF B:0 RX
+ - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
+ # RF B:1 TX
+ - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
+ # RF B:1 RX
+ - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
- # Replay
+ # Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
@@ -108,10 +116,10 @@ connections:
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
-# - srcblk = Source block to connect (Always "_device_")
-# - srcport = Clock domain on the source block to connect
-# - dstblk = Destination block to connect
-# - dstport = Clock domain on the destination block to connect
+# - srcblk = Source block to connect (Always "_device_")
+# - srcport = Clock domain on the source block to connect
+# - dstblk = Destination block to connect
+# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.yml b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.yml
index edcdd4c66..000d5976a 100644
--- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.yml
@@ -1,8 +1,10 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
-copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
-license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
+copyright: >- # Copyright information used in file headers
+ Ettus Research, A National Instruments Brand
+license: >- # License information used in file headers
+ SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
rfnoc_version: '1.0' # RFNoC protocol version
chdr_width: 512 # Bit width of the CHDR bus for this image
@@ -13,22 +15,22 @@ default_target: 'X410_CG_400' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
- ep0: # Stream endpoint name
- ctrl: True # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 524288 # Ingress buffer size for data
- ep1: # Stream endpoint name
- ctrl: False # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 524288 # Ingress buffer size for data
- ep2: # Stream endpoint name
- ctrl: False # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 524288 # Ingress buffer size for data
- ep3: # Stream endpoint name
- ctrl: False # Endpoint passes control traffic
- data: True # Endpoint passes data traffic
- buff_size_bytes: 524288 # Ingress buffer size for data
+ ep0: # Stream endpoint name
+ ctrl: True # Endpoint passes control traffic
+ data: True # Endpoint passes data traffic
+ buff_size_bytes: 524288 # Ingress buffer size for data
+ ep1:
+ ctrl: False
+ data: True
+ buff_size_bytes: 524288
+ ep2:
+ ctrl: False
+ data: True
+ buff_size_bytes: 524288
+ ep3:
+ ctrl: False
+ data: True
+ buff_size_bytes: 524288
# A list of all NoC blocks in design
# ----------------------------------
@@ -52,23 +54,23 @@ noc_blocks:
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
- # ep0 to radio0(0) - RFA:0 TX
- - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
- # radio0(0) to ep0 - RFA:0 RX
- - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
- # ep1 to radio0(1) - RFA:1 TX
- - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
- # radio0(1) to ep1 - RFA:1 RX
- - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
+ # RF A:0 TX
+ - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
+ # RF A:0 RX
+ - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
+ # RF A:1 TX
+ - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
+ # RF A:1 RX
+ - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
- # ep2 to radio1(0) - RFB:0 TX
- - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
- # radio1(0) to ep2 - RFB:0 RX
- - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
- # ep3 to radio1(1) - RFB:1 TX
- - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
- # radio1(1) to ep3 - RFB:1 RX
- - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
+ # RF B:0 TX
+ - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
+ # RF B:0 RX
+ - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
+ # RF B:1 TX
+ - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
+ # RF B:1 RX
+ - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
generated by cgit v1.2.3 (git 2.46.0) at 2025-11-04 07:03:59 +0000