diff options
Diffstat (limited to 'fpga/usrp3/top/x400/ip')
64 files changed, 17032 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/ip/Makefile.inc b/fpga/usrp3/top/x400/ip/Makefile.inc new file mode 100644 index 000000000..7904740f9 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/Makefile.inc @@ -0,0 +1,87 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(IP_DIR)/xge_pcs_pma/Makefile.inc +include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc +include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc +include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc +include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc +include $(IP_DIR)/ddr4_64bits/Makefile.inc +include $(IP_DIR)/adc_100m_bd/Makefile.inc +include $(IP_DIR)/adc_400m_bd/Makefile.inc +include $(IP_DIR)/dac_100m_bd/Makefile.inc +include $(IP_DIR)/dac_400m_bd/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/eth_100g_bd/Makefile.inc +include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc +include $(IP_DIR)/hb47_1to2/Makefile.inc +include $(IP_DIR)/hb47_2to1/Makefile.inc + +BD_SRCS = \ +$(IP_X4XX_PS_RFDC_BD_SRCS) \ +$(IP_X4XX_PS_RFDC_HDL_SRCS) \ +$(IP_AXI_INTERCONNECT_APP_BD_SRCS) \ +$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \ +$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \ +$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \ +$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \ +$(IP_ADC_100M_BD_SRCS) \ +$(IP_ADC_100M_HDL_SRCS) \ +$(IP_DAC_100M_BD_SRCS) \ +$(IP_DAC_100M_HDL_SRCS) \ +$(IP_ADC_400M_BD_SRCS) \ +$(IP_ADC_400M_HDL_SRCS) \ +$(IP_DAC_400M_BD_SRCS) \ +$(IP_DAC_400M_HDL_SRCS) \ +$(IP_100G_BD_SRCS) \ +$(IP_100G_HDL_SRCS) \ +$(IP_AXI_ETH_DMA_BD_SRCS) \ +$(IP_AXI_ETH_DMA_BD_HDL_SRCS) + +IP_XCI_SRCS = \ +$(IP_DDR4_64BITS_SRCS) \ +$(IP_XGE_PCS_PMA_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_HB47_1TO2_SRCS) \ +$(IP_HB47_2TO1_SRCS) \ + +BD_OUTPUTS = \ +$(BD_X4XX_PS_RFDC_BD_OUTS) \ +$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \ +$(BD_AXI_INTERCONNECT_ETH_BD_OUTS) \ +$(BD_AXI_INTERCONNECT_DMA_BD_OUTS) \ +$(BD_ADC_100M_BD_OUTS) \ +$(BD_ADC_400M_BD_OUTS) \ +$(BD_DAC_100M_BD_OUTS) \ +$(BD_DAC_400M_BD_OUTS) \ +$(BD_100G_BD_OUTS) \ +$(BD_AXI_ETH_DMA_BD_OUTS) + +IP_SYNTH_OUTPUTS = \ +$(IP_DDR4_64BITS_OUTS) \ +$(IP_XGE_PCS_PMA_OUTS) \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_HB47_1TO2_OUTS) \ +$(IP_HB47_2TO1_OUTS) \ + +IP_HDL_SIM_SRCS = \ +$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \ +$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \ +$(IP_FIFO_SHORT_2CLK_HDL_SIM_SRCS) \ +$(IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS) \ +$(IP_AXI_INTERCONNECT_DMA_HDL_SIM_SRCS) \ +$(IP_100G_HDL_SIM_SRCS) \ +$(IP_XGE_PCS_PMA_HDL_SIM_SRCS) + +ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS) + +.PHONY: ip diff --git a/fpga/usrp3/top/x400/ip/adc_100m_bd/.gitignore b/fpga/usrp3/top/x400/ip/adc_100m_bd/.gitignore new file mode 100644 index 000000000..49f7d3710 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_100m_bd/.gitignore @@ -0,0 +1 @@ +synthstub/ diff --git a/fpga/usrp3/top/x400/ip/adc_100m_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/adc_100m_bd/Makefile.inc new file mode 100644 index 000000000..91130f5ad --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_100m_bd/Makefile.inc @@ -0,0 +1,38 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_ADC_100M_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_100m_bd/, \ +adc_100m_bd.tcl \ +) + +IP_ADC_100M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \ +100m/ddc_saturate.vhd \ +100m/adc_3_1_clk_converter.vhd \ +100m/adc_gearbox_2x1.v \ +common/PkgRf.vhd \ +common/scale_2x.vhd \ +) + +IP_ADC_100M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_100m_bd/, \ +adc_100m_bd.tcl \ +) + +IP_ADC_100M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_100m_bd/, \ +adc_100m_bd/adc_100m_bd.bd \ +) + +BD_ADC_100M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_100m_bd/, \ +adc_100m_bd.bd.out \ +adc_100m_bd/adc_100m_bd_ooc.xdc \ +adc_100m_bd/synth/adc_100m_bd.v \ +) + +EMPTY_IP_SRCS = + +$(IP_ADC_100M_BD_SRCS) $(BD_ADC_100M_BD_OUTS) $(IP_ADC_100M_BDTCL_SRCS): $(IP_ADC_100M_ORIG_SRCS) $(IP_ADC_100M_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,adc_100m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_100M_HDL_SRCS),) diff --git a/fpga/usrp3/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl b/fpga/usrp3/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl new file mode 100644 index 000000000..a3fcc6edc --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl @@ -0,0 +1,435 @@ + +################################################################ +# This is a generated script based on design: adc_100m_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source adc_100m_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# adc_3_1_clk_converter, adc_gearbox_2x1, ddc_saturate, scale_2x + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name adc_100m_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + + # Add USER_COMMENTS on $design_name + set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name] + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axis_register_slice:1.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:fir_compiler:7.2\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +adc_3_1_clk_converter\ +adc_gearbox_2x1\ +ddc_saturate\ +scale_2x\ +" + + set list_mods_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {122880000} \ + ] $adc_data_out + + set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {4} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $adc_i_data_in + + set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {4} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $adc_q_data_in + + + # Create ports + set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ] + set data_clk [ create_bd_port -dir I -type clk data_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {adc_data_out} \ + CONFIG.FREQ_HZ {122880000} \ + ] $data_clk + set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ] + set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ] + set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ] + set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {adc_i_data_in:adc_q_data_in} \ + CONFIG.ASSOCIATED_RESET {adc_gearbox_resetn_rclk:rfdc_adc_axi_resetn_rclk} \ + CONFIG.FREQ_HZ {184320000} \ + ] $rfdc_clk + set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {368640000} \ + ] $rfdc_clk_2x + set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ] + + # Create instance: adc_3_1_clk_converter_0, and set properties + set block_name adc_3_1_clk_converter + set block_cell_name adc_3_1_clk_converter_0 + if { [catch {set adc_3_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $adc_3_1_clk_converter_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: adc_data_to_axi, and set properties + set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {4} \ + ] $adc_data_to_axi + + # Create instance: adc_gearbox_2x1_0, and set properties + set block_name adc_gearbox_2x1 + set block_cell_name adc_gearbox_2x1_0 + if { [catch {set adc_gearbox_2x1_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $adc_gearbox_2x1_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: adc_i_data_from_axi, and set properties + set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {0} \ + CONFIG.TDATA_NUM_BYTES {4} \ + ] $adc_i_data_from_axi + + # Create instance: adc_q_data_from_axi, and set properties + set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {0} \ + CONFIG.TDATA_NUM_BYTES {4} \ + ] $adc_q_data_from_axi + + # Create instance: const_1, and set properties + set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] + + # Create instance: ddc_saturate, and set properties + set block_name ddc_saturate + set block_cell_name ddc_saturate + if { [catch {set ddc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $ddc_saturate eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: fir_compiler_0, and set properties + set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ] + set_property -dict [ list \ + CONFIG.Clock_Frequency {384} \ + CONFIG.CoefficientVector {-2,0,8,12,0,-26,-36,0,63,81,0,-130,-161,0,241,291,0,-415,-491,0,676,788,0,-1059,-1223,0,1621,1864,0,-2473,-2860,0,3892,4607,0,-6820,-8705,0,17900,36048,43690,36048,17900,0,-8705,-6820,0,4607,3892,0,-2860,-2473,0,1864,1621,0,-1223,-1059,0,788,676,0,-491,-415,0,291,241,0,-161,-130,0,81,63,0,-36,-26,0,12,8,0,-2} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Sets {1} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Coefficient_Structure {Non_Symmetric} \ + CONFIG.Coefficient_Width {18} \ + CONFIG.ColumnConfig {27} \ + CONFIG.Data_Fractional_Bits {0} \ + CONFIG.Data_Width {16} \ + CONFIG.Decimation_Rate {3} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.Filter_Type {Decimation} \ + CONFIG.Has_ARESETn {true} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.M_DATA_Has_TREADY {false} \ + CONFIG.Number_Channels {1} \ + CONFIG.Number_Paths {2} \ + CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \ + CONFIG.Output_Width {17} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.RateSpecification {Frequency_Specification} \ + CONFIG.Reset_Data_Vector {true} \ + CONFIG.S_DATA_Has_FIFO {false} \ + CONFIG.Sample_Frequency {384} \ + CONFIG.Zero_Pack_Factor {1} \ + ] $fir_compiler_0 + + # Create instance: scale_2x_0, and set properties + set block_name scale_2x + set block_cell_name scale_2x_0 + if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $scale_2x_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + set_property -dict [ list \ + CONFIG.kDataWidth {32} \ + ] $scale_2x_0 + + # Create interface connections + connect_bd_intf_net -intf_net adc_data_combine_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS] + connect_bd_intf_net -intf_net adc_i_axi_data_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS] + connect_bd_intf_net -intf_net adc_q_axi_data_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS] + connect_bd_intf_net -intf_net fir_compiler_0_M_AXIS_DATA [get_bd_intf_pins adc_3_1_clk_converter_0/s_axis] [get_bd_intf_pins fir_compiler_0/M_AXIS_DATA] + + # Create port connections + connect_bd_net -net adc_3_1_clk_converter_0_m_axis_tdata [get_bd_pins adc_3_1_clk_converter_0/m_axis_tdata] [get_bd_pins ddc_saturate/cDataIn] + connect_bd_net -net adc_3_1_clk_converter_0_m_axis_tvalid [get_bd_pins adc_3_1_clk_converter_0/m_axis_tvalid] [get_bd_pins ddc_saturate/cDataValidIn] + connect_bd_net -net adc_data_out_resetn_dclk_1 [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins adc_3_1_clk_converter_0/m_axis_resetn] [get_bd_pins adc_data_to_axi/aresetn] + connect_bd_net -net adc_gearbox_2x1_0_adc_data_out_2x [get_bd_pins adc_gearbox_2x1_0/adc_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tdata] + connect_bd_net -net adc_gearbox_2x1_0_rfi_1x [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout] + connect_bd_net -net adc_gearbox_2x1_0_valid_out_2x [get_bd_pins adc_gearbox_2x1_0/valid_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tvalid] + connect_bd_net -net adc_q_data_breakout_m_axis_tdata [get_bd_pins adc_gearbox_2x1_0/adc_q_in_1x] [get_bd_pins adc_q_data_from_axi/m_axis_tdata] + connect_bd_net -net aresetn_0_1 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins adc_3_1_clk_converter_0/s_axis_resetn] [get_bd_pins fir_compiler_0/aresetn] + connect_bd_net -net axis_register_slice_0_m_axis_tdata [get_bd_pins adc_gearbox_2x1_0/adc_i_in_1x] [get_bd_pins adc_i_data_from_axi/m_axis_tdata] + connect_bd_net -net axis_register_slice_0_m_axis_tvalid [get_bd_pins adc_gearbox_2x1_0/valid_in_1x] [get_bd_pins adc_i_data_from_axi/m_axis_tvalid] + connect_bd_net -net data_clock_mmcm_data_clk [get_bd_ports data_clk] [get_bd_pins adc_3_1_clk_converter_0/m_axis_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins ddc_saturate/Clk] + connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_ports rfdc_clk] [get_bd_pins adc_gearbox_2x1_0/clk1x] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_q_data_from_axi/aclk] + connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_ports rfdc_clk_2x] [get_bd_pins adc_3_1_clk_converter_0/s_axis_clk] [get_bd_pins adc_gearbox_2x1_0/clk2x] [get_bd_pins fir_compiler_0/aclk] + connect_bd_net -net ddc_saturate_cDataOut [get_bd_pins ddc_saturate/cDataOut] [get_bd_pins scale_2x_0/cDataIn] + connect_bd_net -net ddc_saturate_cDataValidOut [get_bd_pins ddc_saturate/cDataValidOut] [get_bd_pins scale_2x_0/cDataValidIn] + connect_bd_net -net enable_data_to_fir_rclk_1 [get_bd_ports enable_data_to_fir_rclk] [get_bd_pins adc_gearbox_2x1_0/enable_1x] + connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_gearbox_2x1_0/reset_n_1x] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn] + connect_bd_net -net scale_2x_0_cDataOut [get_bd_pins adc_data_to_axi/s_axis_tdata] [get_bd_pins scale_2x_0/cDataOut] + connect_bd_net -net scale_2x_0_cDataValidOut [get_bd_pins adc_data_to_axi/s_axis_tvalid] [get_bd_pins scale_2x_0/cDataValidOut] + connect_bd_net -net swap_iq_2x_1 [get_bd_ports swap_iq_2x] [get_bd_pins adc_gearbox_2x1_0/swap_iq_2x] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/adc_100m_bd/hdl_sources.tcl b/fpga/usrp3/top/x400/ip/adc_100m_bd/hdl_sources.tcl new file mode 100644 index 000000000..770a4c041 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_100m_bd/hdl_sources.tcl @@ -0,0 +1,10 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +# Vivado's block diagram default library for files not belonging to any special +# library is called xil_defaultlib +read_verilog -library xil_defaultlib $script_dir/../../rf/100m/adc_gearbox_2x1.v +read_vhdl -library xil_defaultlib $script_dir/../../rf/100m/ddc_saturate.vhd +read_vhdl -library xil_defaultlib $script_dir/../../rf/100m/adc_3_1_clk_converter.vhd +read_vhdl -library xil_defaultlib $script_dir/../../rf/common/PkgRf.vhd +read_vhdl -library xil_defaultlib $script_dir/../../rf/common/scale_2x.vhd diff --git a/fpga/usrp3/top/x400/ip/adc_400m_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/adc_400m_bd/Makefile.inc new file mode 100644 index 000000000..658ee13fb --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_400m_bd/Makefile.inc @@ -0,0 +1,38 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_ADC_400M_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_400m_bd/, \ +adc_400m_bd.tcl \ +) + +IP_ADC_400M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \ +400m/ddc_400m_saturate.vhd \ +400m/adc_gearbox_8x4.v \ +400m/adc_gearbox_2x4.vhd \ +common/PkgRf.vhd \ +common/scale_2x.vhd \ +) + +IP_ADC_400M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_400m_bd/, \ +adc_400m_bd.tcl \ +) + +IP_ADC_400M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_400m_bd/, \ +adc_400m_bd/adc_400m_bd.bd \ +) + +BD_ADC_400M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_400m_bd/, \ +adc_400m_bd.bd.out \ +adc_400m_bd/adc_400m_bd_ooc.xdc \ +adc_400m_bd/synth/adc_400m_bd.v \ +) + +EMPTY_IP_SRCS = + +$(IP_ADC_400M_BD_SRCS) $(BD_ADC_400M_BD_OUTS) $(IP_ADC_400M_BDTCL_SRCS): $(IP_ADC_400M_ORIG_SRCS) $(IP_ADC_400M_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,adc_400m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_400M_HDL_SRCS),) diff --git a/fpga/usrp3/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl b/fpga/usrp3/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl new file mode 100644 index 000000000..59ed94947 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl @@ -0,0 +1,432 @@ + +################################################################ +# This is a generated script based on design: adc_400m_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source adc_400m_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# adc_gearbox_2x4, adc_gearbox_8x4, ddc_400m_saturate, scale_2x + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name adc_400m_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + + # Add USER_COMMENTS on $design_name + set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name] + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axis_register_slice:1.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:fir_compiler:7.2\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +adc_gearbox_2x4\ +adc_gearbox_8x4\ +ddc_400m_saturate\ +scale_2x\ +" + + set list_mods_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {122880000} \ + ] $adc_data_out + + set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {16} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $adc_i_data_in + + set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {16} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $adc_q_data_in + + + # Create ports + set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ] + set data_clk [ create_bd_port -dir I -type clk data_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {adc_data_out_resetn_dclk} \ + CONFIG.FREQ_HZ {122880000} \ + ] $data_clk + set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ] + set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ] + set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ] + set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $rfdc_clk + set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {fir_resetn_rclk2x} \ + CONFIG.FREQ_HZ {368640000} \ + ] $rfdc_clk_2x + set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ] + + # Create instance: adc_data_to_axi, and set properties + set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ] + set_property -dict [ list \ + CONFIG.HAS_TREADY {0} \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {16} \ + ] $adc_data_to_axi + + # Create instance: adc_gearbox_2x4_0, and set properties + set block_name adc_gearbox_2x4 + set block_cell_name adc_gearbox_2x4_0 + if { [catch {set adc_gearbox_2x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $adc_gearbox_2x4_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: adc_gearbox_8x4_0, and set properties + set block_name adc_gearbox_8x4 + set block_cell_name adc_gearbox_8x4_0 + if { [catch {set adc_gearbox_8x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $adc_gearbox_8x4_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: adc_i_data_from_axi, and set properties + set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {0} \ + CONFIG.TDATA_NUM_BYTES {16} \ + ] $adc_i_data_from_axi + + # Create instance: adc_q_data_from_axi, and set properties + set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {0} \ + CONFIG.TDATA_NUM_BYTES {16} \ + ] $adc_q_data_from_axi + + # Create instance: const_1, and set properties + set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] + + # Create instance: ddc_400m_saturate_0, and set properties + set block_name ddc_400m_saturate + set block_cell_name ddc_400m_saturate_0 + if { [catch {set ddc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $ddc_400m_saturate_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: fir_compiler_0, and set properties + set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ] + set_property -dict [ list \ + CONFIG.Clock_Frequency {384} \ + CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Sets {1} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Coefficient_Width {18} \ + CONFIG.ColumnConfig {26} \ + CONFIG.Decimation_Rate {3} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.Filter_Type {Decimation} \ + CONFIG.Has_ARESETn {true} \ + CONFIG.Interpolation_Rate {1} \ + CONFIG.Number_Channels {1} \ + CONFIG.Number_Paths {2} \ + CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \ + CONFIG.Output_Width {17} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.RateSpecification {Frequency_Specification} \ + CONFIG.Reset_Data_Vector {false} \ + CONFIG.S_DATA_Has_FIFO {false} \ + CONFIG.Sample_Frequency {1536} \ + CONFIG.Zero_Pack_Factor {1} \ + ] $fir_compiler_0 + + # Create instance: scale_2x_0, and set properties + set block_name scale_2x + set block_cell_name scale_2x_0 + if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $scale_2x_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + set_property -dict [ list \ + CONFIG.kDataWidth {128} \ + ] $scale_2x_0 + + # Create interface connections + connect_bd_intf_net -intf_net S_AXIS_0_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS] + connect_bd_intf_net -intf_net S_AXIS_0_2 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS] + connect_bd_intf_net -intf_net adc_data_to_axi_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS] + + # Create port connections + connect_bd_net -net aclk_0_3 [get_bd_ports rfdc_clk_2x] [get_bd_pins adc_gearbox_2x4_0/Clk3x] [get_bd_pins adc_gearbox_8x4_0/clk2x] [get_bd_pins fir_compiler_0/aclk] + connect_bd_net -net adc_data_out_resetn_dclk [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_gearbox_2x4_0/ac1Reset_n] + connect_bd_net -net adc_gearbox_2x4_0_c1DataOut [get_bd_pins adc_gearbox_2x4_0/c1DataOut] [get_bd_pins ddc_400m_saturate_0/cDataIn] + connect_bd_net -net adc_gearbox_2x4_0_c1DataValidOut [get_bd_pins adc_gearbox_2x4_0/c1DataValidOut] [get_bd_pins ddc_400m_saturate_0/cDataValidIn] + connect_bd_net -net adc_gearbox_8x4_0_adc_out_2x [get_bd_pins adc_gearbox_8x4_0/adc_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tdata] + connect_bd_net -net adc_gearbox_8x4_0_valid_out_2x [get_bd_pins adc_gearbox_8x4_0/valid_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tvalid] + connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_gearbox_8x4_0/adc_i_in_1x] [get_bd_pins adc_i_data_from_axi/m_axis_tdata] + connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_gearbox_8x4_0/adc_q_in_1x] [get_bd_pins adc_q_data_from_axi/m_axis_tdata] + connect_bd_net -net adc_q_data_from_axi_m_axis_tvalid [get_bd_pins adc_gearbox_8x4_0/valid_in_1x] [get_bd_pins adc_q_data_from_axi/m_axis_tvalid] + connect_bd_net -net aresetn_0_1 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins adc_gearbox_2x4_0/ac3Reset_n] [get_bd_pins fir_compiler_0/aresetn] + connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout] + connect_bd_net -net data_clk_1 [get_bd_ports data_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_gearbox_2x4_0/Clk1x] [get_bd_pins ddc_400m_saturate_0/Clk] + connect_bd_net -net ddc_400m_saturate_0_cDataOut [get_bd_pins ddc_400m_saturate_0/cDataOut] [get_bd_pins scale_2x_0/cDataIn] + connect_bd_net -net ddc_400m_saturate_0_cDataValidOut [get_bd_pins ddc_400m_saturate_0/cDataValidOut] [get_bd_pins scale_2x_0/cDataValidIn] + connect_bd_net -net enable_1x_0_1 [get_bd_ports enable_data_to_fir_rclk] [get_bd_pins adc_gearbox_8x4_0/enable_1x] + connect_bd_net -net fir_compiler_0_m_axis_data_tdata [get_bd_pins adc_gearbox_2x4_0/c3DataIn] [get_bd_pins fir_compiler_0/m_axis_data_tdata] + connect_bd_net -net fir_compiler_0_m_axis_data_tvalid [get_bd_pins adc_gearbox_2x4_0/c3DataValidIn] [get_bd_pins fir_compiler_0/m_axis_data_tvalid] + connect_bd_net -net reset_n_1x_0_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_gearbox_8x4_0/reset_n_1x] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn] + connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_gearbox_8x4_0/clk1x] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_q_data_from_axi/aclk] + connect_bd_net -net scale_2x_0_cDataOut [get_bd_pins adc_data_to_axi/s_axis_tdata] [get_bd_pins scale_2x_0/cDataOut] + connect_bd_net -net scale_2x_0_cDataValidOut [get_bd_pins adc_data_to_axi/s_axis_tvalid] [get_bd_pins scale_2x_0/cDataValidOut] + connect_bd_net -net swap_iq_2x_0_1 [get_bd_ports swap_iq_2x] [get_bd_pins adc_gearbox_8x4_0/swap_iq_2x] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/adc_400m_bd/hdl_sources.tcl b/fpga/usrp3/top/x400/ip/adc_400m_bd/hdl_sources.tcl new file mode 100644 index 000000000..c19ebf78e --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_400m_bd/hdl_sources.tcl @@ -0,0 +1,10 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +# Vivado's block diagram default library for files not belonging to any special +# library is called xil_defaultlib +read_verilog -library xil_defaultlib $script_dir/../../rf/400m/adc_gearbox_8x4.v +read_vhdl -library xil_defaultlib $script_dir/../../rf/common/PkgRf.vhd +read_vhdl -library xil_defaultlib $script_dir/../../rf/400m/adc_gearbox_2x4.vhd +read_vhdl -library xil_defaultlib $script_dir/../../rf/400m/ddc_400m_saturate.vhd +read_vhdl -library xil_defaultlib $script_dir/../../rf/common/scale_2x.vhd diff --git a/fpga/usrp3/top/x400/ip/adc_400m_bd/synthstub/adc_400m_bd.vhd b/fpga/usrp3/top/x400/ip/adc_400m_bd/synthstub/adc_400m_bd.vhd new file mode 100644 index 000000000..68a8770b4 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/adc_400m_bd/synthstub/adc_400m_bd.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------------------ +-- +-- File: adc_400m_bd.vhd +-- Author: niBlockDesign::niBdExportStub +-- Original Project: HwBuildTools +-- Date: 21 October 2020 +-- +------------------------------------------------------------------------------------------ +-- (c) Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------------------ +-- +-- Purpose: This is an automatically generated stub file to match the entity +-- declaration for 'adc_400m_bd'. This file was created using niBdExportStub +-- Do not modify this file directly! +-- +------------------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library unisim; +use unisim.vcomponents.all; + +entity adc_400m_bd is +port ( + adc_data_out_resetn_dclk : in STD_LOGIC; + data_clk : in STD_LOGIC; + enable_data_to_fir_rclk : in STD_LOGIC; + fir_resetn_rclk2x : in STD_LOGIC; + rfdc_adc_axi_resetn_rclk : in STD_LOGIC; + rfdc_clk : in STD_LOGIC; + rfdc_clk_2x : in STD_LOGIC; + swap_iq_2x : in STD_LOGIC; + adc_q_data_in_tvalid : in STD_LOGIC; + adc_q_data_in_tready : out STD_LOGIC; + adc_q_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_i_data_in_tvalid : in STD_LOGIC; + adc_i_data_in_tready : out STD_LOGIC; + adc_i_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_data_out_tvalid : out STD_LOGIC; + adc_data_out_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ) + ); + end entity adc_400m_bd; + +architecture stub of adc_400m_bd is +begin +end architecture stub; diff --git a/fpga/usrp3/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..81ddcdc00 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,21 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo_sim_netlist.v \ +) + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..26d706087 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi64_4k_2clk_fifo</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">69</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">512x72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">509</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Independent_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi64_4k_2clk_fifo</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">509</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">13</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">AXI_STREAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/Makefile.inc new file mode 100644 index 000000000..c1da814e2 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/Makefile.inc @@ -0,0 +1,31 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_ETH_DMA_BD_HDL_SRCS = $(addprefix $(IP_DIR)/axi_eth_dma_bd/, \ +axi_eth_dma.sv \ +) + +IP_AXI_ETH_DMA_BD_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_eth_dma_bd/, \ +axi_eth_dma_bd.tcl \ +) + +IP_AXI_ETH_DMA_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \ +axi_eth_dma_bd.tcl \ +) + +IP_AXI_ETH_DMA_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \ +axi_eth_dma_bd/axi_eth_dma_bd.bd \ +) + +BD_AXI_ETH_DMA_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \ +axi_eth_dma_bd.bd.out \ +axi_eth_dma_bd/synth/axi_eth_dma_bd.v \ +) + +$(IP_AXI_ETH_DMA_BD_SRCS) $(BD_AXI_ETH_DMA_BD_OUTS) $(IP_AXI_ETH_DMA_BDTCL_SRCS): $(IP_AXI_ETH_DMA_BD_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_eth_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv new file mode 100644 index 000000000..87e8825c5 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv @@ -0,0 +1,73 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: axi_eth_dma +// +// Description: Wrapper for the Xilinx AXI DMA +// + +module axi_eth_dma ( + // All interfaces on s_axi_eth_dma.clk domain + AxiStreamIf.slave e2c, // from enet mac + AxiStreamIf.master c2e, // to enet mac + AxiLiteIf.slave s_axi_eth_dma, // Register interface + AxiIf.master axi_hp, // DMA interface to host memory + output logic eth_rx_irq, + output logic eth_tx_irq + +); + + `include "../../../../lib/axi4lite_sv/axi_lite.vh" + `include "../../../../lib/axi4s_sv/axi4s.vh" + `include "../../../../lib/axi4_sv/axi.vh" + + // _v versions have no procedural assignment so they can drive a port. + AxiLiteIf_v #(32,10) + s_axi_eth_dma_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst)); + AxiIf_v #(128,49) + axi_hp_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst)); + + AxiStreamIf #(.DATA_WIDTH(c2e.DATA_WIDTH), .USER_WIDTH(c2e.USER_WIDTH), .TUSER(0)) + c2e_v (c2e.clk, c2e.rst); + AxiStreamIf #(.DATA_WIDTH(e2c.DATA_WIDTH), .USER_WIDTH(e2c.USER_WIDTH), .TUSER(0)) + e2c_v (e2c.clk, e2c.rst); + + always_comb begin + // O = I; (O , I ) + `AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma) + // Overriding assignments to mask off upper address bits + s_axi_eth_dma_v.araddr = 0; + s_axi_eth_dma_v.araddr[9:0] = s_axi_eth_dma.araddr[9:0]; + s_axi_eth_dma_v.awaddr = 0; + s_axi_eth_dma_v.awaddr[9:0] = s_axi_eth_dma.awaddr[9:0]; + end + always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end + always_comb begin `AXI4S_ASSIGN(c2e, c2e_v) end + always_comb begin `AXI4_ASSIGN(axi_hp, axi_hp_v) end + + axi_eth_dma_bd axi_eth_dma_bd_i ( + .clk40 (s_axi_eth_dma.clk), + .clk40_rstn (!s_axi_eth_dma.rst), + + .c2e_tdata (c2e_v.tdata), + .c2e_tkeep (c2e_v.tkeep), + .c2e_tlast (c2e_v.tlast), + .c2e_tready (c2e_v.tready), + .c2e_tvalid (c2e_v.tvalid), + + .e2c_tdata (e2c_v.tdata), + .e2c_tkeep (e2c_v.tkeep), + .e2c_tlast (e2c_v.tlast), + .e2c_tready (e2c_v.tready), + .e2c_tvalid (e2c_v.tvalid), + + `AXI4LITE_PORT_ASSIGN_NRS(axi_eth_dma, s_axi_eth_dma_v) + `AXI4_PORT_ASSIGN_NR(axi_hp, axi_hp_v) + + .eth_tx_irq (eth_tx_irq), + .eth_rx_irq (eth_rx_irq) + ); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl new file mode 100644 index 000000000..da97912fc --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl @@ -0,0 +1,325 @@ + +################################################################ +# This is a generated script based on design: axi_eth_dma_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_eth_dma_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_eth_dma_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:smartconnect:1.0\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set axi_eth_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_eth_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $axi_eth_dma + + set axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_hp ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + ] $axi_hp + + set c2e [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 c2e ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + ] $c2e + + set e2c [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 e2c ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $e2c + + + # Create ports + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {e2c:axi_eth_dma:axi_hp:c2e} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + set eth_rx_irq [ create_bd_port -dir O -type intr eth_rx_irq ] + set eth_tx_irq [ create_bd_port -dir O -type intr eth_tx_irq ] + + # Create instance: axi_eth_dma, and set properties + set axi_eth_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_eth_dma ] + set_property -dict [ list \ + CONFIG.c_addr_width {36} \ + CONFIG.c_enable_multi_channel {0} \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_m_axi_mm2s_data_width {64} \ + CONFIG.c_m_axi_s2mm_data_width {64} \ + CONFIG.c_m_axis_mm2s_tdata_width {64} \ + CONFIG.c_micro_dma {0} \ + CONFIG.c_mm2s_burst_size {8} \ + CONFIG.c_s2mm_burst_size {16} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + ] $axi_eth_dma + + # Create instance: smartconnect_eth_dma, and set properties + set smartconnect_eth_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_eth_dma ] + set_property -dict [ list \ + CONFIG.NUM_SI {3} \ + ] $smartconnect_eth_dma + + # Create interface connections + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_ports c2e] [get_bd_intf_pins axi_eth_dma/M_AXIS_MM2S] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_ports e2c] [get_bd_intf_pins axi_eth_dma/S_AXIS_S2MM] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_MM2S [get_bd_intf_pins axi_eth_dma/M_AXI_MM2S] [get_bd_intf_pins smartconnect_eth_dma/S01_AXI] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_S2MM [get_bd_intf_pins axi_eth_dma/M_AXI_S2MM] [get_bd_intf_pins smartconnect_eth_dma/S02_AXI] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_SG [get_bd_intf_pins axi_eth_dma/M_AXI_SG] [get_bd_intf_pins smartconnect_eth_dma/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_eth_dma_ctrl [get_bd_intf_ports axi_eth_dma] [get_bd_intf_pins axi_eth_dma/S_AXI_LITE] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports axi_hp] [get_bd_intf_pins smartconnect_eth_dma/M00_AXI] + + # Create port connections + connect_bd_net -net axi_eth_dma_mm2s_introut [get_bd_ports eth_tx_irq] [get_bd_pins axi_eth_dma/mm2s_introut] + connect_bd_net -net axi_eth_dma_s2mm_introut [get_bd_ports eth_rx_irq] [get_bd_pins axi_eth_dma/s2mm_introut] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_eth_dma/m_axi_mm2s_aclk] [get_bd_pins axi_eth_dma/m_axi_s2mm_aclk] [get_bd_pins axi_eth_dma/m_axi_sg_aclk] [get_bd_pins axi_eth_dma/s_axi_lite_aclk] [get_bd_pins smartconnect_eth_dma/aclk] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_eth_dma/axi_resetn] [get_bd_pins smartconnect_eth_dma/aresetn] + + # Create address segments + create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg + create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg + create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg + create_bd_addr_seg -range 0x010000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] SEG_axi_eth_dma_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/synthstub/axi_eth_dma_bd.vhd b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/synthstub/axi_eth_dma_bd.vhd new file mode 100644 index 000000000..55ef1c05c --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_eth_dma_bd/synthstub/axi_eth_dma_bd.vhd @@ -0,0 +1,90 @@ +-- +-- Copyright 2021 Ettus Research, a National Instruments Brand +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- Module: axi_eth_dma_bd +-- +-- Description: +-- +-- This is an automatically generated stub file to match the entity +-- declaration for 'axi_eth_dma_bd'. This file was created using +-- niBdExportStub Do not modify this file directly! +-- + +library ieee; +use ieee.std_logic_1164.all; +library unisim; +use unisim.vcomponents.all; + +entity axi_eth_dma_bd is +port ( + clk40 : in STD_LOGIC; + clk40_rstn : in STD_LOGIC; + eth_rx_irq : out STD_LOGIC; + eth_tx_irq : out STD_LOGIC; + c2e_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + c2e_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); + c2e_tlast : out STD_LOGIC; + c2e_tready : in STD_LOGIC; + c2e_tvalid : out STD_LOGIC; + e2c_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + e2c_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); + e2c_tlast : in STD_LOGIC; + e2c_tready : out STD_LOGIC; + e2c_tvalid : in STD_LOGIC; + axi_eth_dma_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_eth_dma_arready : out STD_LOGIC; + axi_eth_dma_arvalid : in STD_LOGIC; + axi_eth_dma_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_eth_dma_awready : out STD_LOGIC; + axi_eth_dma_awvalid : in STD_LOGIC; + axi_eth_dma_bready : in STD_LOGIC; + axi_eth_dma_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + axi_eth_dma_bvalid : out STD_LOGIC; + axi_eth_dma_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + axi_eth_dma_rready : in STD_LOGIC; + axi_eth_dma_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + axi_eth_dma_rvalid : out STD_LOGIC; + axi_eth_dma_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + axi_eth_dma_wready : out STD_LOGIC; + axi_eth_dma_wvalid : in STD_LOGIC; + axi_hp_awaddr : out STD_LOGIC_VECTOR ( 48 downto 0 ); + axi_hp_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + axi_hp_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + axi_hp_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + axi_hp_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + axi_hp_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_hp_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + axi_hp_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_hp_awvalid : out STD_LOGIC; + axi_hp_awready : in STD_LOGIC; + axi_hp_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + axi_hp_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 ); + axi_hp_wlast : out STD_LOGIC; + axi_hp_wvalid : out STD_LOGIC; + axi_hp_wready : in STD_LOGIC; + axi_hp_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + axi_hp_bvalid : in STD_LOGIC; + axi_hp_bready : out STD_LOGIC; + axi_hp_araddr : out STD_LOGIC_VECTOR ( 48 downto 0 ); + axi_hp_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + axi_hp_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + axi_hp_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + axi_hp_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + axi_hp_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_hp_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + axi_hp_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_hp_arvalid : out STD_LOGIC; + axi_hp_arready : in STD_LOGIC; + axi_hp_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + axi_hp_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + axi_hp_rlast : in STD_LOGIC; + axi_hp_rvalid : in STD_LOGIC; + axi_hp_rready : out STD_LOGIC + ); + end entity axi_eth_dma_bd; + +architecture stub of axi_eth_dma_bd is +begin +end architecture stub; diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_app_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/axi_interconnect_app_bd/Makefile.inc new file mode 100644 index 000000000..788b06761 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_app_bd/Makefile.inc @@ -0,0 +1,28 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCONNECT_APP_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_app_bd/, \ +axi_interconnect_app_bd.tcl \ +) + +IP_AXI_INTERCONNECT_APP_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_app_bd/, \ +axi_interconnect_app_bd.tcl \ +) + +IP_AXI_INTERCONNECT_APP_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_app_bd/, \ +axi_interconnect_app_bd/axi_interconnect_app_bd.bd \ +) + +BD_AXI_INTERCONNECT_APP_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_app_bd/, \ +axi_interconnect_app_bd.bd.out \ +axi_interconnect_app_bd/axi_interconnect_app_bd_ooc.xdc \ +axi_interconnect_app_bd/synth/axi_interconnect_app_bd.v \ +) + +$(IP_AXI_INTERCONNECT_APP_BD_SRCS) $(BD_AXI_INTERCONNECT_APP_BD_OUTS) $(IP_AXI_INTERCONNECT_APP_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_APP_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_interconnect_app_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl b/fpga/usrp3/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl new file mode 100644 index 000000000..6647aa39a --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl @@ -0,0 +1,303 @@ + +################################################################ +# This is a generated script based on design: axi_interconnect_app_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_interconnect_app_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_interconnect_app_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set m_axi_qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_qsfp0 + + set m_axi_qsfp1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_qsfp1 + + set s_axi_app [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_app ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {4} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {4} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_app + + + # Create ports + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_qsfp0:m_axi_qsfp1:s_axi_app} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {2} \ + ] $axi_interconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_app] [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_qsfp0] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_qsfp1] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + + # Create port connections + connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] + + # Create address segments + create_bd_addr_seg -range 0x00040000 -offset 0x001200000000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp0/Reg] SEG_m_axi_qsfp0_Reg + create_bd_addr_seg -range 0x00040000 -offset 0x001200040000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp1/Reg] SEG_m_axi_qsfp1_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc new file mode 100644 index 000000000..31b996bb9 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc @@ -0,0 +1,41 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCONNECT_DMA_HDL_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_dma_bd/, \ +axi_interconnect_dma.sv \ +) + +IP_AXI_INTERCONNECT_DMA_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \ +sim/axi_interconnect_dma_bd.v\ +ip/axi_interconnect_dma_bd_xbar_0/sim/axi_interconnect_dma_bd_xbar_0.v\ +ipshared/*/simulation/fifo_generator_vlog_beh.v\ +ipshared/*/hdl/*.v\ +)) + +IP_AXI_INTERCONNECT_DMA_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_dma_bd/, \ +axi_interconnect_dma_bd.tcl \ +) + +IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \ +axi_interconnect_dma_bd.tcl \ +) + +IP_AXI_INTERCONNECT_DMA_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \ +axi_interconnect_dma_bd/axi_interconnect_dma_bd.bd \ +) + +BD_AXI_INTERCONNECT_DMA_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \ +axi_interconnect_dma_bd.bd.out \ +axi_interconnect_dma_bd/axi_interconnect_dma_bd_ooc.xdc \ +axi_interconnect_dma_bd/synth/axi_interconnect_dma_bd.v \ +) + + + +$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) $(BD_AXI_INTERCONNECT_DMA_BD_OUTS) $(IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_DMA_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_interconnect_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv new file mode 100644 index 000000000..9fd2f6589 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv @@ -0,0 +1,40 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: axi_interconnect_dma +// +// Description: Wrapper for the Xilinx AXI interconnect block +// + +module axi_interconnect_dma ( + AxiIf.slave s_axi_hp_dma [3:0], // Incoming AXI from DMA engines + AxiIf.master m_axi_hp // Outgoing AXI to memory +); + + // AxiIf_v has no procedural assignments so it can be driven by a port. + `include "../../../../lib/axi4_sv/axi.vh" + AxiIf_v #(128,49) + m_axi_hp_v(.clk(m_axi_hp.clk), .rst(m_axi_hp.rst)); + AxiIf_v #(128,49) + s_axi_hp_dma_v[3:0](.clk(m_axi_hp.clk), .rst(m_axi_hp.rst)); + + // O = I; (O , I ) + always_comb begin `AXI4_ASSIGN(m_axi_hp, m_axi_hp_v) end + always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[0], s_axi_hp_dma[0]) end + always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[1], s_axi_hp_dma[1]) end + always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[2], s_axi_hp_dma[2]) end + always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[3], s_axi_hp_dma[3]) end + + axi_interconnect_dma_bd axi_interconnect_dma_bd_i ( + `AXI4_PORT_ASSIGN_NR(m_axi_hp, m_axi_hp_v) + `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma0, s_axi_hp_dma_v[0]) + `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma1, s_axi_hp_dma_v[1]) + `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma2, s_axi_hp_dma_v[2]) + `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma3, s_axi_hp_dma_v[3]) + .clk40 (m_axi_hp.clk), + .clk40_rstn (!m_axi_hp.rst) + ); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl new file mode 100644 index 000000000..43c959ac0 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl @@ -0,0 +1,405 @@ + +################################################################ +# This is a generated script based on design: axi_interconnect_dma_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_interconnect_dma_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_interconnect_dma_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set m_axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_hp ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + ] $m_axi_hp + + set s_axi_hp_dma0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {4} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {4} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp_dma0 + + set s_axi_hp_dma1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {4} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {4} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp_dma1 + + set s_axi_hp_dma2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma2 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {4} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {4} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp_dma2 + + set s_axi_hp_dma3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma3 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {4} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {4} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp_dma3 + + + # Create ports + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axi_hp_dma0:s_axi_hp_dma1:s_axi_hp_dma2:s_axi_hp_dma3:m_axi_hp} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_DATA_FIFO {1} \ + CONFIG.M00_HAS_REGSLICE {4} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {4} \ + CONFIG.S00_HAS_DATA_FIFO {1} \ + CONFIG.S00_HAS_REGSLICE {4} \ + CONFIG.S01_ARB_PRIORITY {0} \ + CONFIG.S01_HAS_DATA_FIFO {1} \ + CONFIG.S01_HAS_REGSLICE {4} \ + CONFIG.S02_ARB_PRIORITY {0} \ + CONFIG.S02_HAS_DATA_FIFO {1} \ + CONFIG.S02_HAS_REGSLICE {4} \ + CONFIG.S03_ARB_PRIORITY {0} \ + CONFIG.S03_HAS_DATA_FIFO {1} \ + CONFIG.S03_HAS_REGSLICE {4} \ + CONFIG.STRATEGY {1} \ + ] $axi_interconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_hp_dma0] [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_hp] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net s_axi_eth1_1 [get_bd_intf_ports s_axi_hp_dma1] [get_bd_intf_pins axi_interconnect_0/S01_AXI] + connect_bd_intf_net -intf_net s_axi_eth2_1 [get_bd_intf_ports s_axi_hp_dma2] [get_bd_intf_pins axi_interconnect_0/S02_AXI] + connect_bd_intf_net -intf_net s_axi_eth3_1 [get_bd_intf_ports s_axi_hp_dma3] [get_bd_intf_pins axi_interconnect_0/S03_AXI] + + # Create port connections + connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins axi_interconnect_0/S03_ACLK] + connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_interconnect_0/S03_ARESETN] + + # Create address segments + create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg + create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg + create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg + create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc new file mode 100644 index 000000000..f21a366f0 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/Makefile.inc @@ -0,0 +1,41 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCONNECT_ETH_HDL_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_eth_bd/, \ +axi_interconnect_eth.sv \ +) + +IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/axi_interconnect_eth_bd/, \ +sim/axi_interconnect_eth_bd.v\ +ip/axi_interconnect_eth_bd_xbar_0/sim/axi_interconnect_eth_bd_xbar_0.v\ +ipshared/*/simulation/fifo_generator_vlog_beh.v\ +ipshared/*/hdl/*.v\ +)) + +IP_AXI_INTERCONNECT_ETH_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_eth_bd/, \ +axi_interconnect_eth_bd.tcl \ +) + +IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \ +axi_interconnect_eth_bd.tcl \ +) + +IP_AXI_INTERCONNECT_ETH_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \ +axi_interconnect_eth_bd/axi_interconnect_eth_bd.bd \ +) + +BD_AXI_INTERCONNECT_ETH_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \ +axi_interconnect_eth_bd.bd.out \ +axi_interconnect_eth_bd/synth/axi_interconnect_eth_bd.v \ +axi_interconnect_eth_bd/axi_interconnect_eth_bd_ooc.xdc \ +) + + + +$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) $(BD_AXI_INTERCONNECT_ETH_BD_OUTS) $(IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_ETH_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_interconnect_eth_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv b/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv new file mode 100644 index 000000000..d74389c03 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv @@ -0,0 +1,98 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: axi_interconnect_eth +// +// Description: +// +// Wrapper for the Xilinx AXI Lite interconnect block +// + +module axi_interconnect_eth ( + // All interfaces on s_axi_eth.clk domain + AxiLiteIf.master m_axi_dma[3:0], // maps to CPU_DMA +0x00000-0x07FFF + AxiLiteIf.master m_axi_misc[3:0], // maps to nixge +0x08000-0x09FFF + // UIO +0x0A000-0x0BFFF + AxiLiteIf.master m_axi_mac[3:0], // maps to 100G Mac +0x0C000-0x0DFFF + + AxiLiteIf.slave s_axi_eth // incoming axi_net bus +); + + + // AxiLiteIf_v has no procedural assignments so it can be + // driven by a port. + `include "../../../../lib/axi4lite_sv/axi_lite.vh" + AxiLiteIf_v #(32,40) + m_axi_dma_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst)); + AxiLiteIf_v #(32,40) + m_axi_misc_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst)); + AxiLiteIf_v #(32,40) + m_axi_mac_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst)); + AxiLiteIf_v #(32,40) + s_axi_eth_v(.clk(s_axi_eth.clk),.rst(s_axi_eth.rst)); + + // O = I;(O ,I ) + always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[1],m_axi_dma_v[1]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[2],m_axi_dma_v[2]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[3],m_axi_dma_v[3]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[0],m_axi_misc_v[0]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[1],m_axi_misc_v[1]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[2],m_axi_misc_v[2]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[3],m_axi_misc_v[3]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[0],m_axi_mac_v[0]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[1],m_axi_mac_v[1]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[2],m_axi_mac_v[2]) end + always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[3],m_axi_mac_v[3]) end + always_comb begin `AXI4LITE_ASSIGN(s_axi_eth_v,s_axi_eth) end + + axi_interconnect_eth_bd axi_interconnect_eth_bd_i + ( + `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma0,m_axi_dma_v[0]) + .m_axi_dma0_arprot(), + .m_axi_dma0_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma1,m_axi_dma_v[1]) + .m_axi_dma1_arprot(), + .m_axi_dma1_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma2,m_axi_dma_v[2]) + .m_axi_dma2_arprot(), + .m_axi_dma2_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_dma3,m_axi_dma_v[3]) + .m_axi_dma3_arprot(), + .m_axi_dma3_awprot(), + + `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac0,m_axi_mac_v[0]) + .m_axi_mac0_arprot(), + .m_axi_mac0_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac1,m_axi_mac_v[1]) + .m_axi_mac1_arprot(), + .m_axi_mac1_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac2,m_axi_mac_v[2]) + .m_axi_mac2_arprot(), + .m_axi_mac2_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_mac3,m_axi_mac_v[3]) + .m_axi_mac3_arprot(), + .m_axi_mac3_awprot(), + + `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc0,m_axi_misc_v[0]) + .m_axi_misc0_arprot(), + .m_axi_misc0_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc1,m_axi_misc_v[1]) + .m_axi_misc1_arprot(), + .m_axi_misc1_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc2,m_axi_misc_v[2]) + .m_axi_misc2_arprot(), + .m_axi_misc2_awprot(), + `AXI4LITE_PORT_ASSIGN_NR(m_axi_misc3,m_axi_misc_v[3]) + .m_axi_misc3_arprot(), + .m_axi_misc3_awprot(), + + `AXI4LITE_PORT_ASSIGN_NR(s_axi_eth,s_axi_eth_v) + .s_axi_eth_arprot(3'b0), + .s_axi_eth_awprot(3'b0), + .clk40(s_axi_eth.clk), + .clk40_rstn(!s_axi_eth.rst)); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl b/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl new file mode 100644 index 000000000..2efa50bfd --- /dev/null +++ b/fpga/usrp3/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl @@ -0,0 +1,462 @@ + +################################################################ +# This is a generated script based on design: axi_interconnect_eth_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_interconnect_eth_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_interconnect_eth_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set m_axi_dma0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_dma0 + + set m_axi_dma1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_dma1 + + set m_axi_dma2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma2 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_dma2 + + set m_axi_dma3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma3 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_dma3 + + set m_axi_mac0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_mac0 + + set m_axi_mac1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_mac1 + + set m_axi_mac2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac2 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_mac2 + + set m_axi_mac3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac3 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_mac3 + + set m_axi_misc0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_misc0 + + set m_axi_misc1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_misc1 + + set m_axi_misc2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc2 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_misc2 + + set m_axi_misc3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc3 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_misc3 + + set s_axi_eth [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {4} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {4} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_eth + + + # Create ports + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_misc0:m_axi_mac0:s_axi_eth:m_axi_misc3:m_axi_mac3:m_axi_dma1:m_axi_misc1:m_axi_mac2:m_axi_dma2:m_axi_mac1:m_axi_misc2:m_axi_dma0:m_axi_dma3} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {12} \ + ] $axi_interconnect_0 + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_eth] [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_misc0] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_mac0] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports m_axi_dma0] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports m_axi_misc1] [get_bd_intf_pins axi_interconnect_0/M03_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports m_axi_mac1] [get_bd_intf_pins axi_interconnect_0/M04_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports m_axi_dma1] [get_bd_intf_pins axi_interconnect_0/M05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports m_axi_misc2] [get_bd_intf_pins axi_interconnect_0/M06_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports m_axi_mac2] [get_bd_intf_pins axi_interconnect_0/M07_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_ports m_axi_dma2] [get_bd_intf_pins axi_interconnect_0/M08_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_ports m_axi_misc3] [get_bd_intf_pins axi_interconnect_0/M09_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_ports m_axi_mac3] [get_bd_intf_pins axi_interconnect_0/M10_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_ports m_axi_dma3] [get_bd_intf_pins axi_interconnect_0/M11_AXI] + + # Create port connections + connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] + + # Create address segments + create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] SEG_m_axi_dma0_Reg + create_bd_addr_seg -range 0x00008000 -offset 0x00010000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] SEG_m_axi_dma1_Reg + create_bd_addr_seg -range 0x00008000 -offset 0x00020000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] SEG_m_axi_dma2_Reg + create_bd_addr_seg -range 0x00008000 -offset 0x00030000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] SEG_m_axi_dma3_Reg + create_bd_addr_seg -range 0x00002000 -offset 0x0000C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] SEG_m_axi_mac0_Reg + create_bd_addr_seg -range 0x00002000 -offset 0x0001C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] SEG_m_axi_mac1_Reg + create_bd_addr_seg -range 0x00002000 -offset 0x0002C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] SEG_m_axi_mac2_Reg + create_bd_addr_seg -range 0x00002000 -offset 0x0003C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] SEG_m_axi_mac3_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x00008000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] SEG_m_axi_misc0_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x00018000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] SEG_m_axi_misc1_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x00028000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] SEG_m_axi_misc2_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x00038000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] SEG_m_axi_misc3_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/dac_100m_bd/.gitignore b/fpga/usrp3/top/x400/ip/dac_100m_bd/.gitignore new file mode 100644 index 000000000..49f7d3710 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_100m_bd/.gitignore @@ -0,0 +1 @@ +synthstub/ diff --git a/fpga/usrp3/top/x400/ip/dac_100m_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/dac_100m_bd/Makefile.inc new file mode 100644 index 000000000..c107580be --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_100m_bd/Makefile.inc @@ -0,0 +1,36 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DAC_100M_ORIG_SRCS = $(addprefix $(IP_DIR)/dac_100m_bd/, \ +dac_100m_bd.tcl \ +) + +IP_DAC_100M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/100m/, \ +duc_saturate.vhd \ +dac_1_3_clk_converter.vhd \ +dac_2_1_clk_converter.vhd \ +) + +IP_DAC_100M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_100m_bd/, \ +dac_100m_bd.tcl \ +) + +IP_DAC_100M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_100m_bd/, \ +dac_100m_bd/dac_100m_bd.bd \ +) + +BD_DAC_100M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/dac_100m_bd/, \ +dac_100m_bd.bd.out \ +dac_100m_bd/dac_100m_bd_ooc.xdc \ +dac_100m_bd/synth/dac_100m_bd.v \ +) + +EMPTY_IP_SRCS = + +$(IP_DAC_100M_BD_SRCS) $(BD_DAC_100M_BD_OUTS) $(IP_DAC_100M_BDTCL_SRCS): $(IP_DAC_100M_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,dac_100m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_DAC_100M_HDL_SRCS),) diff --git a/fpga/usrp3/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl b/fpga/usrp3/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl new file mode 100644 index 000000000..fcc30e5c7 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl @@ -0,0 +1,389 @@ + +################################################################ +# This is a generated script based on design: dac_100m_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source dac_100m_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# dac_1_3_clk_converter, dac_2_1_clk_converter, duc_saturate + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name dac_100m_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:fir_compiler:7.2\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:axis_register_slice:1.1\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +dac_1_3_clk_converter\ +dac_2_1_clk_converter\ +duc_saturate\ +" + + set list_mods_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set dac_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {122880000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {4} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_data_in + + set dac_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 dac_data_out ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $dac_data_out + + + # Create ports + set dac_data_in_resetn_dclk [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk ] + set dac_data_in_resetn_rclk [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk ] + set dac_data_in_resetn_rclk2x [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk2x ] + set data_clk [ create_bd_port -dir I -type clk data_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {dac_data_in} \ + CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk} \ + CONFIG.FREQ_HZ {122880000} \ + ] $data_clk + set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {dac_data_out} \ + CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk} \ + CONFIG.FREQ_HZ {184320000} \ + ] $rfdc_clk + set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk2x} \ + CONFIG.FREQ_HZ {368640000} \ + ] $rfdc_clk_2x + + # Create instance: constant_high, and set properties + set constant_high [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_high ] + + # Create instance: dac_1_3_clk_converter_0, and set properties + set block_name dac_1_3_clk_converter + set block_cell_name dac_1_3_clk_converter_0 + if { [catch {set dac_1_3_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $dac_1_3_clk_converter_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: dac_2_1_clk_converter_0, and set properties + set block_name dac_2_1_clk_converter + set block_cell_name dac_2_1_clk_converter_0 + if { [catch {set dac_2_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $dac_2_1_clk_converter_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: dac_interpolator, and set properties + set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ] + set_property -dict [ list \ + CONFIG.Clock_Frequency {368.64} \ + CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Sets {1} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Coefficient_Structure {Symmetric} \ + CONFIG.Coefficient_Width {18} \ + CONFIG.ColumnConfig {14} \ + CONFIG.Data_Fractional_Bits {0} \ + CONFIG.Data_Width {16} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.Filter_Type {Interpolation} \ + CONFIG.Has_ARESETn {true} \ + CONFIG.Interpolation_Rate {3} \ + CONFIG.M_DATA_Has_TREADY {false} \ + CONFIG.Number_Channels {1} \ + CONFIG.Number_Paths {2} \ + CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \ + CONFIG.Output_Width {18} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.RateSpecification {Frequency_Specification} \ + CONFIG.Reset_Data_Vector {false} \ + CONFIG.S_DATA_Has_FIFO {false} \ + CONFIG.Sample_Frequency {122.88} \ + CONFIG.Zero_Pack_Factor {1} \ + ] $dac_interpolator + + # Create instance: data_combiner, and set properties + set data_combiner [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_combiner ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {32} \ + CONFIG.IN1_WIDTH {32} \ + ] $data_combiner + + # Create instance: duc_saturate, and set properties + set block_name duc_saturate + set block_cell_name duc_saturate + if { [catch {set duc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $duc_saturate eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: registered_dac_data, and set properties + set registered_dac_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 registered_dac_data ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {4} \ + ] $registered_dac_data + + # Create interface connections + connect_bd_intf_net -intf_net dac_1_3_clk_converter_0_m_axis [get_bd_intf_pins dac_1_3_clk_converter_0/m_axis] [get_bd_intf_pins dac_interpolator/S_AXIS_DATA] + connect_bd_intf_net -intf_net dac_2_1_clk_converter_0_m_axis [get_bd_intf_ports dac_data_out] [get_bd_intf_pins dac_2_1_clk_converter_0/m_axis] + connect_bd_intf_net -intf_net dac_data_in_1 [get_bd_intf_ports dac_data_in] [get_bd_intf_pins dac_1_3_clk_converter_0/s_axis] + + # Create port connections + connect_bd_net -net aclk_0_1 [get_bd_ports data_clk] [get_bd_pins dac_1_3_clk_converter_0/s_axis_aclk] + connect_bd_net -net aresetn_0_1 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins dac_1_3_clk_converter_0/s_axis_aresetn] + connect_bd_net -net axis_register_slice_0_m_axis_tdata [get_bd_pins data_combiner/In0] [get_bd_pins registered_dac_data/m_axis_tdata] + connect_bd_net -net dac_data_in_resetn_rclk2x [get_bd_ports dac_data_in_resetn_rclk2x] [get_bd_pins dac_1_3_clk_converter_0/m_axis_aresetn] [get_bd_pins dac_2_1_clk_converter_0/s_axis_aresetn] [get_bd_pins dac_interpolator/aresetn] [get_bd_pins registered_dac_data/aresetn] + connect_bd_net -net dac_data_in_resetn_rclk_1 [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins dac_2_1_clk_converter_0/m_axis_aresetn] + connect_bd_net -net dac_interpolator_m_axis_data_tdata [get_bd_pins dac_interpolator/m_axis_data_tdata] [get_bd_pins duc_saturate/cDataIn] + connect_bd_net -net dac_interpolator_m_axis_data_tvalid [get_bd_pins dac_interpolator/m_axis_data_tvalid] [get_bd_pins duc_saturate/cDataValidIn] + connect_bd_net -net data_combiner_dout [get_bd_pins dac_2_1_clk_converter_0/s_axis_tdata] [get_bd_pins data_combiner/dout] + connect_bd_net -net ddc_saturate_0_cDataOut [get_bd_pins data_combiner/In1] [get_bd_pins duc_saturate/cDataOut] [get_bd_pins registered_dac_data/s_axis_tdata] + connect_bd_net -net duc_saturate_0_cDataValidOut [get_bd_pins duc_saturate/cDataValidOut] [get_bd_pins registered_dac_data/s_axis_tvalid] + connect_bd_net -net m_axis_aclk_0_1 [get_bd_ports rfdc_clk_2x] [get_bd_pins dac_1_3_clk_converter_0/m_axis_aclk] [get_bd_pins dac_2_1_clk_converter_0/s_axis_aclk] [get_bd_pins dac_interpolator/aclk] [get_bd_pins duc_saturate/Clk] [get_bd_pins registered_dac_data/aclk] + connect_bd_net -net registered_dac_data_m_axis_tvalid [get_bd_pins dac_2_1_clk_converter_0/s_axis_tvalid] [get_bd_pins registered_dac_data/m_axis_tvalid] + connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins dac_2_1_clk_converter_0/m_axis_aclk] + connect_bd_net -net xlconstant_0_dout [get_bd_pins constant_high/dout] [get_bd_pins registered_dac_data/m_axis_tready] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/dac_100m_bd/hdl_sources.tcl b/fpga/usrp3/top/x400/ip/dac_100m_bd/hdl_sources.tcl new file mode 100644 index 000000000..c33ee9cd5 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_100m_bd/hdl_sources.tcl @@ -0,0 +1,6 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +read_vhdl -library work $script_dir/../../rf/100m/duc_saturate.vhd +read_vhdl -library work $script_dir/../../rf/100m/dac_1_3_clk_converter.vhd +read_vhdl -library work $script_dir/../../rf/100m/dac_2_1_clk_converter.vhd diff --git a/fpga/usrp3/top/x400/ip/dac_400m_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/dac_400m_bd/Makefile.inc new file mode 100644 index 000000000..c55c67928 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_400m_bd/Makefile.inc @@ -0,0 +1,38 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DAC_400M_ORIG_SRCS = $(addprefix $(IP_DIR)/dac_400m_bd/, \ +dac_400m_bd.tcl \ +) + +IP_DAC_400M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/400m/, \ +duc_400m_saturate.vhd \ +dac_gearbox_6x8.vhd \ +dac_gearbox_6x12.vhd \ +dac_gearbox_12x8.vhd \ +dac_gearbox_4x2.v \ +) + +IP_DAC_400M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_400m_bd/, \ +dac_400m_bd.tcl \ +) + +IP_DAC_400M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_400m_bd/, \ +dac_400m_bd/dac_400m_bd.bd \ +) + +BD_DAC_400M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/dac_400m_bd/, \ +dac_400m_bd.bd.out \ +dac_400m_bd/dac_400m_bd_ooc.xdc \ +dac_400m_bd/synth/dac_400m_bd.v \ +) + +EMPTY_IP_SRCS = + +$(IP_DAC_400M_BD_SRCS) $(BD_DAC_400M_BD_OUTS) $(IP_DAC_400M_BDTCL_SRCS): $(IP_DAC_400M_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,dac_400m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_DAC_400M_HDL_SRCS),) diff --git a/fpga/usrp3/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl b/fpga/usrp3/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl new file mode 100644 index 000000000..96392adcf --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl @@ -0,0 +1,348 @@ + +################################################################ +# This is a generated script based on design: dac_400m_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source dac_400m_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# dac_gearbox_4x2, dac_gearbox_6x8, duc_400m_saturate + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name dac_400m_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:fir_compiler:7.2\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +dac_gearbox_4x2\ +dac_gearbox_6x8\ +duc_400m_saturate\ +" + + set list_mods_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set dac_data_in_resetn_dclk [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk ] + set dac_data_in_resetn_dclk2x [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk2x ] + set dac_data_in_resetn_rclk [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk ] + set dac_data_in_tdata [ create_bd_port -dir I -from 127 -to 0 -type data dac_data_in_tdata ] + set dac_data_in_tready [ create_bd_port -dir O -type data dac_data_in_tready ] + set dac_data_in_tvalid [ create_bd_port -dir I -type data dac_data_in_tvalid ] + set dac_data_out_tdata [ create_bd_port -dir O -from 255 -to 0 -type data dac_data_out_tdata ] + set dac_data_out_tready [ create_bd_port -dir I -type data dac_data_out_tready ] + set dac_data_out_tvalid [ create_bd_port -dir O -type data dac_data_out_tvalid ] + set data_clk [ create_bd_port -dir I -type clk data_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {122880000} \ + ] $data_clk + set data_clk_2x [ create_bd_port -dir I -type clk data_clk_2x ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk2x} \ + CONFIG.FREQ_HZ {245760000} \ + ] $data_clk_2x + set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $rfdc_clk + + # Create instance: dac_gearbox_4x2_0, and set properties + set block_name dac_gearbox_4x2 + set block_cell_name dac_gearbox_4x2_0 + if { [catch {set dac_gearbox_4x2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $dac_gearbox_4x2_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: dac_gearbox_6x8_0, and set properties + set block_name dac_gearbox_6x8 + set block_cell_name dac_gearbox_6x8_0 + if { [catch {set dac_gearbox_6x8_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $dac_gearbox_6x8_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: dac_interpolator, and set properties + set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ] + set_property -dict [ list \ + CONFIG.Clock_Frequency {245.76} \ + CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \ + CONFIG.Coefficient_Fractional_Bits {0} \ + CONFIG.Coefficient_Sets {1} \ + CONFIG.Coefficient_Sign {Signed} \ + CONFIG.Coefficient_Structure {Inferred} \ + CONFIG.Coefficient_Width {18} \ + CONFIG.ColumnConfig {27} \ + CONFIG.Decimation_Rate {1} \ + CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ + CONFIG.Filter_Type {Interpolation} \ + CONFIG.Has_ARESETn {true} \ + CONFIG.Interpolation_Rate {3} \ + CONFIG.Number_Channels {1} \ + CONFIG.Number_Paths {2} \ + CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \ + CONFIG.Output_Width {18} \ + CONFIG.Quantization {Integer_Coefficients} \ + CONFIG.RateSpecification {Frequency_Specification} \ + CONFIG.Reset_Data_Vector {false} \ + CONFIG.S_DATA_Has_FIFO {false} \ + CONFIG.Sample_Frequency {491.52} \ + CONFIG.Zero_Pack_Factor {1} \ + ] $dac_interpolator + + # Create instance: duc_400m_saturate_0, and set properties + set block_name duc_400m_saturate + set block_cell_name duc_400m_saturate_0 + if { [catch {set duc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $duc_400m_saturate_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create port connections + connect_bd_net -net dac_data_in_1 [get_bd_ports dac_data_in_tdata] [get_bd_pins dac_gearbox_4x2_0/data_in_1x] + connect_bd_net -net dac_data_in_resetn_dclk_1 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins dac_gearbox_4x2_0/reset_n_1x] [get_bd_pins dac_gearbox_6x8_0/ac1Reset_n] + connect_bd_net -net dac_data_in_resetn_rclk_1 [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins dac_gearbox_6x8_0/arReset_n] + connect_bd_net -net dac_data_out_tready_1 [get_bd_ports dac_data_out_tready] [get_bd_pins dac_gearbox_6x8_0/rReadyForOutput] + connect_bd_net -net dac_data_valid_in_1 [get_bd_ports dac_data_in_tvalid] [get_bd_pins dac_gearbox_4x2_0/valid_in_1x] + connect_bd_net -net dac_gearbox_4x2_0_data_out_2x [get_bd_pins dac_gearbox_4x2_0/data_out_2x] [get_bd_pins dac_interpolator/s_axis_data_tdata] + connect_bd_net -net dac_gearbox_4x2_0_ready_out_1x [get_bd_ports dac_data_in_tready] [get_bd_pins dac_gearbox_4x2_0/ready_out_1x] + connect_bd_net -net dac_gearbox_4x2_0_valid_out_2x [get_bd_pins dac_gearbox_4x2_0/valid_out_2x] [get_bd_pins dac_interpolator/s_axis_data_tvalid] + connect_bd_net -net dac_gearbox_6x8_0_rDataOut [get_bd_ports dac_data_out_tdata] [get_bd_pins dac_gearbox_6x8_0/rDataOut] + connect_bd_net -net dac_gearbox_6x8_0_rDataValidOut [get_bd_ports dac_data_out_tvalid] [get_bd_pins dac_gearbox_6x8_0/rDataValidOut] + connect_bd_net -net dac_interpolator_m_axis_data_tdata [get_bd_pins dac_interpolator/m_axis_data_tdata] [get_bd_pins duc_400m_saturate_0/cDataIn] + connect_bd_net -net dac_interpolator_m_axis_data_tvalid [get_bd_pins dac_interpolator/m_axis_data_tvalid] [get_bd_pins duc_400m_saturate_0/cDataValidIn] + connect_bd_net -net data_clk_1 [get_bd_ports data_clk] [get_bd_pins dac_gearbox_4x2_0/clk1x] [get_bd_pins dac_gearbox_6x8_0/Clk1x] + connect_bd_net -net data_clk_2x_1 [get_bd_ports data_clk_2x] [get_bd_pins dac_gearbox_4x2_0/clk2x] [get_bd_pins dac_gearbox_6x8_0/Clk2x] [get_bd_pins dac_interpolator/aclk] [get_bd_pins duc_400m_saturate_0/Clk] + connect_bd_net -net data_resetn_dclk2x_1 [get_bd_ports dac_data_in_resetn_dclk2x] [get_bd_pins dac_gearbox_6x8_0/ac2Reset_n] [get_bd_pins dac_interpolator/aresetn] + connect_bd_net -net duc_400m_saturate_0_cDataOut [get_bd_pins dac_gearbox_6x8_0/c2DataIn] [get_bd_pins duc_400m_saturate_0/cDataOut] + connect_bd_net -net duc_400m_saturate_0_cDataValidOut [get_bd_pins dac_gearbox_6x8_0/c2DataValidIn] [get_bd_pins duc_400m_saturate_0/cDataValidOut] + connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins dac_gearbox_6x8_0/RfClk] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/dac_400m_bd/hdl_sources.tcl b/fpga/usrp3/top/x400/ip/dac_400m_bd/hdl_sources.tcl new file mode 100644 index 000000000..46c2b485e --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_400m_bd/hdl_sources.tcl @@ -0,0 +1,9 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +read_verilog -library work $script_dir/../../rf/400m/dac_gearbox_4x2.v +read_vhdl -library work $script_dir/../../rf/common/PkgRf.vhd +read_vhdl -library work $script_dir/../../rf/400m/dac_gearbox_6x8.vhd +read_vhdl -library work $script_dir/../../rf/400m/dac_gearbox_6x12.vhd +read_vhdl -library work $script_dir/../../rf/400m/dac_gearbox_12x8.vhd +read_vhdl -library work $script_dir/../../rf/400m/duc_400m_saturate.vhd diff --git a/fpga/usrp3/top/x400/ip/dac_400m_bd/synthstub/dac_400m_bd.vhd b/fpga/usrp3/top/x400/ip/dac_400m_bd/synthstub/dac_400m_bd.vhd new file mode 100644 index 000000000..d959d5752 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/dac_400m_bd/synthstub/dac_400m_bd.vhd @@ -0,0 +1,44 @@ +------------------------------------------------------------------------------------------ +-- +-- File: dac_400m_bd.vhd +-- Author: niBlockDesign::niBdExportStub +-- Original Project: HwBuildTools +-- Date: 22 April 2020 +-- +------------------------------------------------------------------------------------------ +-- (c) Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------------------ +-- +-- Purpose: This is an automatically generated stub file to match the entity +-- declaration for 'dac_400m_bd'. This file was created using niBdExportStub +-- Do not modify this file directly! +-- +------------------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library unisim; +use unisim.vcomponents.all; + +entity dac_400m_bd is +port ( + dac_data_in_resetn_dclk : in STD_LOGIC; + dac_data_in_resetn_dclk2x : in STD_LOGIC; + dac_data_in_resetn_rclk : in STD_LOGIC; + dac_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + dac_data_in_tready : out STD_LOGIC; + dac_data_in_tvalid : in STD_LOGIC; + dac_data_out_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_data_out_tready : in STD_LOGIC; + dac_data_out_tvalid : out STD_LOGIC; + data_clk : in STD_LOGIC; + data_clk_2x : in STD_LOGIC; + rfdc_clk : in STD_LOGIC + ); + end entity dac_400m_bd; + +architecture stub of dac_400m_bd is +begin +end architecture stub; diff --git a/fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc b/fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc new file mode 100644 index 000000000..4b3ebada2 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/ddr4_64bits/Makefile.inc @@ -0,0 +1,18 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR4_64BITS_SRCS = \ +$(IP_BUILD_DIR)/ddr4_64bits/ddr4_64bits.xci + +IP_DDR4_64BITS_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits/, \ +ddr4_64bits.xci.out \ +) + + +$(IP_DDR4_64BITS_SRCS) $(IP_DDR4_64BITS_OUTS) : $(IP_DIR)/ddr4_64bits/ddr4_64bits.xci + $(call BUILD_VIVADO_IP,ddr4_64bits,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci b/fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci new file mode 100644 index 000000000..d1b5484e5 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/ddr4_64bits/ddr4_64bits.xci @@ -0,0 +1,450 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>ddr4_64bits</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4" spirit:version="2.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_MASK_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_1">X0Y11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_2">X0Y10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_1">X0Y70</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.CENTER_BANK_CLOCK_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ADDR_WIDTH">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BANK_GROUP_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BANK_WIDTH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">9996</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO_2X</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">8Gb</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_ADDR">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">MT40A512M16HA-075E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">Components</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">8Gb</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">8192</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">4294967296</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">750</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_750_Timing</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">075E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">300000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCK">833</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW">37</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRAS">39</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRCD">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tREFI">9363</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC">421</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">145</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRP">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD"/> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_L">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_S">7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRTP">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWR">19</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR"/> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_L">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_S">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tXPR">109</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">9996</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT1_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Simulation_Mode">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AL_SEL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ADDR_WIDTH">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CKE_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CS_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ACT_SKEW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_11">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_12">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AutoPrecharge">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme">RD_PRI_REG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiIDWidth">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiNarrowBurst">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstLength">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstType">Sequential</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Capacity">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasLatency">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CustomParts">no_file_loaded</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">9996</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MCS_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MT40A512M16HA-075E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">Components</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_2">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC_DLR">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TXPR">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">833</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TREFI">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TXPR">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.LR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.MIGRATION">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ODT_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.StackHeight">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ddr4_64bits</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCI_Cascade">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Power_Reduction">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Complete_Memory_Controller</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reference_Clock">Differential</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SET_DW_TO_40">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_3DS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP1">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplusRFSOC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu28dr</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvg1517</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">73068</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1_AR73068</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/eth_100g_bd/Makefile.inc new file mode 100644 index 000000000..88c9c1184 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/Makefile.inc @@ -0,0 +1,53 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_100G_HDL_SRCS = $(addprefix $(IP_DIR)/eth_100g_bd/, \ +PkgEth100gLbus.sv \ +eth_100g.sv \ +eth_100g_axis2lbus.sv \ +eth_100g_lbus2axis.sv \ +) + +IP_100G_HDL_SIM_SRCS = $(addprefix $(IP_DIR)/eth_100g_bd/, \ +model_100gbe.sv \ +) \ +$(wildcard $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/eth_100g_bd/, \ +sim/eth_100g_bd.v\ +ip/*/ip_0/sim/*.v\ +ip/*/sim/*.h\ +ip/*/sim/*.v\ +ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v2_6_1/*.v\ +ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/*.v\ +ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/header_files/*.h\ +ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0.v\ +ipshared/*/hdl/*.v\ +ipshared/*/hdl/*.sv\ +)) + +IP_100G_ORIG_SRCS = $(addprefix $(IP_DIR)/eth_100g_bd/, \ +eth_100g_bd.tcl \ +) + +IP_100G_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/, \ +eth_100g_bd.tcl \ +) + +IP_100G_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/, \ +eth_100g_bd/eth_100g_bd.bd \ +) + +BD_100G_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/, \ +eth_100g_bd.bd.out \ +eth_100g_bd/eth_100g_bd_ooc.xdc \ +eth_100g_bd/synth/eth_100g_bd.v \ +) + +EMPTY_IP_SRCS = + +$(IP_100G_BD_SRCS) $(BD_100G_BD_OUTS) $(IP_100G_BDTCL_SRCS): $(IP_100G_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,eth_100g_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS)) diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/PkgEth100gLbus.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/PkgEth100gLbus.sv new file mode 100644 index 000000000..588313e55 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/PkgEth100gLbus.sv @@ -0,0 +1,36 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: PkgEth100gLbus +// +// Description: +// +// Package to define an Lbus record +// + +//----------------------------------------------------------------------------- +// Lbus interface +// +// This is the segmented local bus interface on the Xilinx CMAC IP +// see Xilinx CMAC documentation for detail +// https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf +//----------------------------------------------------------------------------- + +package PkgEth100gLbus; + + localparam DATA_WIDTH = 512; + localparam NUM_SEG = 4; + localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG; + + typedef struct packed { + logic [SEG_DATA_WIDTH-1:0] data; + logic [$clog2(SEG_DATA_WIDTH/8)-1:0] mty; + logic sop; + logic eop; + logic err; + logic ena; + } lbus_t; + +endpackage : PkgEth100gLbus diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv new file mode 100644 index 000000000..456db06d9 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g.sv @@ -0,0 +1,1220 @@ +// +// Copyright 2021 Ettus Research, A National Instruments brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: eth_100g +// +// Description: Wrapper for the Xilinx 100G mac + + +module eth_100g #( + logic PAUSE_EN = 1, + logic [15:0] PAUSE_QUANTA = 16'hFFFF, + logic [15:0] PAUSE_REFRESH = 16'hFFFF + )( + + // Resets + input logic areset, + // Clock for misc stuff + input logic clk100, + // Low jitter refclk + input logic refclk_p, + input logic refclk_n, + // RX Clk for output + output logic rx_rec_clk_out, + // MGT high-speed IO + output logic[3:0] tx_p, + output logic[3:0] tx_n, + input logic[3:0] rx_p, + input logic[3:0] rx_n, + + // Data port + output logic mgt_clk, + output logic mgt_rst, + input logic mgt_pause_req, + // Interface clocks for mgt_tx and mgt_rx are NOT used (logic uses mgt_clk) + AxiStreamIf.slave mgt_tx, + AxiStreamIf.master mgt_rx, + // Axi port + AxiLiteIf.slave mgt_axil, + // Misc + output logic [31:0] phy_status, + input logic [31:0] mac_ctrl, + output logic [31:0] mac_status, + output logic phy_reset, + output logic link_up +); + + logic tx_ovfout; + logic tx_unfout; + logic stat_rx_aligned; + logic stat_auto_config_done; + logic stat_auto_config_done_bclk; + logic usr_tx_reset; + logic usr_rx_reset; + + // Heirarchical refference (xilinx says it will synthesize) + // eth_100g_bd_i/cmac_usplus_0/gt_rxrecclkout} + assign rx_rec_clk_out = eth_100g_bd_i.cmac_usplus_0.gt_rxrecclkout[0]; + //status registers + always_comb begin + phy_status = 0; + phy_status[0] = usr_tx_reset; + phy_status[1] = usr_rx_reset; + + end + + logic [8:0] pause_mask; // from mac ctl register bits 24:16 + + always_ff @(posedge mgt_clk) begin : mac_status_reg + if (mgt_rst) begin + mac_status <= 0; + end else begin + mac_status[0] <= mac_status[0] || tx_ovfout; + mac_status[1] <= mac_status[1] || tx_unfout; + mac_status[2] <= stat_rx_aligned; + mac_status[3] <= mac_status[3] || (!mgt_rx.tready && mgt_rx.tvalid); + mac_status[4] <= stat_auto_config_done; + mac_status[24:16] <= pause_mask; + end + end + + //extra simulation checks + localparam USE_MAC_CHECKS = 1; + if (USE_MAC_CHECKS) begin + always_ff @(posedge mgt_rx.clk) begin : check_no_holdoff + if (!mgt_rx.rst) begin + if (!mgt_rx.tready && mgt_rx.tvalid) begin + $fatal(1,"MAC RX can't hold off the MAC"); + end + assert(tx_ovfout==0) else + $fatal(1,"MAC TX had an overflow!"); + assert(tx_unfout==0) else + $fatal(1,"MAC TX had an underflow!"); + end + end + end + + initial begin + assert (mgt_tx.DATA_WIDTH == 512) else + $fatal("mgt_rx.DATA_WIDTH must be 512"); + // $clog2(512/8)+1 + assert (mgt_rx.USER_WIDTH == 7) else + $fatal("mgt_rx.USER_WIDTH must be 7"); + assert (mgt_tx.TDATA == 1) else + $fatal("mgt_tx.TDATA must be enabled"); + assert (mgt_tx.TUSER == 1) else + $fatal("mgt_tx.TUSER must be enabled"); + assert (mgt_tx.TKEEP == 1) else + $fatal("mgt_tx.TKEEP must be enabled"); + assert (mgt_tx.TLAST == 1) else + $fatal("mgt_tx.TLAST must be enabled"); + assert (mgt_rx.DATA_WIDTH == 512) else + $fatal("mgt_rx.DATA_WIDTH must be 512"); + // $clog2(512/8)+1 + assert (mgt_rx.USER_WIDTH == 7) else + $fatal("mgt_rx.DATA_WIDTH must be 7"); + assert (mgt_rx.TDATA == 1) else + $fatal("mgt_rx.TDATA must be enabled"); + assert (mgt_rx.TUSER == 1) else + $fatal("mgt_rx.TUSER must be enabled"); + assert (mgt_rx.TKEEP == 0) else + $fatal("mgt_rx.TKEEP must not be enabled"); + assert (mgt_rx.TLAST == 1) else + $fatal("mgt_rx.TLAST must be enabled"); + end + + AxiStreamIf #(.DATA_WIDTH(512),.TUSER(0),.TKEEP(0)) + eth100g_tx(mgt_clk,mgt_rst); + AxiStreamIf #(.DATA_WIDTH(512),.USER_WIDTH(7),.TKEEP(0)) + eth100g_rx(mgt_clk,mgt_rst); + + logic mgt_tx_idle; + logic mgt_tx_pause; + + always_comb begin + eth100g_tx.tdata = mgt_tx.tdata; + eth100g_tx.tuser = 0; + eth100g_tx.tkeep = mgt_tx.tkeep; + eth100g_tx.tvalid = mgt_tx.tvalid && !mgt_tx_pause; + eth100g_tx.tlast = mgt_tx.tlast; + mgt_tx.tready = eth100g_tx.tready && !mgt_tx_pause; + end + + always_comb begin + mgt_rx.tdata = eth100g_rx.tdata; + mgt_rx.tuser = eth100g_rx.tuser; + mgt_rx.tuser[mgt_rx.USER_WIDTH-1] = // assign error bit [MSB] + // CRC failure + eth100g_rx.tuser[mgt_rx.USER_WIDTH-1] || + // Missed a DATA word. + mgt_rx.tvalid && !mgt_rx.tready; + mgt_rx.tkeep = eth100g_rx.tkeep; + mgt_rx.tvalid = eth100g_rx.tvalid; + mgt_rx.tlast = eth100g_rx.tlast; + // The MAC ignores hold off. Data must be consumed every clock it is valid. + // eth100g_rx.tready = mgt_rx.tready; + end + + // This is a heavily replicated signal, add some pipeline + // to it to make it easier to spread out + logic mgt_rst_0; + + + // Flow control signals + // 0-7 map to PCP codes 0-7. 8 is a global pause request + logic [8:0] stat_rx_pause_req ; + logic [8:0] ctl_tx_pause_req ; // drive for at least 16 clocks + logic ctl_tx_resend_pause; // resend the pause request (tieing this high forces a spam of resend requests) + + // QuantaPeriod is 512 bit times or 5.12 ns + // resend pause requests so (quanta*QuantaPeriod)/(refresh*QuantaPeriod) is the percentage of BW that gets through. + // pause_mask is part of the mac_ctrl register + always_comb begin + ctl_tx_resend_pause = 0; + ctl_tx_pause_req = '0; + if (mgt_pause_req) begin + ctl_tx_pause_req = pause_mask; + end + end + logic mgt_tx_pause_req; + assign mgt_tx_pause_req = (pause_mask & stat_rx_pause_req) != 0; + always_ff @(posedge mgt_clk,posedge areset) begin : reset_timing_dff + if (areset) begin + mgt_rst_0 <= 1'b1; + mgt_rst <= 1'b1; + mgt_tx_pause <= 1'b0; + mgt_tx_idle <= 1'b1; + end else begin + mgt_rst_0 <= !link_up; + mgt_rst <= mgt_rst_0; + //idle until a valid sets + if (mgt_tx_idle) begin + if (!eth100g_tx.tvalid) begin + mgt_tx_pause <= mgt_tx_pause_req; + end else begin + // one clock packet + if (eth100g_tx.tvalid && eth100g_tx.tlast && eth100g_tx.tready) begin + mgt_tx_idle <= 1; + mgt_tx_pause <= mgt_tx_pause_req; + end else begin + mgt_tx_idle <= 0; + end + end + //set idle if end of packet is accepted + end else if (eth100g_tx.tvalid && eth100g_tx.tlast && eth100g_tx.tready) begin + mgt_tx_idle <= 1; + mgt_tx_pause <= mgt_tx_pause_req; + end + end + end + + always_comb phy_reset = usr_tx_reset || usr_rx_reset; + always_comb link_up = stat_rx_aligned && !phy_reset; + + // resets stat counts and moves the total to the readable version. + localparam PM_COUNT = 40000; + logic pm_tick = 0; + logic [15:0] pm_tick_count; + always_ff @(posedge mgt_axil.clk) begin : pm_tick_counter + if (mgt_axil.rst) begin + pm_tick_count = 0; + pm_tick = 0; + end else begin + if (pm_tick_count == PM_COUNT-1) begin + pm_tick_count = 0; + pm_tick = 1; + end else begin + pm_tick_count = pm_tick_count+1; + pm_tick = 0; + end + end + end + + `include "../../../../lib/axi4lite_sv/axi_lite.vh" + AxiLiteIf_v #(.DATA_WIDTH(mgt_axil.DATA_WIDTH),.ADDR_WIDTH(32)) + mgt_axil_v(.clk(mgt_axil.clk),.rst(mgt_axil.rst)); + + localparam AUTO_CONNECT=1; + // When enabled the port will automatically attempt to connect to an Ethernet partner + // without requiring any action from SW. If it is not defined, SW will have to perform + // a similar set of writes. Xilinx publishes a driver for the MAC, that we could associate. + // The sequence of writes was taken from the CMAC example, without any deep knowledge + // of what the standard Ethernet connection protocol is. + + // Inject writes to perform connection inbetween other SW writes to read the mac. + if (AUTO_CONNECT) begin : yes_auto_connect + // defined in https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf + // pg 187 + localparam CONFIGURATION_TX_REG1 = 32'h000C; + localparam ctl_tx_ctl_enable = 0; + localparam ctl_tx_ctl_tx_send_lfi = 3; + localparam ctl_tx_ctl_tx_send_rfi = 4; + localparam ctl_tx_ctl_tx_send_idle = 5; + localparam ctl_tx_ctl_test_pattern = 16; + + localparam CONFIGURATION_RX_REG1 = 32'h0014; + localparam ctl_rx_ctl_enable = 0; + localparam ctl_rx_ctl_rx_force_resync = 7; + localparam ctl_rx_ctl_test_pattern = 8; + + localparam RSFEC_CONFIG_INDICATION_CORRECTION = 32'h1000; + localparam rs_fec_in_ctl_rx_rsfec_enable_correction = 0; + localparam rs_fec_in_ctl_rx_rsfec_enable_indication = 1; + localparam rs_fec_in_ctl_rsfec_ieee_error_indication_mode = 2; + + localparam RSFEC_CONFIG_ENABLE = 32'h107C; + localparam rs_fec_in_ctl_rx_rsfec_enable = 0; + localparam rs_fec_in_ctl_tx_rsfec_enable = 1; + + // Extra configuration for Pause Frames (CMAC guide Pg 210) + //0x0084 : 32'h00003DFF [CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1] + //0x0088 : 32'h0001C631 [CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2] + //0x0048 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1] + //0x004C : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2] + //0x0050 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3] + //0x0054 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4] + //0x0058 : 32'h0000FFFF [CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5] + //0x0034 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1] + //0x0038 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2] + //0x003C : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3] + //0x0040 : 32'hFFFFFFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4] + //0x0044 : 32'h0000FFFF [CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5] + //0x0030 : 32'h000001FF [CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1] + + localparam CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1 = 32'h0084; + //3DFF - 0011 1101 1111 1111 + localparam ctl_rx_pause_en = 0; // 9 bits + localparam ctl_rx_enable_gcp = 10; + localparam ctl_rx_enable_pcp = 11; + localparam ctl_rx_enable_gpp = 12; + localparam ctl_rx_enable_ppp = 13; + localparam ctl_rx_pause_ack = 23; // 8 bits + localparam CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2 = 32'h0088; + //1C631 - 0001 1100 0110 0011 0001 + localparam ctl_rx_check_mcast_gcp = 0; //1 + localparam ctl_rx_check_ucast_gcp = 1; + localparam ctl_rx_check_sa_gcp = 2; + localparam ctl_rx_check_etype_gcp = 3; + localparam ctl_rx_check_opcode_gcp = 4; //1 + localparam ctl_rx_check_mcast_pcp = 5; //1 + localparam ctl_rx_check_ucast_pcp = 6; + localparam ctl_rx_check_sa_pcp = 7; + localparam ctl_rx_check_etype_pcp = 8; + localparam ctl_rx_check_opcode_pcp = 9; //1 + localparam ctl_rx_check_mcast_gpp = 10; //1 + localparam ctl_rx_check_ucast_gpp = 11; + localparam ctl_rx_check_sa_gpp = 12; + localparam ctl_rx_check_etype_gpp = 13; + localparam ctl_rx_check_opcode_gpp = 14; //1 + localparam ctl_rx_check_opcode_ppp = 15; //1 + localparam ctl_rx_check_mcast_ppp = 16; //1 + localparam ctl_rx_check_ucast_ppp = 17; + localparam ctl_rx_check_sa_ppp = 18; + localparam ctl_rx_check_etype_ppp = 19; + + localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1 = 32'h0048; + localparam ctl_tx_pause_quanta0 = 0; + localparam ctl_tx_pause_quanta1 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2 = 32'h004C; + localparam ctl_tx_pause_quanta2 = 0; + localparam ctl_tx_pause_quanta3 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3 = 32'h0050; + localparam ctl_tx_pause_quanta4 = 0; + localparam ctl_tx_pause_quanta5 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 = 32'h0054; + localparam ctl_tx_pause_quanta6 = 0; + localparam ctl_tx_pause_quanta7 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5 = 32'h0058; + localparam ctl_tx_pause_quanta8 = 0; + localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1 = 32'h0034; + localparam ctl_tx_pause_refresh_timer0 = 0; + localparam ctl_tx_pause_refresh_timer1 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2 = 32'h0038; + localparam ctl_tx_pause_refresh_timer2 = 0; + localparam ctl_tx_pause_refresh_timer3 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3 = 32'h003C; + localparam ctl_tx_pause_refresh_timer4 = 0; + localparam ctl_tx_pause_refresh_timer5 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4 = 32'h0040; + localparam ctl_tx_pause_refresh_timer6 = 0; + localparam ctl_tx_pause_refresh_timer7 = 16; + localparam CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5 = 32'h0044; + localparam ctl_tx_pause_refresh_timer8 = 0; + localparam CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1 = 32'h0030; + // 1FF + localparam ctl_tx_pause_enable = 0; // 9 bits + + + AxiLiteIf #(.DATA_WIDTH(mgt_axil.DATA_WIDTH),.ADDR_WIDTH(32)) + auto_axil(.clk(mgt_axil.clk),.rst(mgt_axil.rst)); + + typedef enum logic [4:0] { + ST_RESET = 5'd0, + ST_WR_CONFIGURATION_TX_REG1_IDLE = 5'd1, + ST_WR_RSFEC_CONFIG_INDICATION_CORRECTION = 5'd2, + ST_WR_RSFEC_CONFIG_ENABLE = 5'd3, + ST_WR_CONFIGURATION_RX_REG1 = 5'd4, + ST_WAIT = 5'd5, + ST_WR_CONFIGURATION_TX_REG1_TX_ENABLE = 5'd6, + ST_READY = 5'd7, + // EXTRA PAUSE WRITES + ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1 = 5'd8, + ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2 = 5'd9, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1 = 5'd10, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2 = 5'd11, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3 = 5'd12, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4 = 5'd13, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5 = 5'd14, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1 = 5'd15, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2 = 5'd16, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3 = 5'd17, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4 = 5'd18, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5 = 5'd19, + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1 = 5'd20 + } auto_connect_state_t; + + auto_connect_state_t auto_connect_state = ST_RESET; + logic auto_rst0, auto_rst1, auto_rst2, auto_rst3; + logic mgt_axil_in_progress; + logic w_req, aw_req; + logic phy_reset_bclk,stat_rx_aligned_bclk; + logic auto_enable; + + synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) phy_reset_sync_i ( + .clk(mgt_axil.clk), .rst(1'b0), .in(phy_reset), .out(phy_reset_bclk) + ); + + synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) rx_aligned_sync_i ( + .clk(mgt_axil.clk), .rst(1'b0), .in(stat_rx_aligned), .out(stat_rx_aligned_bclk) + ); + + synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) auto_config_done_sync_i ( + .clk(mgt_clk), .rst(1'b0), .in(stat_auto_config_done_bclk), .out(stat_auto_config_done) + ); + + + synchronizer #( .STAGES(2), .WIDTH(1), .INITIAL_VAL(0) ) auto_enable_sync_i ( + .clk(mgt_axil.clk), .rst(1'b0), .in(mac_ctrl[0]), .out(auto_enable) + ); + + synchronizer #( .STAGES(2), .WIDTH(9), .INITIAL_VAL(9'h100) ) pause_mask_sync_i ( + .clk(mgt_clk), .rst(1'b0), .in(mac_ctrl[24:16]), .out(pause_mask) + ); + + + always_ff @(posedge mgt_axil.clk) begin : auto_enable_logic + if (mgt_axil.rst) begin + auto_rst0 <= 1'b1; + auto_rst1 <= 1'b1; + auto_rst2 <= 1'b1; + auto_rst3 <= 1'b1; + auto_connect_state <= ST_RESET; + stat_auto_config_done_bclk <= 1'b0; + mgt_axil_in_progress <= 1'b0; + w_req <= 1'b0; + aw_req <= 1'b0; + + // default is to drive mgt_axi_through + /* write address channel */ + auto_axil.awaddr <= 'bX; + auto_axil.awvalid <= 1'b0; + mgt_axil.awready <= 1'b0; + /* write data channel */ + auto_axil.wdata <= 'bX; + auto_axil.wstrb <= 'b0; + auto_axil.wvalid <= 1'b0; + mgt_axil.wready <= 1'b0; + /* write resp channel */ + mgt_axil.bresp[1:0] <= 'b0; + mgt_axil.bvalid <= 1'b0; + auto_axil.bready <= 1'b0; + /* read address channel */ + auto_axil.araddr <= 'b0; + auto_axil.arvalid <= 1'b0; + mgt_axil.arready <= 1'b0; + /* read resp channel */ + mgt_axil.rdata <= 'bX; + mgt_axil.rresp[1:0] <= 'b0; + mgt_axil.rvalid <= 1'b0; + auto_axil.rready <= 1'b0; + + end else begin + // 4 clocks to mimic Xilinx Example behavior + auto_rst0 <= phy_reset_bclk; + auto_rst1 <= auto_rst0; + auto_rst2 <= auto_rst1; + auto_rst3 <= auto_rst2; + // assumes one access in flight at time (valid for standard Xilinx AXIL driver) + // set if anyone starts driving a W Address / W Data / R Address channel + if (auto_axil.awvalid || auto_axil.wvalid || auto_axil.arvalid) begin + mgt_axil_in_progress <= 1'b1; + // clear on an acknowledged response + end else if ((auto_axil.bvalid && auto_axil.bready) || + (auto_axil.rvalid && auto_axil.rready)) begin + mgt_axil_in_progress <= 1'b0; + end + + // default is to drive mgt_axi_through + /* write address channel */ + auto_axil.awaddr <= mgt_axil.awaddr; + auto_axil.awvalid <= mgt_axil.awvalid; + mgt_axil.awready <= auto_axil.awready; + /* write data channel */ + auto_axil.wdata <= mgt_axil.wdata; + auto_axil.wstrb <= mgt_axil.wstrb; + auto_axil.wvalid <= mgt_axil.wvalid; + mgt_axil.wready <= auto_axil.wready; + /* write resp channel */ + mgt_axil.bresp <= auto_axil.bresp; + mgt_axil.bvalid <= auto_axil.bvalid; + auto_axil.bready <= mgt_axil.bready; + /* read address channel */ + auto_axil.araddr <= mgt_axil.araddr; + auto_axil.arvalid <= mgt_axil.arvalid; + mgt_axil.arready <= auto_axil.arready; + /* read resp channel */ + mgt_axil.rdata <= auto_axil.rdata; + mgt_axil.rresp <= auto_axil.rresp; + mgt_axil.rvalid <= auto_axil.rvalid; + auto_axil.rready <= mgt_axil.rready; + + if (auto_rst3) begin + auto_connect_state = ST_RESET; + stat_auto_config_done_bclk <= 1'b0; + end else begin + case (auto_connect_state) + + ST_RESET: begin + stat_auto_config_done_bclk <= 1'b0; + if (!mgt_axil_in_progress && auto_enable) begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_connect_state <= ST_WR_CONFIGURATION_TX_REG1_IDLE; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_REG1_IDLE: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // start transmitting alignment pattern + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_ctl_enable] <= 0; + auto_axil.wdata[ctl_tx_ctl_tx_send_idle] <= 0; + auto_axil.wdata[ctl_tx_ctl_tx_send_lfi] <= 0; + auto_axil.wdata[ctl_tx_ctl_tx_send_rfi] <= 1; + auto_axil.wdata[ctl_tx_ctl_test_pattern] <= 0; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_RSFEC_CONFIG_INDICATION_CORRECTION; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_RSFEC_CONFIG_INDICATION_CORRECTION: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // configure fec + auto_axil.wdata <= 0; + auto_axil.wdata[rs_fec_in_ctl_rx_rsfec_enable_correction] <= 1; + auto_axil.wdata[rs_fec_in_ctl_rx_rsfec_enable_indication] <= 1; + auto_axil.wdata[rs_fec_in_ctl_rsfec_ieee_error_indication_mode] <= 1; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= RSFEC_CONFIG_INDICATION_CORRECTION; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_RSFEC_CONFIG_ENABLE; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_RSFEC_CONFIG_ENABLE: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // enable fec + auto_axil.wdata <= 0; + auto_axil.wdata[rs_fec_in_ctl_rx_rsfec_enable] <= 1; + auto_axil.wdata[rs_fec_in_ctl_tx_rsfec_enable] <= 1; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= RSFEC_CONFIG_ENABLE; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_RX_REG1; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_RX_REG1: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_rx_ctl_enable] <= 1; + auto_axil.wdata[ctl_rx_ctl_rx_force_resync] <= 0; + auto_axil.wdata[ctl_rx_ctl_test_pattern] <= 0; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_RX_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WAIT; + end + end + + ST_WAIT: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // don't drive any writes, but hold off bus + auto_axil.wdata <= 0; + auto_axil.wstrb <= 0; + auto_axil.wvalid <= 0; + auto_axil.awaddr <= 0; + auto_axil.awvalid <= 0; + auto_axil.bready <= 0; + if (stat_rx_aligned_bclk) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_REG1_TX_ENABLE; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_REG1_TX_ENABLE: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // stop transmitting alignment pattern + // and start transmitting data + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_ctl_enable] <= 1; + auto_axil.wdata[ctl_tx_ctl_tx_send_idle] <= 0; + auto_axil.wdata[ctl_tx_ctl_tx_send_lfi] <= 0; + auto_axil.wdata[ctl_tx_ctl_tx_send_rfi] <= 0; + auto_axil.wdata[ctl_tx_ctl_test_pattern] <= 0; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + if (PAUSE_EN) begin + auto_connect_state <= ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1; + w_req <= 1'b1; + aw_req <= 1'b1; + end else begin + auto_connect_state <= ST_READY; + end + end + end + + ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + //3DFF - 0011 1101 1111 1111 + auto_axil.wdata[ctl_rx_pause_en+:9] <= '1; + auto_axil.wdata[ctl_rx_enable_gcp] <= 1; + auto_axil.wdata[ctl_rx_enable_pcp] <= 1; + auto_axil.wdata[ctl_rx_enable_gpp] <= 1; + auto_axil.wdata[ctl_rx_enable_ppp] <= 1; + //ctl_rx_pause_ack = 23; // 8 bits NOT SET + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + //1C631 - 0001 1100 0110 0011 0001 + auto_axil.wdata[ctl_rx_check_mcast_gcp ] <= 1; //1 + auto_axil.wdata[ctl_rx_check_ucast_gcp ] <= 0; + auto_axil.wdata[ctl_rx_check_sa_gcp ] <= 0; + auto_axil.wdata[ctl_rx_check_etype_gcp ] <= 0; + auto_axil.wdata[ctl_rx_check_opcode_gcp] <= 1; //1 + auto_axil.wdata[ctl_rx_check_mcast_pcp ] <= 1; //1 + auto_axil.wdata[ctl_rx_check_ucast_pcp ] <= 0; + auto_axil.wdata[ctl_rx_check_sa_pcp ] <= 0; + auto_axil.wdata[ctl_rx_check_etype_pcp ] <= 0; + auto_axil.wdata[ctl_rx_check_opcode_pcp] <= 1; //1 + auto_axil.wdata[ctl_rx_check_mcast_gpp ] <= 1; //1 + auto_axil.wdata[ctl_rx_check_ucast_gpp ] <= 0; + auto_axil.wdata[ctl_rx_check_sa_gpp ] <= 0; + auto_axil.wdata[ctl_rx_check_etype_gpp ] <= 0; + auto_axil.wdata[ctl_rx_check_opcode_gpp] <= 1; //1 + auto_axil.wdata[ctl_rx_check_opcode_ppp] <= 1; //1 + auto_axil.wdata[ctl_rx_check_mcast_ppp ] <= 1; //1 + auto_axil.wdata[ctl_rx_check_ucast_ppp ] <= 0; + auto_axil.wdata[ctl_rx_check_sa_ppp ] <= 0; + auto_axil.wdata[ctl_rx_check_etype_ppp ] <= 0; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_quanta0+:16] <= PAUSE_QUANTA; + auto_axil.wdata[ctl_tx_pause_quanta1+:16] <= PAUSE_QUANTA; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_quanta2+:16] <= PAUSE_QUANTA; + auto_axil.wdata[ctl_tx_pause_quanta3+:16] <= PAUSE_QUANTA; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_quanta4+:16] <= PAUSE_QUANTA; + auto_axil.wdata[ctl_tx_pause_quanta5+:16] <= PAUSE_QUANTA; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_quanta6+:16] <= PAUSE_QUANTA; + auto_axil.wdata[ctl_tx_pause_quanta7+:16] <= PAUSE_QUANTA; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_quanta8+:16] <= PAUSE_QUANTA; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_refresh_timer0+:16] <= PAUSE_REFRESH; + auto_axil.wdata[ctl_tx_pause_refresh_timer1+:16] <= PAUSE_REFRESH; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_refresh_timer2+:16] <= PAUSE_REFRESH; + auto_axil.wdata[ctl_tx_pause_refresh_timer3+:16] <= PAUSE_REFRESH; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_refresh_timer4+:16] <= PAUSE_REFRESH; + auto_axil.wdata[ctl_tx_pause_refresh_timer5+:16] <= PAUSE_REFRESH; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_refresh_timer6+:16] <= PAUSE_REFRESH; + auto_axil.wdata[ctl_tx_pause_refresh_timer7+:16] <= PAUSE_REFRESH; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + auto_axil.wdata[ctl_tx_pause_refresh_timer8+:16] <= PAUSE_REFRESH; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_WR_CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1; + w_req <= 1'b1; + aw_req <= 1'b1; + end + end + + ST_WR_CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1: begin + mgt_axil.awready <= 0; + mgt_axil.wready <= 0; + mgt_axil.arready <= 0; + auto_axil.arvalid <= 0; + // turn on RX interface + auto_axil.wdata <= 0; + // 1FF + auto_axil.wdata[ctl_tx_pause_enable+:9] <= '1; + auto_axil.wstrb <= '1; + auto_axil.wvalid <= w_req; + auto_axil.awaddr <= CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1; + auto_axil.awvalid <= aw_req; + auto_axil.bready <= 1'b1; + if (auto_axil.wready) begin + auto_axil.wvalid <= 1'b0; + w_req <= 1'b0; + end + if (auto_axil.awready) begin + auto_axil.awvalid <= 1'b0; + aw_req <= 1'b0; + end + if (auto_axil.bvalid) begin + auto_connect_state <= ST_READY; + end + end + + ST_READY: begin + stat_auto_config_done_bclk <= 1'b1; + if (!stat_rx_aligned_bclk) begin + auto_connect_state <= ST_RESET; + end + end + + endcase + end + end + end + + always_comb begin + `AXI4LITE_ASSIGN(mgt_axil_v,auto_axil) + + // window address to 0x0000-x1FFF + mgt_axil_v.araddr = 0; + mgt_axil_v.araddr[12:0] = auto_axil.araddr[12:0]; + // window address to 0x0000-x1FFF + mgt_axil_v.awaddr = 0; + mgt_axil_v.awaddr[12:0] = auto_axil.awaddr[12:0]; + end + + end else begin : no_auto_connect + + always_comb begin + `AXI4LITE_ASSIGN(mgt_axil_v,mgt_axil) + + // window address to 0x0000-x1FFF + mgt_axil_v.araddr = 0; + mgt_axil_v.araddr[12:0] = mgt_axil.araddr[12:0]; + // window address to 0x0000-x1FFF + mgt_axil_v.awaddr = 0; + mgt_axil_v.awaddr[12:0] = mgt_axil.awaddr[12:0]; + + stat_auto_config_done_bclk = 1'b1; + end + end + + import PkgEth100gLbus::*; + + + lbus_t lbus_rx [3:0]; + lbus_t lbus_tx [3:0]; + logic lbus_tx_rdyout; + + eth_100g_lbus2axi #(.NUM_SEG(4)) lbus2axi ( + .axis(eth100g_rx), + .lbus_in(lbus_rx) + ); + + eth_100g_axi2lbus #(.NUM_SEG(4)) axi2lbus ( + .axis(eth100g_tx), + .lbus_rdy(lbus_tx_rdyout), + .lbus_out(lbus_tx) + ); + + eth_100g_bd eth_100g_bd_i ( + .refclk_clk_n(refclk_n), + .refclk_clk_p(refclk_p), + .gt_rx_gt_port_0_n(rx_n[0]), + .gt_rx_gt_port_0_p(rx_p[0]), + .gt_rx_gt_port_1_n(rx_n[1]), + .gt_rx_gt_port_1_p(rx_p[1]), + .gt_rx_gt_port_2_n(rx_n[2]), + .gt_rx_gt_port_2_p(rx_p[2]), + .gt_rx_gt_port_3_n(rx_n[3]), + .gt_rx_gt_port_3_p(rx_p[3]), + .init_clk(clk100), + .gt_tx_gt_port_0_n(tx_n[0]), + .gt_tx_gt_port_0_p(tx_p[0]), + .gt_tx_gt_port_1_n(tx_n[1]), + .gt_tx_gt_port_1_p(tx_p[1]), + .gt_tx_gt_port_2_n(tx_n[2]), + .gt_tx_gt_port_2_p(tx_p[2]), + .gt_tx_gt_port_3_n(tx_n[3]), + .gt_tx_gt_port_3_p(tx_p[3]), + .sys_reset(areset), + .usr_rx_reset(usr_rx_reset), + .usr_tx_reset(usr_tx_reset), + .gt_txusrclk2(mgt_clk), + .rx_clk(mgt_clk), //feedback in + .tx_ovfout(tx_ovfout), + .tx_unfout(tx_unfout), + .stat_rx_aligned(stat_rx_aligned), + .drp_clk(clk100), + .core_drp_daddr(10'b0), + .core_drp_den(1'b0), + .core_drp_di(16'b0), + .core_drp_do(), + .core_drp_drdy(), + .core_drp_dwe(1'b0), + `AXI4LITE_PORT_ASSIGN(s_axi,mgt_axil_v) + .pm_tick(pm_tick), + .ctl_tx_pause_req(ctl_tx_pause_req), + .ctl_tx_resend_pause(ctl_tx_resend_pause), + .stat_rx_pause_req(stat_rx_pause_req), + .eth100g_rx_lbus_seg0_data(lbus_rx[0].data), + .eth100g_rx_lbus_seg0_ena(lbus_rx[0].ena), + .eth100g_rx_lbus_seg0_eop(lbus_rx[0].eop), + .eth100g_rx_lbus_seg0_err(lbus_rx[0].err), + .eth100g_rx_lbus_seg0_mty(lbus_rx[0].mty), + .eth100g_rx_lbus_seg0_sop(lbus_rx[0].sop), + .eth100g_rx_lbus_seg1_data(lbus_rx[1].data), + .eth100g_rx_lbus_seg1_ena(lbus_rx[1].ena), + .eth100g_rx_lbus_seg1_eop(lbus_rx[1].eop), + .eth100g_rx_lbus_seg1_err(lbus_rx[1].err), + .eth100g_rx_lbus_seg1_mty(lbus_rx[1].mty), + .eth100g_rx_lbus_seg1_sop(lbus_rx[1].sop), + .eth100g_rx_lbus_seg2_data(lbus_rx[2].data), + .eth100g_rx_lbus_seg2_ena(lbus_rx[2].ena), + .eth100g_rx_lbus_seg2_eop(lbus_rx[2].eop), + .eth100g_rx_lbus_seg2_err(lbus_rx[2].err), + .eth100g_rx_lbus_seg2_mty(lbus_rx[2].mty), + .eth100g_rx_lbus_seg2_sop(lbus_rx[2].sop), + .eth100g_rx_lbus_seg3_data(lbus_rx[3].data), + .eth100g_rx_lbus_seg3_ena(lbus_rx[3].ena), + .eth100g_rx_lbus_seg3_eop(lbus_rx[3].eop), + .eth100g_rx_lbus_seg3_err(lbus_rx[3].err), + .eth100g_rx_lbus_seg3_mty(lbus_rx[3].mty), + .eth100g_rx_lbus_seg3_sop(lbus_rx[3].sop), + .eth100g_tx_lbus_seg0_data(lbus_tx[0].data), + .eth100g_tx_lbus_seg0_ena(lbus_tx[0].ena), + .eth100g_tx_lbus_seg0_eop(lbus_tx[0].eop), + .eth100g_tx_lbus_seg0_err(lbus_tx[0].err), + .eth100g_tx_lbus_seg0_mty(lbus_tx[0].mty), + .eth100g_tx_lbus_seg0_sop(lbus_tx[0].sop), + .eth100g_tx_lbus_seg1_data(lbus_tx[1].data), + .eth100g_tx_lbus_seg1_ena(lbus_tx[1].ena), + .eth100g_tx_lbus_seg1_eop(lbus_tx[1].eop), + .eth100g_tx_lbus_seg1_err(lbus_tx[1].err), + .eth100g_tx_lbus_seg1_mty(lbus_tx[1].mty), + .eth100g_tx_lbus_seg1_sop(lbus_tx[1].sop), + .eth100g_tx_lbus_seg2_data(lbus_tx[2].data), + .eth100g_tx_lbus_seg2_ena(lbus_tx[2].ena), + .eth100g_tx_lbus_seg2_eop(lbus_tx[2].eop), + .eth100g_tx_lbus_seg2_err(lbus_tx[2].err), + .eth100g_tx_lbus_seg2_mty(lbus_tx[2].mty), + .eth100g_tx_lbus_seg2_sop(lbus_tx[2].sop), + .eth100g_tx_lbus_seg3_data(lbus_tx[3].data), + .eth100g_tx_lbus_seg3_ena(lbus_tx[3].ena), + .eth100g_tx_lbus_seg3_eop(lbus_tx[3].eop), + .eth100g_tx_lbus_seg3_err(lbus_tx[3].err), + .eth100g_tx_lbus_seg3_mty(lbus_tx[3].mty), + .eth100g_tx_lbus_seg3_sop(lbus_tx[3].sop), + .eth100g_tx_tx_rdyout(lbus_tx_rdyout)); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_axis2lbus.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_axis2lbus.sv new file mode 100644 index 000000000..a3c319043 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_axis2lbus.sv @@ -0,0 +1,120 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: eth_100g_axi2lbus +// +// Description: +// Translate from AXI4S (Xilinx segmented ifc) to lbus. +// +// Built using example provided from Xilinx +// +// Parameters: +// - FIFO_DEPTH - FIFO will be 2** deep +// - NUM_SEG - Number of lbus segments coming in + +import PkgEth100gLbus::*; + +module eth_100g_axi2lbus #( + parameter FIFO_DEPTH = 5, + parameter NUM_SEG = 4 +) +( + + // AXIS IF + AxiStreamIf.slave axis, + + // Lbus Segments + + input logic lbus_rdy, + output lbus_t lbus_out [NUM_SEG-1:0] + +); + + localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG; + localparam SEG_BYTES = SEG_DATA_WIDTH/8; + localparam SEG_MTY_WIDTH = $clog2(SEG_BYTES); + + // post rotation lbus signals + lbus_t lbus_d [NUM_SEG-1:0]; + + // Find last so we can find SOP + logic found_last; + + // Propagate ready when asserting , propagate delayed ready while deasserting + logic axis_tready_i; + assign axis.tready = axis_tready_i | lbus_rdy; + + always @(posedge axis.clk) begin + axis_tready_i <= lbus_rdy; + end + + //declare a segment width axis bus so I can use it's methods + AxiStreamIf #(.DATA_WIDTH(SEG_DATA_WIDTH),.USER_WIDTH($clog2(SEG_BYTES))) + seg_axi (axis.clk, axis.rst); + assign seg_axi.tlast = 1'b1; + + logic [NUM_SEG:0] valid; + assign valid[NUM_SEG] = 1'b0; + + genvar b; + genvar s; + generate begin : lbus_gen + for (s=0; s < NUM_SEG; s=s+1) begin : segment_loop + // Reverse data byte ordering on each segment + for (b = 0; b < DATA_WIDTH/32; b=b+1) begin : byte_loop + assign lbus_d[s].data[b*8 +: 8] = axis.tdata[((s+1)*(DATA_WIDTH/NUM_SEG)-8-(b*8)) +: 8]; + end : byte_loop + // valid if tkeep is set for any bytes in the segment + assign valid[s] = (| axis.tkeep[s*SEG_BYTES +: SEG_BYTES]) & axis.tvalid; + // enable when valid and transfering + assign lbus_d[s].ena = valid[s] & axis.tready; + // eop on last valid byte if last is set + // we init an extra valid bit to 0 so if all valid bits for all segments are set we trigger an eop on the final segment + assign lbus_d[s].eop = (valid[s] ^ valid[s+1]) & axis.tlast; + // set error on all segmetns if tuser is set + assign lbus_d[s].err = valid[s] & axis.tuser; + // translate keep to trailing bytes and invert sign + always_comb begin + if (lbus_d[s].eop) begin + lbus_d[s].mty = SEG_BYTES - seg_axi.keep2trailing(axis.tkeep[s*SEG_BYTES+: SEG_BYTES]); + end else begin + lbus_d[s].mty = 'b0; + end + end + //SOP can only occur on segment 0, so init all the bits to zero, then assign segment 0 + if (s==0) begin + assign lbus_d[s].sop = found_last & axis.tvalid & axis.tready; + end else begin + assign lbus_d[s].sop = 1'b0; + end + // assign the output DFF's + always_ff @(posedge axis.clk) begin + lbus_out[s].data <= lbus_d[s].data; + lbus_out[s].ena <= lbus_d[s].ena; + lbus_out[s].sop <= lbus_d[s].sop; + lbus_out[s].eop <= lbus_d[s].eop; + lbus_out[s].err <= lbus_d[s].err; + lbus_out[s].mty <= lbus_d[s].mty; + end + + end : segment_loop + end : lbus_gen + endgenerate + + + + // SOP Statemachine + always_ff @(posedge axis.clk) begin : sop_sm + if(axis.rst) begin + found_last <= 1'b1; + end else begin + if(axis.tvalid & axis.tlast & axis.tready) found_last <= 1'b1; + else if(axis.tvalid & axis.tready) found_last <= 1'b0; + end + end : sop_sm + +endmodule + + diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl new file mode 100644 index 000000000..624e0902e --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl @@ -0,0 +1,361 @@ + +################################################################ +# This is a generated script based on design: eth_100g_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source eth_100g_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name eth_100g_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:cmac_usplus:2.6\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set core_drp [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:drp_rtl:1.0 core_drp ] + + set eth100g_rx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_rx ] + + set eth100g_tx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_tx ] + + set gt_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_rx ] + + set gt_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_tx ] + + set refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {156250000} \ + ] $refclk + + set s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi + + + # Create ports + set ctl_tx_pause_req [ create_bd_port -dir I -from 8 -to 0 ctl_tx_pause_req ] + set ctl_tx_resend_pause [ create_bd_port -dir I ctl_tx_resend_pause ] + set drp_clk [ create_bd_port -dir I -type clk drp_clk ] + set gt_txusrclk2 [ create_bd_port -dir O -type clk gt_txusrclk2 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {eth100g_rx:eth100g_tx} \ + CONFIG.FREQ_HZ {322265625} \ + ] $gt_txusrclk2 + set init_clk [ create_bd_port -dir I -type clk init_clk ] + set pm_tick [ create_bd_port -dir I pm_tick ] + set rx_clk [ create_bd_port -dir I -type clk rx_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {322265625} \ + ] $rx_clk + set s_axi_aclk [ create_bd_port -dir I -type clk s_axi_aclk ] + set s_axi_sreset [ create_bd_port -dir I -type rst s_axi_sreset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $s_axi_sreset + set stat_rx_aligned [ create_bd_port -dir O stat_rx_aligned ] + set stat_rx_pause_req [ create_bd_port -dir O -from 8 -to 0 stat_rx_pause_req ] + set sys_reset [ create_bd_port -dir I -type rst sys_reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $sys_reset + set tx_ovfout [ create_bd_port -dir O tx_ovfout ] + set tx_unfout [ create_bd_port -dir O tx_unfout ] + set usr_rx_reset [ create_bd_port -dir O -type rst usr_rx_reset ] + set usr_tx_reset [ create_bd_port -dir O -type rst usr_tx_reset ] + + # Create instance: cmac_usplus_0, and set properties + set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:2.6 cmac_usplus_0 ] + set_property -dict [ list \ + CONFIG.CMAC_CAUI4_MODE {1} \ + CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \ + CONFIG.ENABLE_AXI_INTERFACE {1} \ + CONFIG.GT_DRP_CLK {100} \ + CONFIG.GT_GROUP_SELECT {X0Y4~X0Y7} \ + CONFIG.GT_REF_CLK_FREQ {156.25} \ + CONFIG.INCLUDE_AUTO_NEG_LT_LOGIC {0} \ + CONFIG.INCLUDE_RS_FEC {1} \ + CONFIG.INCLUDE_SHARED_LOGIC {2} \ + CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \ + CONFIG.LANE10_GT_LOC {NA} \ + CONFIG.LANE1_GT_LOC {X0Y4} \ + CONFIG.LANE2_GT_LOC {X0Y5} \ + CONFIG.LANE3_GT_LOC {X0Y6} \ + CONFIG.LANE4_GT_LOC {X0Y7} \ + CONFIG.LANE5_GT_LOC {NA} \ + CONFIG.LANE6_GT_LOC {NA} \ + CONFIG.LANE7_GT_LOC {NA} \ + CONFIG.LANE8_GT_LOC {NA} \ + CONFIG.LANE9_GT_LOC {NA} \ + CONFIG.NUM_LANES {4} \ + CONFIG.RX_CHECK_ACK {0} \ + CONFIG.RX_EQ_MODE {AUTO} \ + CONFIG.RX_FLOW_CONTROL {1} \ + CONFIG.TX_FLOW_CONTROL {1} \ + CONFIG.USER_INTERFACE {LBUS} \ + ] $cmac_usplus_0 + + # Create instance: tie_loopback, and set properties + set tie_loopback [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 tie_loopback ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {12} \ + ] $tie_loopback + + # Create instance: tie_zero, and set properties + set tie_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 tie_zero ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $tie_zero + + # Create interface connections + connect_bd_intf_net -intf_net RefClk_1 [get_bd_intf_ports refclk] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk] + connect_bd_intf_net -intf_net Rx_1 [get_bd_intf_ports gt_rx] [get_bd_intf_pins cmac_usplus_0/gt_rx] + connect_bd_intf_net -intf_net cmac_usplus_0_gt_tx [get_bd_intf_ports gt_tx] [get_bd_intf_pins cmac_usplus_0/gt_tx] + connect_bd_intf_net -intf_net cmac_usplus_0_lbus_rx [get_bd_intf_ports eth100g_rx] [get_bd_intf_pins cmac_usplus_0/lbus_rx] + connect_bd_intf_net -intf_net eth_100g_tx_1 [get_bd_intf_ports eth100g_tx] [get_bd_intf_pins cmac_usplus_0/lbus_tx] + connect_bd_intf_net -intf_net sDrp_1 [get_bd_intf_ports core_drp] [get_bd_intf_pins cmac_usplus_0/core_drp] + connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_ports s_axi] [get_bd_intf_pins cmac_usplus_0/s_axi] + + # Create port connections + connect_bd_net -net SysClk_1 [get_bd_ports init_clk] [get_bd_pins cmac_usplus_0/init_clk] + connect_bd_net -net aResetIn_1 [get_bd_ports sys_reset] [get_bd_pins cmac_usplus_0/sys_reset] + connect_bd_net -net cmac_usplus_0_gt_txusrclk2 [get_bd_ports gt_txusrclk2] [get_bd_pins cmac_usplus_0/gt_txusrclk2] + connect_bd_net -net cmac_usplus_0_stat_rx_aligned [get_bd_ports stat_rx_aligned] [get_bd_pins cmac_usplus_0/stat_rx_aligned] + connect_bd_net -net cmac_usplus_0_stat_rx_pause_req [get_bd_ports stat_rx_pause_req] [get_bd_pins cmac_usplus_0/stat_rx_pause_req] + connect_bd_net -net cmac_usplus_0_tx_ovfout [get_bd_ports tx_ovfout] [get_bd_pins cmac_usplus_0/tx_ovfout] + connect_bd_net -net cmac_usplus_0_tx_unfout [get_bd_ports tx_unfout] [get_bd_pins cmac_usplus_0/tx_unfout] + connect_bd_net -net cmac_usplus_0_usr_rx_reset [get_bd_ports usr_rx_reset] [get_bd_pins cmac_usplus_0/usr_rx_reset] + connect_bd_net -net cmac_usplus_0_usr_tx_reset [get_bd_ports usr_tx_reset] [get_bd_pins cmac_usplus_0/usr_tx_reset] + connect_bd_net -net ctl_tx_pause_req_1 [get_bd_ports ctl_tx_pause_req] [get_bd_pins cmac_usplus_0/ctl_tx_pause_req] + connect_bd_net -net ctl_tx_resend_pause_1 [get_bd_ports ctl_tx_resend_pause] [get_bd_pins cmac_usplus_0/ctl_tx_resend_pause] + connect_bd_net -net drp_clk_1 [get_bd_ports drp_clk] [get_bd_pins cmac_usplus_0/drp_clk] + connect_bd_net -net pm_tick_1 [get_bd_ports pm_tick] [get_bd_pins cmac_usplus_0/pm_tick] + connect_bd_net -net rx_clk_1 [get_bd_ports rx_clk] [get_bd_pins cmac_usplus_0/rx_clk] + connect_bd_net -net s_axi_aclk_1 [get_bd_ports s_axi_aclk] [get_bd_pins cmac_usplus_0/s_axi_aclk] + connect_bd_net -net s_axi_sreset_1 [get_bd_ports s_axi_sreset] [get_bd_pins cmac_usplus_0/s_axi_sreset] + connect_bd_net -net tie_loopback_dout [get_bd_pins cmac_usplus_0/gt_loopback_in] [get_bd_pins tie_loopback/dout] + connect_bd_net -net tie_zero_dout [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins tie_zero/dout] + + # Create address segments + create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] SEG_cmac_usplus_0_Reg + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_lbus2axis.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_lbus2axis.sv new file mode 100644 index 000000000..0fd1ab42f --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/eth_100g_lbus2axis.sv @@ -0,0 +1,555 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: eth_100g_lbus2axi +// +// Description: +// Translate from lbus (xilinx segmented ifc) to +// AXI4S. +// +// Built using example provided from Xilinx +// +// Parameters: +// - FIFO_DEPTH - FIFO will be 2** deep +// - NUM_SEG - Number of lbus segments coming in +// +// Notes on timing difficulty +// The path back to pop is challenged +// -LBUS is popped out of the FIFO (SRL read can be slow) +// -LBUS is rotated N to 1 Mux (N= number of segments) For 100g N=4 +// -Find where EOP is (search for the first 1) +// -Unrotate the number of words and use that to calculate pop +// +// Fifo Output +// Data starts from the SRL and is indexed by the read pointer +// Data_Valid comes from a comparison on fullness +// Invalid control is forced to zero (necessary for algorithm) +// It's not necessary to force all the data to zero just the control plane. +// +// Fifo output data is rotated (4 to 1) mux then reinterpreted as lbus data +// +// The rotated control signals are analyzed to determine +// no_eop, no_sop, some_empty, no_ena +// +// eop is specifically inspected in a 4in,4out function to find a pseudo +// one hot. this is unrotated along with enable, and combined with +// datavalid to determine the next pop, which controls incrementing of the +// rd_pointer. +// + +import PkgEth100gLbus::*; + +module eth_100g_lbus2axi #( + parameter FIFO_DEPTH = 5, + parameter NUM_SEG = 4 +) +( + + // AXIS IF + AxiStreamIf.master axis, + + // Lbus Segments + input lbus_t lbus_in [NUM_SEG-1:0] + +); + + localparam SEG_BYTES = SEG_DATA_WIDTH/8; + localparam SEG_MTY_WIDTH = $clog2(SEG_BYTES); + localparam SEG_SHMEAR_WIDTH = SEG_DATA_WIDTH + SEG_MTY_WIDTH + 4; + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// Data Input to FIFO /////////// + ////////////////////////////////////////////////////////////////////////////////// + + lbus_t lbus_fout_p[NUM_SEG-1:0]; //{ena,err,eop,sop,mty,data} + lbus_t lbus_fout[NUM_SEG-1:0]; //{ena,err,eop,sop,mty,data} + //FIFO Logic + logic push; + logic [NUM_SEG-1:0] pop; + + logic [NUM_SEG-1:0] full; + logic [NUM_SEG-1:0] empty; + + // always push the fifo on all lanes + assign push = lbus_in[0].ena; + + // For each lane of incoming data place it into a separate FIFO + generate + genvar b1,gseg1; + begin : gen_seg_fifo + for(gseg1 = 0; gseg1 < NUM_SEG; gseg1=gseg1+1) begin + + ////////////////////////////////////////////////////////////////////////////////// + // INLINE FIFO + ////////////////////////////////////////////////////////////////////////////////// + + // simulation error if we push a full fifo + always_comb begin + if (push) begin + assert (!full[gseg1]) else $error("Pushing full fifo!"); + end + end + + // limit fanout to improve timing + (* max_fanout = 75 *) logic [4:0] a; + + for (b1=0;b1<SEG_DATA_WIDTH;b1=b1+1) begin : gen_srl_data + SRLC32E srl_data( + .Q(lbus_fout_p[gseg1].data[b1]), .Q31(), + .A(a), + .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].data[b1]) + ); + end + for (b1=0;b1<SEG_MTY_WIDTH;b1=b1+1) begin : gen_srl_mty + SRLC32E srl_mty( + .Q(lbus_fout_p[gseg1].mty[b1]), .Q31(), + .A(a), + .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].mty[b1]) + ); + end + SRLC32E srl_err( + .Q(lbus_fout_p[gseg1].err), .Q31(), + .A(a), + .CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].err) + ); + + // empty on prebuffer and SRL + logic my_empty; + always @(posedge axis.clk) + begin + if(axis.rst) begin + a <= 0; + my_empty <= 1; + full[gseg1] <= 0; + end else if(pop[gseg1] & ~push) begin + full[gseg1] <= 0; + if(a==0) begin + my_empty <= 1; + end else begin + a <= a - 1; + end + end else if(push & ~pop[gseg1]) begin + my_empty <= 0; + if(~my_empty) begin + a <= a + 1; + end + if(a == 30) begin + full[gseg1] <= 1; + end + end + end + + // FIFO for time sensitive control signals. This creates a separate 31 deep fifo from + // DFF's on just 3 signals. The data signals continue to use an SRL to save space. + // The design bellow is a FIFO followed by a single DFF regsiter that is automatically + // prefilled when the FIFO has data. + logic [4:0] w_ptr,r_ptr,r_ptr_d,fullness; + logic [31:0] ena_mem, sop_mem, eop_mem; + + // Final fifo stage after memory to remove address muxing from timing path + // this adds one clock of latency to empty flag as it will take 2 clocks to propagate + // into fifo. + + //push critical timing signals to final flop. This adds 1 clock of latency on + // the final empty flag, but removes muxing of the memory elements + logic push_dff; + + //using r_ptr_d to avoid extra latency in fullness change + always_comb begin + if (pop[gseg1]) begin + r_ptr_d = r_ptr+1; + end else begin + r_ptr_d = r_ptr; + end + fullness = w_ptr-r_ptr_d; + push_dff = (fullness != 0) & (pop[gseg1] | empty[gseg1]); + end + + // speedier fifo implementation on these three control signals + // THE goal of this complexity is to have the outputs be a direct FF output + // instead of a muxed memory output. + always @(posedge axis.clk) + begin + if(axis.rst) begin + ena_mem <= '0; + sop_mem <= '0; + eop_mem <= '0; + lbus_fout_p[gseg1].ena <= 1'b0; + lbus_fout_p[gseg1].sop <= 1'b0; + lbus_fout_p[gseg1].eop <= 1'b0; + w_ptr <= 0; + r_ptr <= 0; + empty[gseg1] <= 1'b1; + end else begin + if(push) begin + ena_mem[w_ptr] <= lbus_in[gseg1].ena; + sop_mem[w_ptr] <= lbus_in[gseg1].sop; + eop_mem[w_ptr] <= lbus_in[gseg1].eop; + w_ptr <= w_ptr+1; + end + + r_ptr <= r_ptr_d; + + if (push_dff) begin + empty[gseg1] <= 1'b0; + lbus_fout_p[gseg1].ena <= ena_mem[r_ptr_d]; + lbus_fout_p[gseg1].sop <= sop_mem[r_ptr_d]; + lbus_fout_p[gseg1].eop <= eop_mem[r_ptr_d]; + end else if (pop[gseg1]) begin + empty[gseg1] <= 1'b1; + end + end + end + + // clear the enables if this fifo segment is not valid + always_comb begin + //default assignment + lbus_fout[gseg1] = lbus_fout_p[gseg1]; + if (empty[gseg1]) begin + // clear ena,err,eop,sop,mty (But not data - saves fanout!) + lbus_fout[gseg1].ena = 0; + lbus_fout[gseg1].err = 0; + lbus_fout[gseg1].eop = 0; + lbus_fout[gseg1].sop = 0; + lbus_fout[gseg1].mty = '0; + end else begin + // clear bits if the segment isn't enabled + lbus_fout[gseg1].eop = lbus_fout_p[gseg1].eop && lbus_fout_p[gseg1].ena; + lbus_fout[gseg1].sop = lbus_fout_p[gseg1].sop && lbus_fout_p[gseg1].ena; + lbus_fout[gseg1].err = lbus_fout_p[gseg1].err && lbus_fout_p[gseg1].ena; + end + end + + end + end : gen_seg_fifo + endgenerate + + // post rotation lbus signals + lbus_t lbus_rot [NUM_SEG-1:0]; + + // rotated signals as vectors for decision making + logic [NUM_SEG-1:0] ena; + logic [NUM_SEG-1:0] sop; + logic [NUM_SEG-1:0] eop; + logic [NUM_SEG-1:0] rot_ena; + logic [NUM_SEG-1:0] rot_sop; + logic [NUM_SEG-1:0] rot_eop; + logic [NUM_SEG-1:0] rot_empty; + + always_comb begin + foreach (rot_ena[s]) begin + ena[s] = lbus_fout[s].ena; + sop[s] = lbus_fout[s].sop; + eop[s] = lbus_fout[s].eop; + rot_ena[s] = lbus_rot[s].ena; + rot_sop[s] = lbus_rot[s].sop; + rot_eop[s] = lbus_rot[s].eop; + end + end + + + logic [$clog2(NUM_SEG)-1:0] rot; + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// Generate Decision Information /////////// + ////////////////////////////////////////////////////////////////////////////////// + logic no_sop; + logic no_eop; + logic no_ena; + logic some_empty; + logic send_idle; + + always_comb begin + no_sop = sop == 0; + no_eop = eop == 0; + no_ena = ena == 0; + // check for an empy byte + some_empty = 1'b0; + foreach (ena[seg]) begin : segment_loop + if (ena[seg] == 0) begin + some_empty = 1'b1; + end + end : segment_loop; + end + + always_comb begin + if (no_ena) begin + send_idle = 1'b0; + end else begin + // generally either there is an EOP with some empty segments + // or all empty segments on an unrotated bus. I'm not sure + // what this implies on an rotated bus + send_idle = no_eop & some_empty; + end + end + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// Calculate Pop /////////// + ////////////////////////////////////////////////////////////////////////////////// + // After rotation figure out how far till eop + + //========================================================================== + // one-hot to thermometer code + // The goal is to find how far down till we reach the first eop + // This represents the bytes we will trasnfer this clock + //========================================================================== + // Xilinx example + // case (in_reqs) + // 4'b1000: onehot2thermo = 4'b1111; + // + // 4'b1100: onehot2thermo = 4'b0111; + // 4'b0100: onehot2thermo = 4'b0111; + // + // 4'b1110: onehot2thermo = 4'b0011; + // 4'b0110: onehot2thermo = 4'b0011; + // 4'b0010: onehot2thermo = 4'b0011; + // + // 4'b1111: onehot2thermo = 4'b0001; + // 4'b0111: onehot2thermo = 4'b0001; + // 4'b0011: onehot2thermo = 4'b0001; + // 4'b0001: onehot2thermo = 4'b0001; + // + // default: onehot2thermo = 4'b0000; + // endcase + logic [NUM_SEG-1:0] rot_xfer_now; + logic [NUM_SEG-1:0] mask [NUM_SEG-1:0]; + logic [NUM_SEG-1:0] m1hot [NUM_SEG-1:0]; + logic [NUM_SEG-1:0] meop [NUM_SEG-1:0]; + logic [NUM_SEG-1:0] match; + + always_comb begin + rot_xfer_now = '0; + foreach (rot_eop[s]) begin + // The function + // XXX1=>0001 + // XX10=>0011 + // X100=>0111 + // 1000=>1111 + // MASK + // 2**(0+1)-1 = 0001 + // 2**(1+1)-1 = 0011 + // 2**(2+1)-1 = 0111 + // 2**(3+1)-1 = 1111 + mask[s] = 2**(s+1)-1; // Constant + // MASK + // 2**0 = 0001 + // 2**1 = 0010 + // 2**2 = 0100 + // 2**3 = 1000 + m1hot[s] = 2**s; // Constant + // Mask valid_eop + meop[s] = rot_eop & mask[s]; + // compare against 1hot + match[s] = meop[s] == m1hot[s]; + if (match[s]) begin + rot_xfer_now = mask[s]; + end + end + end + + // unrotate the values and calculate pop + logic [NUM_SEG-1:0] xfer_now; + logic [NUM_SEG-1:0] filler_seg; + + always_comb begin + if (send_idle) + xfer_now = '0; + else if (no_eop | no_sop) + xfer_now = '1; + else + // rotate left + xfer_now = {rot_xfer_now,rot_xfer_now} >> (NUM_SEG - rot); + end + + // Flush out valid segments with no enable + assign filler_seg = ~ena & ~empty; + + assign pop = (xfer_now | filler_seg) & ~empty; + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// Calculate Rotate for the next clock /////////// + ////////////////////////////////////////////////////////////////////////////////// + logic [$clog2(NUM_SEG)-1:0] next_rot; + always_comb begin + next_rot = 0; + foreach (rot_empty[s]) begin + if (~rot_empty[s] & lbus_rot[s].sop) begin + next_rot = s; + end + end + end + + always @(posedge axis.clk) + begin + if(axis.rst) begin + rot <= '0; + //no valid data on any segment + end else if( no_ena ) begin + rot <= '0; + // If EOP, but no SoP + end else if( no_sop & ~no_eop & some_empty) begin + rot <= '0; + // If SOP, accumulate rotation to push to seg 0 + end else if( ~no_sop ) begin + rot <= rot+next_rot; + end + end + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// Rotation of segments from fifo output /////////// + ////////////////////////////////////////////////////////////////////////////////// + generate + genvar b2,gseg2; + begin : rotate_lbus + //perform a bitwise rotation. + for(b2 = 0; b2 < SEG_SHMEAR_WIDTH; b2=b2+1) begin + logic [NUM_SEG-1:0] slice, slice_rotated; + + //copy a horizontal slice across the segments + for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin + assign slice[gseg2] = lbus_fout[gseg2][b2]; + end + + // rotate the slice (should make SEG_SHMEAR_WIDTH copies of NUM_SEG to 1 mux) + assign slice_rotated = {slice,slice} >> rot; //rotate_right + + // Copy slice back to the struct + for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin + assign lbus_rot[gseg2][b2] = slice_rotated[gseg2]; + end + + end + end : rotate_lbus + endgenerate + + always_comb begin : rotate_data_valid + rot_empty = {empty,empty} >> rot; //rotate_right + end : rotate_data_valid + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// LBUS out DFF ///////////////////// + ////////////////////////////////////////////////////////////////////////////////// + // This pipe stage is mainly to allow suming MTY bits and to add space for + // Vivado to try to pipeline the output + // post rotation lbus signals + lbus_t lbus_out [NUM_SEG-1:0]; + logic [NUM_SEG-1:0] axi_seg_valid; + + always_ff @(posedge axis.clk) + begin + if (axis.rst) begin + foreach (lbus_out[seg]) begin : segment_loop + lbus_out[seg] <= '0; + end + axi_seg_valid <= '0; + end else begin + lbus_out <= lbus_rot; + if (send_idle) + axi_seg_valid <= '0; + else if (no_eop) + axi_seg_valid <= '1; + else + axi_seg_valid <= rot_xfer_now; + end + end + + //////////////////////////////////////////////////////////////////////////// + // Generate AXI + //////////////////////////////////////////////////////////////////////////// + logic [axis.DATA_WIDTH - 1:0] axis_tdata_w; + logic [$clog2(axis.DATA_WIDTH/8) - 1:0] axis_tuser_bytes_w; + logic [axis.DATA_WIDTH/8 - 1:0] axis_tkeep_w; + logic [NUM_SEG-1:0] axis_tlast_w; + logic [NUM_SEG-1:0] axis_tvalid_w; + logic [NUM_SEG-1:0] axis_tuser_err_w; + + always_comb begin : axis_translate + axis_tuser_bytes_w = 'd0; // init to zero before summing + foreach (axis_tvalid_w[seg]) begin : segment_loop + axis_tvalid_w[seg] = lbus_out[seg].ena & axi_seg_valid[seg]; + axis_tlast_w[seg] = lbus_out[seg].eop; + axis_tuser_err_w[seg] = lbus_out[seg].err; + + // sum all the segment mty vectors + if (lbus_out[seg].ena && axi_seg_valid[seg]) begin + axis_tuser_bytes_w += SEG_DATA_WIDTH/8 - lbus_out[seg].mty; + end + + // 512 bit word = 64 bytes = 4 X 128 bit(16 byte) segments + // assign bytes : LbusOrder + // S0 : S0B0..S0B15 + // S1 : S1B0..S1B15 + // S2 : S2B0..S2B15 + // S3 : S3B0..S3B15 + // AXI (swap Endianess on each segment) + // AXI = S3B15..S3B0, S2B15..S2B0, S1B15..S1B0, S0B15..S0B0 + for(int b = 0; b < SEG_BYTES; b=b+1) begin : tdata_loop + // ( 1 * 128 )-8- 0*8) 120+:8 = S0B0 + // ( 1 * 128 )-8- 1*8) 112+:8 = S0B1 + // ... + // ( 1 * 128 )-8-14*8) 8+:8 = S0B14 + // ( 1 * 128 )-8-15*8) 0+:8 = S0B15 + //////////////////////////////////// + // ( 2 * 128 )-8- 0*8) 248+:8 = S1B0 + // ( 2 * 128 )-8- 1*8) 240+:8 = S1B1 + // ... + // ( 2 * 128 )-8-14*8) 136+:8 = S1B14 + // ( 2 * 128 )-8-15*8) 128+:8 = S1B15 + //////////////////////////////////// + // ... + //////////////////////////////////// + // ( 4 * 128 )-8- 0*8) 504+:8 = S3B0 + // ( 4 * 128 )-8- 1*8) 496+:8 = S3B1 + // ... + // ( 4 * 128 )-8-14*8) 136+:8 = S3B14 + // ( 4 * 128 )-8-15*8) 384+:8 = S3B15 + axis_tdata_w[((seg+1)*axis.DATA_WIDTH/NUM_SEG-8-b*8) +: 8] = lbus_out[seg].data[b*8 +: 8]; + end : tdata_loop + end : segment_loop + end : axis_translate + + // convert bytes to keep + always_comb begin + axis_tkeep_w = '1; + if (axis_tlast_w != 0 && axis_tuser_bytes_w != 0) begin + foreach(axis_tkeep_w[b]) begin + axis_tkeep_w[b] = axis_tuser_bytes_w > b; + end + end + end + + ////////////////////////////////////////////////////////////////////////////////// + ////////////////// AXIS output flop ///////////////////// + ////////////////////////////////////////////////////////////////////////////////// + + localparam AXIS_MTY_WIDTH = $clog2(axis.BYTES_PER_WORD); + + always_ff @(posedge axis.clk) + begin + if (axis.rst) begin + axis.tdata <= '0; + axis.tvalid <= 1'b0; + axis.tlast <= 1'b0; + axis.tuser <= '0; + axis.tkeep <= '0; + end else begin + axis.tdata <= axis_tdata_w; + axis.tvalid <= |axis_tvalid_w; + axis.tlast <= |axis_tlast_w; + + if (axis.TKEEP == 1) begin + axis.tkeep <= axis_tkeep_w; + end else begin + axis.tkeep <= 'X; + end + + // trailing bytes in last word + axis.tuser[AXIS_MTY_WIDTH-1:0] <= axis_tuser_bytes_w; + // MSB is error + axis.tuser[AXIS_MTY_WIDTH] <= |axis_tuser_err_w; + end + end + +endmodule diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile new file mode 100644 index 000000000..5ec8b6868 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile @@ -0,0 +1,62 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../../../../top) +# Include viv_sim_preamble after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs +include $(BASE_DIR)/../lib/fifo/Makefile.srcs + + +# If you generate the Xilinx CORE with an AXI interface you can find Xilinx's LBUS translators here +#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_lbus2axis_segmented_top.v) \ +#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \ + +DESIGN_SRCS = $(abspath \ +$(abspath ../eth_100g_axis2lbus.sv) \ +$(abspath ../eth_100g_lbus2axis.sv) \ +$(FIFO_SRCS) \ +$(AXI4S_SV_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4 +MODELSIM_ARGS += glbl -t 1fs +# Define toplevel module +TB_TOP_MODULE ?= lbus_all_tb +SIM_TOP = $(TB_TOP_MODULE) + +SIM_SRCS = \ +$(abspath ../PkgEth100gLbus.sv) \ +$(abspath axi_lbus_tb.sv) \ +$(abspath lbus_axi_tb.sv) \ +$(abspath $(TB_TOP_MODULE).sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ + +# Suppressing the following worthless reminder. +#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] - +# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time +SVLOG_ARGS = -suppress 2583 -keep_delta +VLOG_ARGS = -keep_delta + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv new file mode 100644 index 000000000..cfde2d5aa --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv @@ -0,0 +1,285 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: axi_lbus_tb +// +// Description: +// +// Testbench for eth_interface +// + +module axi_lbus_tb #( + parameter TEST_NAME = "" +)( + /* no IO */ +); + // Include macros and time declarations for use with PkgTestExec + `define TEST_EXEC_OBJ test + `include "test_exec.svh" + import PkgAxiStreamBfm::*; + import PkgEthernet::*; + import PkgTestExec::*; + import PkgEth100gLbus::*; + + localparam DATA_WIDTH = 512; + localparam USER_WIDTH = $clog2(DATA_WIDTH/8)+1; + localparam NUM_SEG = 4; + localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG; + localparam SEG_BYTES = SEG_DATA_WIDTH/8; + + //---------------------------------------------------- + // clocks + //---------------------------------------------------- + logic clk; + logic rst; + + sim_clock_gen #(.PERIOD(5), .AUTOSTART(1)) + clk_gen (.clk(clk), .rst(rst)); + + //---------------------------------------------------- + //interfaces + //---------------------------------------------------- + AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) + axis (clk, rst); + + //---------------------------------------------------- + // DUT + //---------------------------------------------------- + lbus_t lbus_out [NUM_SEG-1:0]; + lbus_t lbus_g [NUM_SEG-1:0]; + logic lbus_rdy = 1; + + eth_100g_axi2lbus #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT ( + .axis(axis), + .lbus_rdy(lbus_rdy), + .lbus_out(lbus_out) + ); + + //---------------------------------------------------- + // Xilinx golden model + // When Xilinx is generated with an AXI interface xilinx prints + // an axi2lbus converter that has trouble meeting timing + // this is preserved to allow comparison to that + // TODO: remove when timing is passing and refactor is done + //---------------------------------------------------- +/* + eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top GOLD ( + .core_clk(clk), + .core_rst(rst), + + // AXIS IF + .axis_tvalid(axis.tvalid), + .axis_tready(), + .axis_tdata(axis.tdata), + .axis_tlast(axis.tlast), + .axis_tkeep(axis.tkeep), + .axis_tuser(1'b0), + // LBUS IF + .lbus_rdyout(lbus_rdy), + .lbus_ovfout(1'b0), + .lbus_unfout(1'b0), + // Segment 0 + .lbus_ena0(lbus_g[0].ena), + .lbus_data0(lbus_g[0].data), + .lbus_sop0(lbus_g[0].sop), + .lbus_eop0(lbus_g[0].eop), + .lbus_mty0(lbus_g[0].mty), + .lbus_err0(lbus_g[0].err), + // Segment 1 + .lbus_ena1(lbus_g[1].ena), + .lbus_data1(lbus_g[1].data), + .lbus_sop1(lbus_g[1].sop), + .lbus_eop1(lbus_g[1].eop), + .lbus_mty1(lbus_g[1].mty), + .lbus_err1(lbus_g[1].err), + // Segment 2 + .lbus_ena2(lbus_g[2].ena), + .lbus_data2(lbus_g[2].data), + .lbus_sop2(lbus_g[2].sop), + .lbus_eop2(lbus_g[2].eop), + .lbus_mty2(lbus_g[2].mty), + .lbus_err2(lbus_g[2].err), + // Segment 3 + .lbus_ena3(lbus_g[3].ena), + .lbus_data3(lbus_g[3].data), + .lbus_sop3(lbus_g[3].sop), + .lbus_eop3(lbus_g[3].eop), + .lbus_mty3(lbus_g[3].mty), + .lbus_err3(lbus_g[3].err) + ); +*/ + //---------------------------------------------------- + //BFMS + //---------------------------------------------------- + + TestExec test = new(); + AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi = + new(.slave(null),.master(axis)); + + //--------------------------------------------------------------------------- + // Tests + //--------------------------------------------------------------------------- + + // use Test timeout to check reset goes away + task test_reset(); + test.start_test({TEST_NAME,"Wait for Reset"}, 10us); + wait(!rst); + repeat (10) @(posedge clk); + test.end_test(); + endtask : test_reset + + typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t; + typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t; + + + task automatic check_lbus(AxisPacket_t packets[$]); + + int idle_insert = 0; + int byte_count = 0; + int first_clk = 1; + + // loop over packets + foreach(packets[i]) begin + automatic raw_pkt_t pay; + pay = packets[i].dump_bytes; + + first_clk=1; + while (pay.size() > 0) begin + @(posedge clk); + if (lbus_rdy) begin + if (lbus_out[0].ena) begin + for (int s=0; s < NUM_SEG; s++) begin + byte_count = 0; + for (int b = SEG_DATA_WIDTH/8-1; b >= 0; b--) begin + if (pay.size() > 0) begin + assert (lbus_out[s].data[b*8 +: 8] == pay.pop_front()) else $error("Data Mismatch"); + byte_count++; + end + end + assert (lbus_out[s].ena == (byte_count > 0) ) else $error("Ena Mismatch"); + if (lbus_out[s].ena) begin + if (first_clk && s==0) begin + assert (lbus_out[s].sop == 1) else $error("Sop not set"); + end else begin + assert (lbus_out[s].sop == 0) else $error("Sop Set"); + end + assert (lbus_out[s].mty == (SEG_BYTES-byte_count) % SEG_BYTES) else $error("Mty Mismatch"); + assert (lbus_out[s].eop != (pay.size() > 0) ) else $error("Eop Mismatch"); + assert (lbus_out[s].err == 0) else $error("Err Mismatch"); // not checking error yet + end else begin + assert (lbus_out[s].sop == 0) else $error("Sop Set while disabled"); + assert (lbus_out[s].mty == 0) else $error("Mty set while disabled"); + assert (lbus_out[s].eop == 0) else $error("Eop set while disabled"); + assert (lbus_out[s].err == 0) else $error("Err set while disabled"); + end + end // segment loop + first_clk=0; + end // first segment is enabled + + end else begin //not lbus_rdy + for (int s=0; s < NUM_SEG; s++) begin + assert (lbus_out[s].ena == 0) else $error("Idle Ena set"); + assert (lbus_out[s].err == 0) else $error("Idle Err set"); + assert (lbus_out[s].sop == 0) else $error("Idle Sop set"); + assert (lbus_out[s].eop == 0) else $error("Idle Eop set"); + assert (lbus_out[s].mty == 0) else $error("Idle Mty non zero"); + end + end + end // while pay.size > 0 + end // foreach packet + + endtask : check_lbus; + + task automatic test_transfers(int num_samples[$]); + automatic AxisPacket_t send[$]; + automatic AxisPacket_t expected[$]; + automatic int sample_sum = 0; + + test.start_test({TEST_NAME,"Test Transfer"}, 200us); + + foreach (num_samples[i]) begin + automatic raw_pkt_t pay; + + expected[i] = new; + send[i] = new; + + get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256), + .ramp_inc(1),.pkt(pay),.SWIDTH(8)); + sample_sum += num_samples[i]; + send[i].push_bytes(pay); + + // rebuild the expected packet for comparison without the preamble + expected[i].push_bytes(pay); + end + + fork + begin // tx_thread + foreach (send[i]) begin + axi.put(send[i]); + end + end + begin //rx_thread + check_lbus(expected); + end + join + + test.end_test(); + endtask : test_transfers + + //---------------------------------------------------- + // Main test loop + //---------------------------------------------------- + initial begin : tb_main + automatic int num_samples[$]; + automatic int random_value; + clk_gen.reset(); + + // stalling is not allowed by whoever is reading the MAC + // i.e. ready is ignored + axi.set_master_stall_prob(0); + axi.run(); + test_reset(); + + $display("Fixed Sequences"); + num_samples = {64,65,66,67,68,69,70,71}; + test_transfers(num_samples); + num_samples = {64,128,256,512,256,64,64,64}; + test_transfers(num_samples); + num_samples = {65,64,64,64,64,64,64,64}; + test_transfers(num_samples); + num_samples = {65,64,80,80,80,80,80,80}; + test_transfers(num_samples); + num_samples = {64,64,96,80,96,80,96,80}; + test_transfers(num_samples); + $display("Tons of 64"); + num_samples.delete(); + repeat(1000) begin + num_samples.push_back(64); + end + test_transfers(num_samples); + $display("Tons of 65"); + num_samples.delete(); + repeat(1000) begin + num_samples.push_back(65); + end + test_transfers(num_samples); + $display("Tons of Random"); + num_samples.delete(); + repeat(1000) begin + random_value = $urandom_range(64,512); + num_samples.push_back(random_value); + end + test_transfers(num_samples); + + + // End the TB, but don't $finish, since we don't want to kill other + // instances of this testbench that may be running. + test.end_tb(0); + + // Kill the clocks to end this instance of the testbench + clk_gen.kill(); + end // initial begin + +endmodule diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_all_tb.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_all_tb.sv new file mode 100644 index 000000000..98caa0a86 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_all_tb.sv @@ -0,0 +1,22 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: lbus_all_tb +// +// Description: +// +// Testbench for LBU<->AXI +// + +module lbus_all_tb #( + /* no PARAM */ +)( + /* no IO */ +); + + lbus_axi_tb #(.TEST_NAME("L2A")) L2A (); + axi_lbus_tb #(.TEST_NAME("A2L")) A2L (); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv new file mode 100644 index 000000000..fa5812abe --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv @@ -0,0 +1,343 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: lbus_axi_tb +// +// Description: +// +// Testbench for eth_interface +// + +module lbus_axi_tb #( + parameter TEST_NAME = "" +)( + /* no IO */ +); + // Include macros and time declarations for use with PkgTestExec + `define TEST_EXEC_OBJ test + `include "test_exec.svh" + import PkgAxiStreamBfm::*; + import PkgEthernet::*; + import PkgTestExec::*; + import PkgEth100gLbus::*; + + localparam DATA_WIDTH = 512; + localparam USER_WIDTH = $clog2(DATA_WIDTH/8)+1; + localparam NUM_SEG = 4; + localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG; + localparam SEG_BYTES = SEG_DATA_WIDTH/8; + + //---------------------------------------------------- + // clocks + //---------------------------------------------------- + logic clk; + logic rst; + + sim_clock_gen #(.PERIOD(5), .AUTOSTART(1)) + clk_gen (.clk(clk), .rst(rst)); + + //---------------------------------------------------- + //interfaces + //---------------------------------------------------- + AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) + axis (clk, rst); + + AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) + axig (clk, rst); + + //---------------------------------------------------- + // DUT + //---------------------------------------------------- + lbus_t lbus_in [NUM_SEG-1:0]; + + eth_100g_lbus2axi #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT ( + .axis(axis), + .lbus_in(lbus_in) + ); + + //---------------------------------------------------- + // Xilinx golden model + // When Xilinx is generated with an AXI interface xilinx prints + // a lbus2axis converter that has trouble meeting timing + // this is preserved to allow comparison to that + // TODO: remove when timing is passing and refactor is done + //---------------------------------------------------- +/* + eth_100g_bd_cmac_usplus_0_0_lbus2axis_segmented_top GOLD ( + .core_clk(clk), + .core_rst(rst), + + // AXIS IF + .axis_tvalid(axig.tvalid), + .axis_tdata(axig.tdata), + .axis_tlast(axig.tlast), + .axis_tkeep(axig.tkeep), + .axis_tuser(), + // Segment 0 + .lbus_ena0(lbus_in[0].ena), + .lbus_data0(lbus_in[0].data), + .lbus_sop0(lbus_in[0].sop), + .lbus_eop0(lbus_in[0].eop), + .lbus_mty0(lbus_in[0].mty), + .lbus_err0(lbus_in[0].err), + // Segment 1 + .lbus_ena1(lbus_in[1].ena), + .lbus_data1(lbus_in[1].data), + .lbus_sop1(lbus_in[1].sop), + .lbus_eop1(lbus_in[1].eop), + .lbus_mty1(lbus_in[1].mty), + .lbus_err1(lbus_in[1].err), + // Segment 2 + .lbus_ena2(lbus_in[2].ena), + .lbus_data2(lbus_in[2].data), + .lbus_sop2(lbus_in[2].sop), + .lbus_eop2(lbus_in[2].eop), + .lbus_mty2(lbus_in[2].mty), + .lbus_err2(lbus_in[2].err), + // Segment 3 + .lbus_ena3(lbus_in[3].ena), + .lbus_data3(lbus_in[3].data), + .lbus_sop3(lbus_in[3].sop), + .lbus_eop3(lbus_in[3].eop), + .lbus_mty3(lbus_in[3].mty), + .lbus_err3(lbus_in[3].err) + ); +*/ + //---------------------------------------------------- + //BFMS + //---------------------------------------------------- + + TestExec test = new(); + AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi = + new(.slave(axis),.master(null)); + + //--------------------------------------------------------------------------- + // Tests + //--------------------------------------------------------------------------- + + // use Test timeout to check reset goes away + task test_reset(); + test.start_test({TEST_NAME,"Wait for Reset"}, 10us); + wait(!rst); + repeat (10) @(posedge clk); + test.end_test(); + endtask : test_reset + + typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t; + typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t; + + task automatic clear_lbus_in(); + for (int i=0 ; i < NUM_SEG ; ++i) begin + lbus_in[i].data = 'b0; + lbus_in[i].mty = 'b0; + lbus_in[i].sop = 1'b0; + lbus_in[i].eop = 1'b0; + lbus_in[i].err = 1'b0; + lbus_in[i].ena = 1'b0; + end + endtask : clear_lbus_in; + + task automatic send_lbus(AxisPacket_t packets[$]); + + int seg = 0; + int b = 0; + int idle_insert = 0; + + // loop over packets + foreach(packets[i]) begin + automatic raw_pkt_t pay; + pay = packets[i].dump_bytes; + // set for the first segment + lbus_in[seg].sop = 1; + // empty this packets payload + while (pay.size() > 0) begin + lbus_in[seg].ena = 1; + lbus_in[seg].data |= pay.pop_front()<<(SEG_DATA_WIDTH-b*8-8); + if (pay.size() == 0) begin + lbus_in[seg].eop = 1; + lbus_in[seg].mty = SEG_DATA_WIDTH-1-b; + end + if (seg == NUM_SEG-1 && b == SEG_DATA_WIDTH/8-1) begin + @(posedge clk); + clear_lbus_in(); + idle_insert++; + // insert period idle period + if (idle_insert > 2) begin + @(posedge clk); + idle_insert =0; + end + end + b = (b+1) % (SEG_DATA_WIDTH/8); + if (b==0) begin + seg = (seg+1) % NUM_SEG; + end + end // pay.size > 0 + if (b != 0) begin + seg = (seg+1) % NUM_SEG; + if (seg == 0) begin + @(posedge clk); + clear_lbus_in(); + idle_insert++; + // insert period idle period + if (idle_insert > 2) begin + @(posedge clk); + idle_insert =0; + end + end + b = 0; + end + + // 25% of the time we start a new packet + if ($urandom_range(99) < 25) begin + b = 0; + seg = 0; + // 25% of the time add an idle cycle + if ($urandom_range(99) < 25) begin + @(posedge clk); + clear_lbus_in(); + idle_insert++; + // insert period idle period + if (idle_insert > 2) begin + idle_insert =0; + @(posedge clk); + end + @(posedge clk); + end else begin + @(posedge clk); + clear_lbus_in(); + idle_insert++; + // insert period idle period + if (idle_insert > 2) begin + idle_insert =0; + @(posedge clk); + end + end + end + + end // foreach packet + + @(posedge clk); + clear_lbus_in(); + + endtask : send_lbus; + + task automatic compare_packet(AxisPacket_t actual, expected); + + automatic XportPacket_t actual_copy = new(); + automatic XportPacket_t expected_copy = new(); + actual_copy.import_axis(actual); + expected_copy.import_axis(expected); + + expected_copy.tkeep_to_tuser(); + actual_copy.clear_unused_bytes(); + + if (!expected_copy.equal(actual_copy)) begin + $display("Expected"); + expected_copy.print(); + $display("Actual"); + actual_copy.print(); + if (!expected_copy.equal(actual_copy)) + $error("ERROR :: packet mismatch"); + + end + + endtask : compare_packet; + + task automatic test_transfers(int num_samples[$]); + automatic AxisPacket_t send[$]; + automatic AxisPacket_t expected[$]; + automatic int sample_sum = 0; + + test.start_test({TEST_NAME,"Test Transfer"}, 200us); + + foreach (num_samples[i]) begin + automatic raw_pkt_t pay; + + expected[i] = new; + send[i] = new; + + get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256), + .ramp_inc(1),.pkt(pay),.SWIDTH(8)); + sample_sum += num_samples[i]; + send[i].push_bytes(pay); + + // rebuild the expected packet for comparison without the preamble + expected[i].push_bytes(pay); + end + + fork + begin // tx_thread + send_lbus(send); + end + begin //rx_thread + foreach(expected[i]) begin + automatic AxisPacket_t actual; + axi.get(actual); + compare_packet(actual,expected[i]); + end + end + join + + test.end_test(); + endtask : test_transfers + + //---------------------------------------------------- + // Main test loop + //---------------------------------------------------- + initial begin : tb_main + automatic int num_samples[$]; + automatic int random_value; + clk_gen.reset(); + + // stalling is not allowed by whoever is reading the MAC + // i.e. ready is ignored + axi.slave_tready_init = 1'b1; + axi.set_master_stall_prob(0); + axi.set_slave_stall_prob(0); + axi.run(); + clear_lbus_in(); + test_reset(); + + $display("Fixed Sequences"); + num_samples = {64,65,66,67,68,69,70,71}; + test_transfers(num_samples); + num_samples = {64,128,256,512,256,64,64,64}; + test_transfers(num_samples); + num_samples = {65,64,64,64,64,64,64,64}; + test_transfers(num_samples); + num_samples = {65,64,80,80,80,80,80,80}; + test_transfers(num_samples); + num_samples = {64,64,96,80,96,80,96,80}; + test_transfers(num_samples); + $display("Tons of 64"); + num_samples.delete(); + repeat(1000) begin + num_samples.push_back(64); + end + test_transfers(num_samples); + $display("Tons of 65"); + num_samples.delete(); + repeat(1000) begin + num_samples.push_back(65); + end + test_transfers(num_samples); + $display("Tons of Random"); + num_samples.delete(); + repeat(1000) begin + random_value = $urandom_range(64,512); + num_samples.push_back(random_value); + end + test_transfers(num_samples); + + + // End the TB, but don't $finish, since we don't want to kill other + // instances of this testbench that may be running. + test.end_tb(0); + + // Kill the clocks to end this instance of the testbench + clk_gen.kill(); + end // initial begin + +endmodule diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/model_100gbe.sv b/fpga/usrp3/top/x400/ip/eth_100g_bd/model_100gbe.sv new file mode 100644 index 000000000..e7995dd44 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/model_100gbe.sv @@ -0,0 +1,234 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: model_100gbe +// +// Description: +// +// A wrapper of the 100gbe core to axistream interface. this model can be +// used drive packets into the X400 translated to serial Ethernet. This is +// generally pretty slower than just driving things in at the output of the +// mac. +// + +package Pkg100gbMac; + import PkgAxiLite::*; + import PkgAxiLiteBfm::*; + import PkgTestExec::*; + + localparam DATA_WIDTH =32; + localparam ADDR_WIDTH =15; + + typedef AxiLiteBfm #(DATA_WIDTH, ADDR_WIDTH) MacAxiLiteBfm_t; + + // defined in https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf + // pg 187 + localparam CONFIGURATION_TX_REG1 = 32'h000C; + localparam ctl_tx_ctl_enable = 0; + localparam ctl_tx_ctl_tx_send_lfi = 3; + localparam ctl_tx_ctl_tx_send_rfi = 4; + localparam ctl_tx_ctl_tx_send_idle = 5; + localparam ctl_tx_ctl_test_pattern = 16; + + localparam CONFIGURATION_RX_REG1 = 32'h0014; + localparam ctl_rx_ctl_enable = 0; + localparam ctl_rx_ctl_rx_force_resync = 7; + localparam ctl_rx_ctl_test_pattern = 8; + + localparam RSFEC_CONFIG_INDICATION_CORRECTION = 32'h1000; + localparam rs_fec_in_ctl_rx_rsfec_enable_correction = 0; + localparam rs_fec_in_ctl_rx_rsfec_enable_indication = 1; + localparam rs_fec_in_ctl_rsfec_ieee_error_indication_mode = 2; + + localparam RSFEC_CONFIG_ENABLE = 32'h107C; + localparam rs_fec_in_ctl_rx_rsfec_enable = 0; + localparam rs_fec_in_ctl_tx_rsfec_enable = 1; + + localparam STAT_RX_STATUS_REG = 32'h0204; + localparam stat_rx_status = 0; + localparam stat_rx_aligned = 1; + localparam stat_rx_misaligned = 2; + localparam stat_rx_aligned_err = 3; + + task automatic init_mac (int offset, MacAxiLiteBfm_t axi); + automatic logic [31:0] data; + automatic resp_t resp; + + // start transmitting alignment pattern + data = 0; + data[ctl_tx_ctl_enable] = 0; + data[ctl_tx_ctl_tx_send_idle] = 0; + data[ctl_tx_ctl_tx_send_lfi] = 0; + data[ctl_tx_ctl_tx_send_rfi] = 1; + data[ctl_tx_ctl_test_pattern] = 0; + axi.wr(CONFIGURATION_TX_REG1+offset,data); + + // configure fec + data = 0; + data[rs_fec_in_ctl_rx_rsfec_enable_correction] = 1; + data[rs_fec_in_ctl_rx_rsfec_enable_indication] = 1; + data[rs_fec_in_ctl_rsfec_ieee_error_indication_mode] = 1; + axi.wr(RSFEC_CONFIG_INDICATION_CORRECTION+offset,data); + + data = 0; + data[rs_fec_in_ctl_rx_rsfec_enable] = 1; + data[rs_fec_in_ctl_tx_rsfec_enable] = 1; + axi.wr(RSFEC_CONFIG_ENABLE+offset,data); + + // turn on RX interface + data = 0; + data[ctl_rx_ctl_enable] = 1; + data[ctl_rx_ctl_rx_force_resync] = 0; + data[ctl_rx_ctl_test_pattern] = 0; + axi.wr(CONFIGURATION_RX_REG1+offset,data); + + do begin + axi.rd_block(STAT_RX_STATUS_REG+offset,data,resp); + assert (resp==OKAY); + end while (data[stat_rx_aligned] !== 1); + + // stop transmitting alignment pattern + // and start transmitting data + data = 0; + data[ctl_tx_ctl_enable] = 1; + data[ctl_tx_ctl_tx_send_idle] = 0; + data[ctl_tx_ctl_tx_send_lfi] = 0; + data[ctl_tx_ctl_tx_send_rfi] = 0; + data[ctl_tx_ctl_test_pattern] = 0; + axi.wr(CONFIGURATION_TX_REG1+offset,data); + + endtask : init_mac + +endpackage : Pkg100gbMac + +module model_100gbe ( + input logic areset, + // 156.25 Mhz refclk + input logic ref_clk, + + // QSFP high-speed IO + output logic [3:0] tx_p, + output logic [3:0] tx_n, + input logic [3:0] rx_p, + input logic [3:0] rx_n, + + // CLK and RESET out + output logic mgt_clk, + output logic mgt_rst, + output logic link_up, + + // Data port + AxiStreamIf.slave mgt_tx, + AxiStreamIf.master mgt_rx + +); + + // Include macros and time declarations for use with PkgTestExec + `define TEST_EXEC_OBJ test + `include "test_exec.svh" + import PkgAxiLiteBfm::*; + import PkgTestExec::*; + + logic refclk_p; + logic refclk_n; + + logic clk40,clk40_rst; + logic clk100,clk100_rst; + logic phy_reset; + + assign refclk_p = ref_clk; + assign refclk_n = ~ref_clk; + + //interface + AxiLiteIf #(Pkg100gbMac::DATA_WIDTH,Pkg100gbMac::ADDR_WIDTH) + mgt_axil (clk40, clk40_rst); + //bfm + Pkg100gbMac::MacAxiLiteBfm_t axi = new(.master(mgt_axil)); + TestExec mac_test = new(); + + sim_clock_gen #(.PERIOD(25.0), .AUTOSTART(1)) + clk40_gen (.clk(clk40), .rst(clk40_rst)); + sim_clock_gen #(.PERIOD(100.0), .AUTOSTART(1)) + clk100_gen (.clk(clk100), .rst(clk100_rst)); + + initial begin : init_model + clk40_gen.reset(); + axi.run(); + wait(!clk40_rst); + repeat (10) @(posedge clk40); + + wait(!phy_reset); // both usr_clk's are ok + + mac_test.start_test("model_100gbe::Wait for MAC link_up", 150us); + //Added autoconnect - uncomment to test connecting over AXI + //Pkg100gbMac::init_mac(0,axi); + mac_test.end_test(); + end + + + AxiStreamIf #(.DATA_WIDTH(512),.USER_WIDTH(7),.TKEEP(0)) + eth100g_rx(mgt_clk,mgt_rst); + + always_comb begin + mgt_rx.tdata = eth100g_rx.tdata; + mgt_rx.tuser = eth100g_rx.tuser; + mgt_rx.tkeep = eth100g_rx.trailing2keep(eth100g_rx.tuser); + mgt_rx.tvalid = eth100g_rx.tvalid; + mgt_rx.tlast = eth100g_rx.tlast; + eth100g_rx.tready = mgt_rx.tready; + // The MAC ignores hold off. Data must be consumed every clock it is valid. + if (!mgt_rst) begin + if (!mgt_rx.tready && mgt_rx.tvalid) begin + $error("Model 100Gbe : can't hold off the MAC"); + end + end + end + + // model does not pause. Users could access this heirarchically to test it + logic mgt_pause_req; + assign mgt_pause_req = 1'b0; + + // hold off link up untill the stat_auto_config writes are complete + logic link_up_model; + logic [31:0] mac_status; + always_comb begin + link_up = link_up_model && mac_status[4]; + end + + eth_100g #(.PAUSE_QUANTA(10),.PAUSE_REFRESH(100)) eth_100gx ( + .areset(areset), + //-- Free running 100 MHz clock used for InitClk and AxiLite to mac + //-- 3.125 - 161.132812 MHz. + .clk100(clk100), + // MGT Reference Clock 100/125/156.25/161.1328125 MHz + .refclk_p(refclk_p), + .refclk_n(refclk_n), + // MGT TX/RX differential signals + .tx_p(tx_p), + .tx_n(tx_n), + .rx_p(rx_p), + .rx_n(rx_n), + // 322.26666 Mhz clock generated by 100G Phy from RefClock + .mgt_clk(mgt_clk), + .mgt_rst(mgt_rst), + // pause + .mgt_pause_req(mgt_pause_req), + //------------------------ AXI Stream TX Interface ------------------------ + .mgt_tx(mgt_tx), + //---------------------- AXI Stream RX Interface ------------------------ + // There is no RxTReady signal support by the Ethernet100G IP. Received data has to + // be read immediately or it is lost. + // tUser indicates an error on rcvd packet + .mgt_rx(eth100g_rx), + .mgt_axil(mgt_axil), + // LEDs of QSFP28 port + .phy_status(), + .mac_ctrl(32'h01000001), // autoconfig / pause mask set to global + .mac_status(mac_status), + .phy_reset(phy_reset), + .link_up(link_up_model) + ); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/x400/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..d1fe561c7 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,21 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_HDL_SIM_SRCS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk_sim_netlist.v \ +) + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..888840273 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>fifo_4k_2clk</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_4k_2clk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Disable_Timing_Violations" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/x400/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..5fd855017 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,21 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_HDL_SIM_SRCS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk_sim_netlist.v \ +) + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..cc0f896b8 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>fifo_short_2clk</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">31</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">30</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_short_2clk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">31</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">30</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">72</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.synchronization_stages" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/hb47_1to2/Makefile.inc b/fpga/usrp3/top/x400/ip/hb47_1to2/Makefile.inc new file mode 100644 index 000000000..895f2b50f --- /dev/null +++ b/fpga/usrp3/top/x400/ip/hb47_1to2/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_1TO2_SRCS = $(IP_BUILD_DIR)/hb47_1to2/hb47_1to2.xci + +IP_HB47_1TO2_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_1to2/, \ +hb47_1to2.xci.out \ +synth/hb47_1to2.vhd \ +) + +$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : $(IP_DIR)/hb47_1to2/hb47_1to2.xci + $(call BUILD_VIVADO_IP,hb47_1to2,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/hb47_1to2/hb47_1to2.xci b/fpga/usrp3/top/x400/ip/hb47_1to2/hb47_1to2.xci new file mode 100644 index 000000000..7959aa2fe --- /dev/null +++ b/fpga/usrp3/top/x400/ip/hb47_1to2/hb47_1to2.xci @@ -0,0 +1,298 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>hb47_1to2</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_CHANID_INCORRECT_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_OP_PATH_WIDTHS">35,35,35,35</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_PATH_WIDTHS">35,35,35,35</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_PATTERN">fixed</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE">hb47_1to2.mif</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE_LINES">48</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEMTYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEM_PACKING">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SIGN">0,0,0,0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SRC">0,0,2,2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_WIDTHS">18,18,18,18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_RELOAD">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_CONFIG">24</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_MODE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_PIPE_LEN">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">hb47_1to2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_PACKET_SIZE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_SYNC_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATAPATH_MEMTYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_IP_PATH_WIDTHS">16,16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEMTYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_PACKING">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_PSAMP_SRC">-0;-1;-0;-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SIGN">0,0,0,0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SRC">0,1,0,1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_WIDTHS">16,16,16,16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PX_PATH_WIDTHS">16,16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DECIM_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_MULT_CNFG">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTS_PACKED">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETn">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CONFIG_CHANNEL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERP_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IPBUFF_MEMTYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">29</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_ARRANGEMENT">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">96</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_CHANNELS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_FILTS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MADDS">24</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_RELOAD_SLOTS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TAPS">47</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPBUFF_MEMTYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPT_MADDS">none;none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OP_PATH_PSAMP_SRC">-0;-1;-0;-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_PATH_WIDTHS">18,18,18,18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERSAMPLING_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PX_PATH_SRC">0,1,2,3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RELOAD_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYMMETRY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_FIFO">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_TUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TDATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynquplus</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ZERO_PACKING_FACTOR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BestPrecision">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Blank_Output">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channel_Sequence">Basic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Frequency">300.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientSource">Vector</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientVector">-62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">no_coe_file_loaded</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Reload">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sets">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sign">Signed</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Structure">Inferred</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">24</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">hb47_1to2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_TUSER_Width">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Fractional_Bits">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Sign">Signed</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Width">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Decimation_Rate">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DisplayReloadOrder">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Architecture">Systolic_Multiply_Accumulate</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Selection">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Type">Interpolation</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GUI_Behaviour">Coregen</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_Files">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_COE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_Spec">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HardwareOversamplingRate">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ARESETn">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inter_Column_Pipe_Length">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interpolation_Rate">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TREADY">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multi_Column_Support">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Num_Reload_Slots">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Channels">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Paths">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_List">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Selection">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Rounding_Mode">Convergent_Rounding_to_Even</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Max">0.5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Min">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pattern_List">P4-0,P4-1,P4-2,P4-3,P4-4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Preference_For_Other_Storage">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Quantization">Integer_Coefficients</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RateSpecification">Output_Sample_Period</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Rate_Change_Type">Integer</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reload_File">no_coe_file_loaded</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Data_Vector">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Method">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Sync_Mode">On_Vector</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_FIFO">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SamplePeriod">0.5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sample_Frequency">0.001</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Select_Pattern">All</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Max">1.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Min">0.5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Zero_Pack_Factor">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplusRFSOC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu28dr</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvg1517</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1_AR73068</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Frequency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CoefficientVector" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sets" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sign" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Structure" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ColumnConfig" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Decimation_Rate" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Architecture" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ARESETn" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interpolation_Rate" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TREADY" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Channels" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Paths" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Rounding_Mode" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Quantization" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RateSpecification" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Data_Vector" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_DATA_Has_FIFO" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SamplePeriod" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Sample_Frequency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/hb47_2to1/Makefile.inc b/fpga/usrp3/top/x400/ip/hb47_2to1/Makefile.inc new file mode 100644 index 000000000..e4a865941 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/hb47_2to1/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_2TO1_SRCS = $(IP_BUILD_DIR)/hb47_2to1/hb47_2to1.xci + +IP_HB47_2TO1_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_2to1/, \ +hb47_2to1.xci.out \ +synth/hb47_2to1.vhd \ +) + +$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : $(IP_DIR)/hb47_2to1/hb47_2to1.xci + $(call BUILD_VIVADO_IP,hb47_2to1,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x400/ip/hb47_2to1/hb47_2to1.xci b/fpga/usrp3/top/x400/ip/hb47_2to1/hb47_2to1.xci new file mode 100644 index 000000000..e9af18853 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/hb47_2to1/hb47_2to1.xci @@ -0,0 +1,313 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>hb47_2to1</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_CHANID_INCORRECT_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_DATA_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_RELOAD_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_OP_PATH_WIDTHS">35,35</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_PATH_WIDTHS">35,35,35,35</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_PATTERN">fixed</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE">hb47_2to1.mif</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE_LINES">47</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEMTYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEM_PACKING">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SIGN">0,0,0,0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SRC">0,0,0,0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_WIDTHS">18,18,18,18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_RELOAD">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_WIDTH">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_CONFIG">47</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_MODE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_PIPE_LEN">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">hb47_2to1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_PACKET_SIZE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_SYNC_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIG_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATAPATH_MEMTYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_IP_PATH_WIDTHS">16,16,16,16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEMTYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_MEM_PACKING">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_PSAMP_SRC">-0,2;-1,3;0,-2;1,-3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SIGN">0,0,0,0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_SRC">0,1,2,3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_WIDTHS">16,16,16,16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PX_PATH_WIDTHS">16,16,16,16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_WIDTH">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DECIM_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_MULT_CNFG">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTS_PACKED">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETn">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CONFIG_CHANNEL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERP_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IPBUFF_MEMTYPE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">52</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_ARRANGEMENT">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">48</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_CHANNELS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_FILTS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MADDS">47</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_RELOAD_SLOTS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TAPS">47</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPBUFF_MEMTYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPT_MADDS">none</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OP_PATH_PSAMP_SRC">0,-2;1,-3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_PATH_WIDTHS">17,17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERSAMPLING_RATE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PX_PATH_SRC">2,3,2,3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RELOAD_TDATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYMMETRY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_FIFO">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_TUSER">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TUSER_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynquplus</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ZERO_PACKING_FACTOR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BestPrecision">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Blank_Output">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Channel_Sequence">Basic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Frequency">300.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientSource">Vector</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientVector">-62 0 194 0 -440 0 855 0 -1505 0 2478 0 -3900 0 5990 0 -9187 0 14632 0 -26536 0 83009 131071 83009 0 -26536 0 14632 0 -9187 0 5990 0 -3900 0 2478 0 -1505 0 855 0 -440 0 194 0 -62</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">hb47.coe</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Reload">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sets">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sign">Signed</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Structure">Inferred</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">47</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">hb47_2to1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_TUSER_Width">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Fractional_Bits">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Sign">Signed</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Width">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Decimation_Rate">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DisplayReloadOrder">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Architecture">Systolic_Multiply_Accumulate</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Selection">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Type">Decimation</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GUI_Behaviour">Coregen</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_Files">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_COE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Gen_MIF_from_Spec">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HardwareOversamplingRate">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Has_ARESETn">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inter_Column_Pipe_Length">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interpolation_Rate">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TREADY">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multi_Column_Support">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Num_Reload_Slots">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Channels">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Paths">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_List">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Selection">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Buffer_Type">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Rounding_Mode">Convergent_Rounding_to_Even</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">17</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Max">0.4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Min">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pattern_List">P4-0,P4-1,P4-2,P4-3,P4-4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Preference_For_Other_Storage">Automatic</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Quantization">Integer_Coefficients</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RateSpecification">Input_Sample_Period</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Rate_Change_Type">Integer</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reload_File">no_coe_file_loaded</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Data_Vector">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Method">Single</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_CONFIG_Sync_Mode">On_Vector</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_FIFO">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SamplePeriod">0.5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sample_Frequency">0.001</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Select_Pattern">All</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Max">1.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Stopband_Min">0.59</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Zero_Pack_Factor">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplusRFSOC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu28dr</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvg1517</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1_AR73068</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TKEEP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Channel_Sequence" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Frequency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CoefficientSource" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CoefficientVector" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_File" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sets" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Sign" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Structure" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coefficient_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ColumnConfig" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_Has_TLAST" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Fractional_Bits" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Decimation_Rate" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Architecture" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Selection" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Filter_Type" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Has_ARESETn" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interpolation_Rate" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TREADY" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M_DATA_Has_TUSER" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Channels" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Number_Paths" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Optimization_Goal" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Optimization_List" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Optimization_Selection" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Rounding_Mode" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Passband_Max" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Quantization" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RateSpecification" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Data_Vector" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_DATA_Has_FIFO" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S_DATA_Has_TUSER" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SamplePeriod" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Sample_Frequency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Select_Pattern" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Stopband_Max" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Stopband_Min" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc new file mode 100644 index 000000000..5d1d4b3a5 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc @@ -0,0 +1,46 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/, \ +x4xx_ps_rfdc_bd.tcl \ +) + +IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \ +capture_sysref.v \ +rf_nco_reset.vhd \ +rf_reset_controller.vhd \ +rf_reset.vhd \ +clock_gates.vhd \ +sync_wrapper.v \ +axis_mux.vhd \ +gpio_to_axis_mux.vhd \ +) \ +$(addprefix $(BASE_DIR)/../lib/control/, \ +synchronizer.v \ +synchronizer_impl.v \ +) \ +$(addprefix $(BASE_DIR)/x400/regmap/, PkgRFDC_REGS_REGMAP.vhd ) + +IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \ +x4xx_ps_rfdc_bd.tcl \ +) + +IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \ +x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.bd \ +) + +BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \ +x4xx_ps_rfdc_bd.bd.out \ +x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd_ooc.xdc \ +x4xx_ps_rfdc_bd/synth/x4xx_ps_rfdc_bd.v \ +) + +EMPTY_IP_SRCS = + +$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): $(IP_X4XX_PS_RFDC_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,x4xx_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS)) diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl new file mode 100644 index 000000000..65c3aa6ba --- /dev/null +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl @@ -0,0 +1,14 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +read_verilog -library work $script_dir/../../rf/common/capture_sysref.v +read_verilog -library work $script_dir/../../../../lib/control/synchronizer.v +read_verilog -library work $script_dir/../../../../lib/control/synchronizer_impl.v +read_verilog -library work $script_dir/../../rf/common/sync_wrapper.v +read_vhdl -library work $script_dir/../../rf/common/rf_nco_reset.vhd +read_vhdl -library work $script_dir/../../regmap/PkgRFDC_REGS_REGMAP.vhd +read_vhdl -library work $script_dir/../../rf/common/rf_reset_controller.vhd +read_vhdl -library work $script_dir/../../rf/common/rf_reset.vhd +read_vhdl -library work $script_dir/../../rf/common/clock_gates.vhd +read_vhdl -library work $script_dir/../../rf/common/axis_mux.vhd +read_vhdl -library work $script_dir/../../rf/common/gpio_to_axis_mux.vhd diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v new file mode 100644 index 000000000..454154382 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v @@ -0,0 +1,550 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: common_regs +// Description: +// Registers definition within the x4xx_ps_rfdc_bd IP. + +//XmlParse xml_on +//<top name="X4XX_FPGA"> +// <ports> +// <info> +// This section lists all common Processing System ports through +// which the register maps in this project are accessed. Each input +// port to the fabric will point to a regmap. +// </info> +// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP"> +// <info> +// This is the main AXI4-Lite master interface that the PS +// exposes to the kernel to interact with the FPGA fabric. +// There are multiple endpoints connected to this interface. +// </info> +// </port> +// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW"> +// <info> +// This is one of the two cache-coherent AXI slave ports available to +// communicate from the fabric (master) to the PS (slave). +// </info> +// </port> +// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW"> +// <info> +// This is one of the two cache-coherent AXI slave ports available to +// communicate from the fabric (master) to the PS (slave). +// </info> +// </port> +// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP"> +// <info> +// This is the SPI1 interface +// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>) +// of the PS. +// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br} +// The request format on SPI is defined as.{br} +// {b}Write request:{/b} +// {ul} +// {li}1'b1 = write +// {li}15 bit address +// {li}32 bit data (MOSI) +// {li}8 bit processing gap +// {li}5 bit padding +// {li}1 bit ack +// {li}2 bit status +// {/ul} +// {b}Read request:{/b} +// {ul} +// {li}1'b0 = read +// {li}15 bit address +// {li}8 bit processing gap +// {li}32 bit data (MISO) +// {li}5 bit padding +// {li}1 bit ack +// {li}2 bit status +// {/ul} +// </info> +// </port> +// </ports> +// <regmapcfg readablestrobes="false"> +// <map name="AXI_HPM0_REGMAP"/> +// <map name="MB_CPLD_PS_REGMAP"/> +// </regmapcfg> +//</top> +// +//<regmap name="AXI_HPM0_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true"> +// <info> +// This is the map for the register space that the Processing System's +// M_AXI_HPM0_FPD port (AXI4 master interface) has access to. +// This port has a 40-bit address bus. +// </info> +// <group name="COMMON"> +// <window name="RPU" offset="0x0080000000" size="0x00010000"> +// <info>Space reserved for RPU access</info> +// </window> +// <window name="JTAG_ENGINE" offset="0x1000000000" size="0x1000"> +// <info>Register space for the JTAG engine for MB CPLD programming.</info> +// </window> +// <window name="WR" offset="0x100003F000" size="0x1000"> +// <info>NOT IMPLEMENTED YET! Register space reserved for White Rabbit.</info> +// </window> +// <window name="MPM_ENDPOINT" offset="0x1000080000" size="0x20000" +// targetregmap="PL_CPLD_REGMAP"> +// <info>MPM endpoint fro MB/DB communication.</info> +// </window> +// <window name="CORE_REGS" offset="0x10000A0000" size="0x4000" +// targetregmap="CORE_REGS_REGMAP"> +// <info>Register space reserved for mboard-regs (Core).</info> +// </window> +// <window name="INT_ETH_DMA" offset="0x10000A4000" size="0x6000" +// targetregmap="ETH_DMA_CTRL_REGMAP"> +// <info>AXI DMA engine for internal Ethernet interface.</info> +// </window> +// <window name="INT_ETH_REGS" offset="0x10000AA000" size="0x2000"> +// <info>Misc. registers for internal Ethernet.</info> +// </window> +// <window name="RFDC" offset="0x1000100000" size="0x40000"> +// <info>Register space occupied by the Xilinx RFDC IP block.</info> +// </window> +// <window name="RFDC_REGS" offset="0x1000140000" size="0x20000" +// targetregmap="RFDC_REGS_REGMAP"> +// <info>Register space for RFDC control/status registers.</info> +// </window> +// </group> +//</regmap> +// +//<regmap name="ETH_DMA_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true"> +// <info> +// This is the map that the nixge driver uses in Ethernet DMA to +// move data between the Processing System's architecture and the fabric. +// This map is a combination of two main components: a Xilix AXI DMA engine +// and some registers for MAC/PHY control. +// </info> +// <group name="ETH_DMA_CTRL"> +// <window name="AXI_DMA_CTRL" offset="0x0" size="0x4000"> +// <info> +// Refer to Xilinx' AXI DMA v7.1 IP product guide for further +// information on this register map: +// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf +// </info> +// </window> +// <window name="ETH_IO_CTRL" offset="0x4000" size="0x2000"> +// <info>MAC/PHY control for the Ethernet interface.</info> +// </window> +// </group> +//</regmap> +//<regmap name="PL_DMA_MASTER_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true"> +// <info> +// This is a regmap to document the different ports that have access to the PS system memory. +// Each port may have different restrictions on system memory. See the corresponding window +// for details +// </info> +// <group name="HPC0_DMA"> +// <window name="AXI_HPC0_WINDOW" offset="0x0" size="0x10000000000"> +// <info> +// The HPC0 port of the PS is used for general purpose cache-coherent accesses +// to the PS system memory. Different applications may use it for different +// purposes. Its access is configured as follows: {br} +// {table border="1"} +// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr} +// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr} +// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr} +// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr} +// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr} +// {/table} +// </info> +// </window> +// </group> +// <group name="HPC1_DMA"> +// <window name="AXI_HPC1_WINDOW" offset="0x0" size="0x1000000000"> +// <info> +// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave +// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx. +// Its access is configured as follows: {br} +// {table border="1"} +// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr} +// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr} +// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr} +// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr} +// {/table} +// </info> +// </window> +// </group> +//</regmap> +// +//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true"> +// <group name="RFDC_REGS"> +// <info> +// These are the registers located within the RFDC block design +// that provide control and status support for the RF chain. +// </info> +// +// <window name="MMCM" offset="0x0" size="0x10000"> +// <info> +// Register space for controlling the data clock MMCM instance +// within the RFDC block design. +// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the +// regiter space description in chapter 2. +// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf) +// </info> +// </window> +// +// <register name="INVERT_IQ_REG" offset="0x10000" size="32"> +// <info>Control register for inverting I/Q data.</info> +// <!-- TODO: possibly redo these bitfields --> +// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/> +// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/> +// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/> +// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/> +// <bitfield name="INVERT_DB1_ADC0_IQ" range="4"/> +// <bitfield name="INVERT_DB1_ADC1_IQ" range="5"/> +// <bitfield name="INVERT_DB1_ADC2_IQ" range="6"/> +// <bitfield name="INVERT_DB1_ADC3_IQ" range="7"/> +// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/> +// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/> +// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/> +// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/> +// <bitfield name="INVERT_DB1_DAC0_IQ" range="12"/> +// <bitfield name="INVERT_DB1_DAC1_IQ" range="13"/> +// <bitfield name="INVERT_DB1_DAC2_IQ" range="14"/> +// <bitfield name="INVERT_DB1_DAC3_IQ" range="15"/> +// </register> +// +// <register name="MMCM_RESET_REG" offset="0x11000" size="32"> +// <info>Control register for resetting the data clock MMCM.</info> +// <bitfield name="RESET_MMCM" range="0"> +// <info> +// Write a '1' to this bit to reset the MMCM. Then write a +// '0' to place the MMCM out of reset. +// </info> +// </bitfield> +// </register> +// +// <register name="RF_RESET_CONTROL_REG" offset="0x12000" size="32"> +// <info> +// Control register for the RF reset controller. +// Verify the FSM ID before polling starting any reset sequence. +// To use the SW reset triggers: Wait until DB*_DONE is de-asserted. +// Assert either the *_RESET or *_ENABLE bitfields. +// Wait until DB*_DONE is asserted to release the trigger. +// The DB*_DONE signal should then de-assert.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// </info> +// <bitfield name="FSM_RESET" range="0"> +// <info> +// Write a '1' to this bit to reset the RF reset controller. +// Write a '0' once db0_fsm_reset_done asserts. +// </info> +// </bitfield> +// <bitfield name="ADC_RESET" range="4"> +// <info> +// Write a '1' to this bit to trigger a reset for the +// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done +// is asserted. +// </info> +// </bitfield> +// <bitfield name="ADC_ENABLE" range="5"> +// <info> +// Write a '1' to this bit to trigger the enable sequence for +// the daughterboard 0 ADC chain. Write a '0' once +// db0_adc_seq_done is asserted. +// </info> +// </bitfield> +// <bitfield name="DAC_RESET" range="8"> +// <info> +// Write a '1' to this bit to trigger a reset for the +// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done +// is asserted. +// </info> +// </bitfield> +// <bitfield name="DAC_ENABLE" range="9"> +// <info> +// Write a '1' to this bit to trigger the enable sequence for +// the daughterboard 0 DAC chain. Write a '0' once +// db0_dac_seq_done is asserted. +// </info> +// </bitfield> +// </register> +// +// <register name="RF_RESET_STATUS_REG" offset="0x12008" size="32" writable="false"> +// <info> +// Status register for the RF reset controller. +// Verify the FSM ID before polling starting any reset sequence. +// Refer to RF_RESET_CONTROL_REG for instructions on how to use +// the status bits in this register.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// </info> +// <bitfield name="FSM_RESET_DONE" range="3"> +// <info> +// This bit asserts ('1') when the DB0 RF reset controller FSM +// reset sequence is completed. The bitfield deasserts ('0') +// after deasserting db0_fsm_reset. +// </info> +// </bitfield> +// <bitfield name="ADC_SEQ_DONE" range="7"> +// <info> +// This bit asserts ('1') when the DB0 ADC chain reset sequence +// is completed. The bitfield deasserts ('0') after +// deasserting the issued triggered (enable or reset). +// </info> +// </bitfield> +// <bitfield name="DAC_SEQ_DONE" range="11"> +// <info> +// This bit asserts ('1') when the DB0 DAC chain reset sequence +// is completed. The bitfield deasserts ('0') after +// deasserting the issued triggered (enable or reset). +// </info> +// </bitfield> +// </register> +// +// <register name="RF_AXI_STATUS_REG" offset="0x13000" size="32" writable="false"> +// <info> +// Status register for the RF AXI-Stream interfaces.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// </info> +// <bitfield name="RFDC_DAC_TREADY" range="1..0"> +// <info> +// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_DAC_TVALID" range="3..2"> +// <info> +// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_Q_TREADY" range="5..4"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TReady handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_I_TREADY" range="7..6"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TReady handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_Q_TVALID" range="9..8"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TValid handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_I_TVALID" range="11..10"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TValid handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="USER_ADC_TVALID" range="13..12"> +// <info> +// This bitfield is wired to the user's ADC (DB0) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="USER_ADC_TREADY" range="15..14"> +// <info> +// This bitfield is wired to the user's ADC (DB0) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_DAC_TREADY_DB1" range="17..16"> +// <info> +// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_DAC_TVALID_DB1" range="19..18"> +// <info> +// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_Q_TREADY_DB1" range="21..20"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TReady handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_I_TREADY_DB1" range="23..22"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TReady handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_Q_TVALID_DB1" range="25..24"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TValid handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="RFDC_ADC_I_TVALID_DB1" range="27..26"> +// <info> +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TValid handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// </info> +// </bitfield> +// <bitfield name="USER_ADC_TVALID_DB1" range="29..28"> +// <info> +// This bitfield is wired to the user's ADC (DB1) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// <bitfield name="USER_ADC_TREADY_DB1" range="31..30"> +// <info> +// This bitfield is wired to the user's ADC (DB1) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// </info> +// </bitfield> +// </register> +// +// <register name="CALIBRATION_DATA" offset="0x014000"> +// <info> +// The fields of this register provide data to all the DAC channels when enabled +// by the CALIBRATION_ENABLE register. +// </info> +// <bitfield name="Q_DATA" range="31..16"> +// </bitfield> +// <bitfield name="I_DATA" range="15..00"> +// </bitfield> +// </register> +// +// <register name="CALIBRATION_ENABLE" offset="0x014008"> +// <info> +// This register enables calibration data in the DAC data path for each of the +// four channels. Each of these bits is normally '0'. When written '1', DAC data +// for the corresponding channel will be constantly driven with the contents of +// the CALIBRATION_DATA register. +// </info> +// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0"> +// <info> +// Enables calibration data for channel 0. +// </info> +// </bitfield> +// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1"> +// <info> +// Enables calibration data for channel 1. +// </info> +// </bitfield> +// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="4"> +// <info> +// Enables calibration data for channel 2. +// </info> +// </bitfield> +// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="5"> +// <info> +// Enables calibration data for channel 3. +// </info> +// </bitfield> +// </register> +// +// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true"> +// <info> +// Enable RF MMCM outputs. +// </info> +// <bitfield name="ENABLE_DATA_CLK" range="0"/> +// <bitfield name="ENABLE_DATA_CLK_2X" range="4"/> +// <bitfield name="ENABLE_RF_CLK" range="8"/> +// <bitfield name="ENABLE_RF_CLK_2X" range="12"/> +// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/> +// </register> +// +// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false"> +// <info> +// Data Clk Pll Status Register +// </info> +// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/> +// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/> +// </register> +// +// <register name="THRESHOLD_STATUS" offset="0x015000"> +// <info> +// This register shows threshold status for the ADCs. Each bit reflects the +// RFDC's real-time ADC status signals, which will assert when the ADC input +// signal exceeds the programmed threshold value. The status will remain +// asserted until cleared by software. +// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is +// the location of the tile in the converter column and ZZ is either 01 (the +// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). +// See also the Xilinx document PG269. +// </info> +// <bitfield name="ADC0_01_THRESHOLD1" range="0"> +// </bitfield> +// <bitfield name="ADC0_01_THRESHOLD2" range="1"> +// </bitfield> +// <bitfield name="ADC0_23_THRESHOLD1" range="2"> +// </bitfield> +// <bitfield name="ADC0_23_THRESHOLD2" range="3"> +// </bitfield> +// <bitfield name="ADC2_01_THRESHOLD1" range="8"> +// </bitfield> +// <bitfield name="ADC2_01_THRESHOLD2" range="9"> +// </bitfield> +// <bitfield name="ADC2_23_THRESHOLD1" range="10"> +// </bitfield> +// <bitfield name="ADC2_23_THRESHOLD2" range="11"> +// </bitfield> +// </register> +// +// <enumeratedtype name="FABRIC_DSP_BW_ENUM" showhex="true"> +// <value name="FABRIC_DSP_BW_NONE" integer="0"/> +// <value name="FABRIC_DSP_BW_100M" integer="100"/> +// <value name="FABRIC_DSP_BW_200M" integer="200"/> +// <value name="FABRIC_DSP_BW_400M" integer="400"/> +// </enumeratedtype> +// +// <register name="FABRIC_DSP_REG" offset="0x13008" size="32" writable="false"> +// <info> +// This register provides information to the driver on the type +// of DSP that is instantiated in the fabric.{BR/} +// The X410 platform supports multiple RF daughterboards, each requiring +// a different fabric RF DSP chain that works with specific RFDC settings. +// Each bandwidth DSP chain has a unique identifier (BW in MHz), this +// information is conveyed in this register to let the driver +// configure the RFDC with the proper settings. +// Also, channel count for the DSP module is included.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// </info> +// <bitfield name="FABRIC_DSP_BW" range="11..0" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE"> +// <info>Fabric DSP BW in MHz for daughterboard 0.</info> +// </bitfield> +// <bitfield name="FABRIC_DSP_RX_CNT" range="13..12" initialvalue="0"> +// <info>Fabric DSP RX channel count for daughterboard 0.</info> +// </bitfield> +// <bitfield name="FABRIC_DSP_TX_CNT" range="15..14" initialvalue="0"> +// <info>Fabric DSP TX channel count for daughterboard 0.</info> +// </bitfield> +// <bitfield name="FABRIC_DSP_BW_DB1" range="27..16" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE"> +// <info>Fabric DSP BW in MHz for daughterboard 1.</info> +// </bitfield> +// <bitfield name="FABRIC_DSP_RX_CNT_DB1" range="29..28" initialvalue="0"> +// <info>Fabric DSP RX channel count for daughterboard 0.</info> +// </bitfield> +// <bitfield name="FABRIC_DSP_TX_CNT_DB1" range="31..30" initialvalue="0"> +// <info>Fabric DSP TX channel count for daughterboard 0.</info> +// </bitfield> +// </register> +// +// </group> +//</regmap> +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v new file mode 100644 index 000000000..329393bfc --- /dev/null +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v @@ -0,0 +1,336 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: uhd_regs +// Description: +// Registers definition within the x4xx_ps_rfdc_bd IP. + +//XmlParse xml_on +//<regmap name="CMAC_REGMAP" markdown="true" generateverilog="false"> +// <group name="XILINX_CMAC_REGISTERS"> +// <info> +// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187. +// +// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf +// +// </info> +// </group> +//</regmap> + +//XmlParse xml_on +//<regmap name="XGE_MAC_REGMAP" markdown="true" generateverilog="false"> +// <group name="OPENCORE_XGE_REGISTERS"> +// <info> +// +// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf +// +// </info> +// </group> +//</regmap> + + +//<regmap name="DMA_REGMAP" markdown="true" generateverilog="false"> +// <group name="XILINX_DMA_REGISTERS"> +// <info> +// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11 +// +// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf +// +// </info> +// </group> +//</regmap> + +//<regmap name="NIXGE_REGMAP" markdown="true" generateverilog="false"> +// <group name="XGE_MAC_WINDOW"> +// <window name="XGE_MAC" offset="0x1000" size="0x1000" targetregmap="XGE_MAC_REGMAP"/> +// </group> +// <group name="XGE_MAC_REGS"> +// <info> +// nixge (maps to 10g mac if present) +// </info> +// <register name="PORT_INFO" offset="0x0000"> +// <bitfield name="COMPAT_NUM" range="31..24"> +// <info> +// Constant indicating version for this space. +// Not used by the NIXGE driver (12/4/2020) +// </info> +// </bitfield> +// <bitfield name="ACTIVITY" range="17"> +// <info> +// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL. +// </info> +// </bitfield> +// <bitfield name="LINK_UP" range="16"> +// <info> +// Generically means that a connection with a peer has been established. Specific +// meaning varies based on the MGT_PROTOCOL. +// </info> +// </bitfield> +// <bitfield name="MGT_PROTOCOL" range="15..8"> +// <info> +// Constant indicating what flavor of communication this port is using +// +// - 0 = NONE +// - 1 = 1GbE +// - 2 = 10GbE +// - 3 = Aurora +// - 4 = WhiteRabbit +// - 5 = 100GbE +// +// </info> +// </bitfield> +// <bitfield name="PORTNUM" range="7..0"> +// <info> +// Constant indicating which port this register is hooked to +// +// - 0 = QSFP0 +// - 1 = QSFP1 +// +// </info> +// </bitfield> +// </register> +// <register name="MAC_CTRL_STATUS" offset="0x0004"> +// <info> +// Definition of this register depends on Protocol +// +// **10GBE** +// +// *READ - Status* +// +// - 0 = status_crc_error +// - 1 = status_fragment_error +// - 2 = status_txdfifo_ovflow +// - 3 = status_txdfifo_udflow +// - 4 = status_rxdfifo_ovflow +// - 5 = status_rxdfifo_udflow +// - 6 = status_pause_frame_rx +// - 7 = status_local_fault +// - 8 = status_remote_fault +// +// *WRITE - Ctl* +// +// - 0 = ctrl_tx_enable +// +// **100 GBE** +// +// *READ - Status* +// +// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC +// (Stays set till MAC is reset). This is a fatal error +// - 1 = tx_unfout - Sets if TX underflow reported by CMAC +// (Stays set till MAC is reset). This is a fatal error +// - 2 = stat_rx_aligned - goes high when CMAC has finished +// alignment, and is ready to start reception of traffic. +// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID) +// but upstream is trying to hold(TREADY)off we drop a packet. +// Upstream circuitry should detect this when traffic is forked +// between CHDR and CPU, so this bit will only set if there is a +// HW design error. +// - 4 = auto_config_done - This bit goes high when the auto_config +// state machine finishes operation. It is very similiar to +// stat_rx_alligned, but waits for extra writes which occur +// after allignement to complete. +// - 24:16 = pause_mask - readable version of pause_mask bellow. +// +// *WRITE - Ctl* +// +// - 0 = auto_enable - Defaults to ON after reset - Enables a +// state machine that performs CMAC register writes to +// bring up the MAC without SW intervention. +// - 24:16 = pause_mask - A second layer of enables(the first being +// register in the CMAC) on the pause_request mechanic. Bits +// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause +// request (not priority controlled). The mask is used for TX +// and RX. +// </info> +// </register> +// <register name="MAC_PHY_STATUS" offset="0x0008"> +// <info> +// +// Definition of this register depends on Protocol +// +// **10GBE** +// +// *READ - Status * +// +// - 0 = core_status 0 - link_up +// - 1 = core_status 1 +// - 2 = core_status 2 +// - 3 = core_status 3 +// - 4 = core_status 4 +// - 5 = core_status 5 +// - 6 = core_status 6 +// - 7 = core_status 7 +// +// **100 GBE** +// +// *READ - Status* +// +// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets. +// - 1 = usr_rx_reset - RX PLL's have locked +// +// </info> +// </register> +// <register name="MAC_LED_CTL" offset="0x000C"> +// <bitfield name="identify_enable" range="0"> +// <info> +// When set identify_value is used to control the activity LED. +// When clear the activity LED set on any TX or RX traffic to the mgt +// </info> +// </bitfield> +// <bitfield name="identify_value" range="1"> +// <info> +// When identify_enable is set, this value controls the activity LED. +// </info> +// </bitfield> +// </register> +// <register name="ETH_MDIO_BASE" offset="0x0010"> +// <info> +// The x4xx family of products does not use MDIO. +// </info> +// </register> +// <register name="AURORA_OVERRUNS" offset="0x0020"> +// <info> +// Only valid if the protocol is Aurora. +// </info> +// </register> +// <register name="AURORA_CHECKSUM_ERRORS" offset="0x0024"> +// <info> +// Only valid if the protocol is Aurora. +// </info> +// </register> +// <register name="AURORA_BIST_CHECKER_SAMPS" offset="0x0028"> +// <info> +// Only valid if the protocol is Aurora. +// </info> +// </register> +// <register name="AURORA_BIST_CHECKER_ERRORS" offset="0x002C"> +// <info> +// Only valid if the protocol is Aurora. +// </info> +// </register> +// </group> +//</regmap> +// +//<regmap name="UIO_REGMAP" markdown="true" generateverilog="false"> +// <group name="UIO_REGS"> +// <info> +// UIO +// </info> +// <register name="IP" offset="0x0000"> +// <info> +// Set this port's IP address +// </info> +// </register> +// <register name="UDP" offset="0x0004"> +// <info> +// Set the UDP port for CHDR_traffic +// </info> +// </register> +// <register name="BRIDGE_MAC_LSB" offset="0x0010"> +// <info> +// If BRIDGE_ENABLE is set use this MAC_ID +// </info> +// </register> +// <register name="BRIDGE_MAC_MSB" offset="0x0014"> +// <info> +// If BRIDGE_ENABLE is set use this MAC_ID +// </info> +// </register> +// <register name="BRIDGE_IP" offset="0x0018"> +// <info> +// If BRIDGE_ENABLE is set use this IP Address +// </info> +// </register> +// <register name="BRIDGE_UDP" offset="0x001C"> +// <info> +// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic +// </info> +// </register> +// <register name="BRIDGE_ENABLE" offset="0x0020"> +// <info> +// Bit 0 Controls the following logic +// +//```verilog +// always_comb begin : bridge_mux +// my_mac = bridge_en ? bridge_mac_reg : mac_reg; +// my_ip = bridge_en ? bridge_ip_reg : ip_reg; +// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port; +// end +//``` +// +// </info> +// </register> +// <register name="CHDR_DROPPED" offset="0x0030"> +// <info> +// Count the number of Packets dropped that were addressed to the CHDR section. +// </info> +// </register> +// <register name="CPU_DROPPED" offset="0x0034"> +// <info> +// Count the number of Packets dropped that were addressed to us, but not to the CHDR section. +// </info> +// </register> +// <register name="PAUSE" offset="0x0038"> +// <bitfield name="pause_set" range="15..0"> +// <info> +// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only +// used with 100Gb ethernet +// </info> +// </bitfield> +// <bitfield name="pause_clear" range="31..16"> +// <info> +// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. +// *Pause clear must be less than pause set or terrible things will happen.* +// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only +// used with 100Gb ethernet +// </info> +// </bitfield> +// </register> +// </group> +//</regmap> + +//<regmap name="QSFP_REGMAP" markdown="true" generateverilog="false"> +// <group name="QSFP_WINDOWS"> +// <info> +// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations +// +// - 1X10GB Ethernet - Using OpenCore XGE MAC +// - 1x100GB Ethernet - Using Xilinx CMAC +// - (future possible) - Xilinx Aurora (various rates and lane widths) +// - (future possible) - 4X10GB Ethernet +// +// </info> +// <window name="ETH_DMA" offset="0x000" size="0x4000" targetregmap="DMA_REGMAP"/> +// <window name="NIXGE" offset="0x8000" size="0x2000" targetregmap="NIXGE_REGMAP"/> +// <window name="UIO" offset="0xA000" size="0x2000" targetregmap="UIO_REGMAP"/> +// <window name="CMAC" offset="0xC000" size="0x2000" targetregmap="CMAC_REGMAP"/> +// </group> +//</regmap> + + +//<regmap name="AXI_HPM0_REGMAP" markdown="true" generateverilog="false"> +// <group name="UHD_ONLY"> +// <info> +// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0 +// - 0_1 indicates QSFP0 - Lane1 +// - 0_2 indicates QSFP0 - Lane2 +// - 0_3 indicates QSFP0 - Lane3 +// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1 +// - 1_1 indicates QSFP1 - Lane1 +// - 1_2 indicates QSFP1 - Lane2 +// - 1_3 indicates QSFP1 - Lane3 +// </info> +// <window name="QSFP_0_0" offset="0x1200000000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_0_1" offset="0x1200010000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_0_2" offset="0x1200020000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_0_3" offset="0x1200030000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_1_0" offset="0x1200040000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_1_1" offset="0x1200050000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_1_2" offset="0x1200060000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// <window name="QSFP_1_3" offset="0x1200070000" size="0x10000" targetregmap="QSFP_REGMAP"/> +// </group> +//</regmap> +//XmlParse xml_off diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd new file mode 100644 index 000000000..2fac8ad64 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd @@ -0,0 +1,411 @@ +------------------------------------------------------------------------------------------ +-- +-- File: x4xx_ps_rfdc_bd.vhd +-- Author: niBlockDesign::niBdExportStub +-- Original Project: HwBuildTools +-- Date: 03 February 2021 +-- +------------------------------------------------------------------------------------------ +-- (c) Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------------------ +-- +-- Purpose: This is an automatically generated stub file to match the entity +-- declaration for 'x4xx_ps_rfdc_bd'. This file was created using niBdExportStub +-- Do not modify this file directly! +-- +------------------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library unisim; +use unisim.vcomponents.all; + +entity x4xx_ps_rfdc_bd is +port ( + adc_data_out_resetn_dclk : out STD_LOGIC; + adc_enable_data_rclk : out STD_LOGIC; + adc_reset_pulse_dclk : in STD_LOGIC; + adc_rfdc_axi_resetn_rclk : out STD_LOGIC; + bus_clk : in STD_LOGIC; + bus_rstn : in STD_LOGIC; + clk40 : in STD_LOGIC; + clk40_rstn : in STD_LOGIC; + dac_data_in_resetn_dclk : out STD_LOGIC; + dac_data_in_resetn_dclk2x : out STD_LOGIC; + dac_data_in_resetn_rclk : out STD_LOGIC; + dac_data_in_resetn_rclk2x : out STD_LOGIC; + dac_reset_pulse_dclk : in STD_LOGIC; + data_clk : out STD_LOGIC; + data_clk_2x : out STD_LOGIC; + data_clock_locked : out STD_LOGIC; + enable_gated_clocks_clk40 : in STD_LOGIC; + enable_sysref_rclk : in STD_LOGIC; + fir_resetn_rclk2x : out STD_LOGIC; + gated_base_clks_valid_clk40 : out STD_LOGIC; + invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + irq0_lpd_rpu_n : in STD_LOGIC; + irq1_lpd_rpu_n : in STD_LOGIC; + jtag0_tck : inout STD_LOGIC; + jtag0_tdi : inout STD_LOGIC; + jtag0_tdo : in STD_LOGIC; + jtag0_tms : inout STD_LOGIC; + nco_reset_done_dclk : out STD_LOGIC; + pl_clk40 : out STD_LOGIC; + pl_clk100 : out STD_LOGIC; + pl_clk166 : out STD_LOGIC; + pl_clk200 : out STD_LOGIC; + pl_ps_irq0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pl_ps_irq1 : in STD_LOGIC_VECTOR ( 5 downto 0 ); + pl_resetn0 : out STD_LOGIC; + pl_resetn1 : out STD_LOGIC; + pl_resetn2 : out STD_LOGIC; + pl_resetn3 : out STD_LOGIC; + pll_ref_clk_in : in STD_LOGIC; + pll_ref_clk_out : out STD_LOGIC; + rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 ); + rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 ); + rfdc_irq : out STD_LOGIC; + s_axi_hp0_aclk : in STD_LOGIC; + s_axi_hp1_aclk : in STD_LOGIC; + s_axi_hpc0_aclk : in STD_LOGIC; + start_nco_reset_dclk : in STD_LOGIC; + sysref_out_pclk : out STD_LOGIC; + sysref_out_rclk : out STD_LOGIC; + sysref_pl_in : in STD_LOGIC; + s_axi_hp0_aruser : in STD_LOGIC; + s_axi_hp0_awuser : in STD_LOGIC; + s_axi_hp0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_awlock : in STD_LOGIC; + s_axi_hp0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awvalid : in STD_LOGIC; + s_axi_hp0_awready : out STD_LOGIC; + s_axi_hp0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hp0_wlast : in STD_LOGIC; + s_axi_hp0_wvalid : in STD_LOGIC; + s_axi_hp0_wready : out STD_LOGIC; + s_axi_hp0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_bvalid : out STD_LOGIC; + s_axi_hp0_bready : in STD_LOGIC; + s_axi_hp0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_arlock : in STD_LOGIC; + s_axi_hp0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arvalid : in STD_LOGIC; + s_axi_hp0_arready : out STD_LOGIC; + s_axi_hp0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_rlast : out STD_LOGIC; + s_axi_hp0_rvalid : out STD_LOGIC; + s_axi_hp0_rready : in STD_LOGIC; + s_axi_hp0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_eth_dma_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_eth_dma_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_eth_dma_tlast : in STD_LOGIC; + s_axis_eth_dma_tready : out STD_LOGIC; + s_axis_eth_dma_tvalid : in STD_LOGIC; + s_axi_hp1_aruser : in STD_LOGIC; + s_axi_hp1_awuser : in STD_LOGIC; + s_axi_hp1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_awlock : in STD_LOGIC; + s_axi_hp1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_awvalid : in STD_LOGIC; + s_axi_hp1_awready : out STD_LOGIC; + s_axi_hp1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hp1_wlast : in STD_LOGIC; + s_axi_hp1_wvalid : in STD_LOGIC; + s_axi_hp1_wready : out STD_LOGIC; + s_axi_hp1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_bvalid : out STD_LOGIC; + s_axi_hp1_bready : in STD_LOGIC; + s_axi_hp1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_arlock : in STD_LOGIC; + s_axi_hp1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_arvalid : in STD_LOGIC; + s_axi_hp1_arready : out STD_LOGIC; + s_axi_hp1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_rlast : out STD_LOGIC; + s_axi_hp1_rvalid : out STD_LOGIC; + s_axi_hp1_rready : in STD_LOGIC; + s_axi_hp1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_aruser : in STD_LOGIC; + s_axi_hpc0_awuser : in STD_LOGIC; + s_axi_hpc0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_awlock : in STD_LOGIC; + s_axi_hpc0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_awvalid : in STD_LOGIC; + s_axi_hpc0_awready : out STD_LOGIC; + s_axi_hpc0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hpc0_wlast : in STD_LOGIC; + s_axi_hpc0_wvalid : in STD_LOGIC; + s_axi_hpc0_wready : out STD_LOGIC; + s_axi_hpc0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_bvalid : out STD_LOGIC; + s_axi_hpc0_bready : in STD_LOGIC; + s_axi_hpc0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_arlock : in STD_LOGIC; + s_axi_hpc0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_arvalid : in STD_LOGIC; + s_axi_hpc0_arready : out STD_LOGIC; + s_axi_hpc0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_rlast : out STD_LOGIC; + s_axi_hpc0_rvalid : out STD_LOGIC; + s_axi_hpc0_rready : in STD_LOGIC; + s_axi_hpc0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + adc0_clk_clk_n : in STD_LOGIC; + adc0_clk_clk_p : in STD_LOGIC; + adc2_clk_clk_n : in STD_LOGIC; + adc2_clk_clk_p : in STD_LOGIC; + m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_app_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_app_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_app_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_app_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_app_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_app_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_app_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + dac0_clk_clk_n : in STD_LOGIC; + dac0_clk_clk_p : in STD_LOGIC; + dac1_clk_clk_n : in STD_LOGIC; + dac1_clk_clk_p : in STD_LOGIC; + gpio_0_tri_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_0_tri_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); + gpio_0_tri_t : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_eth_internal_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_eth_internal_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_eth_internal_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_eth_internal_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_eth_internal_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_eth_internal_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_eth_internal_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_eth_dma_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_eth_dma_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_eth_dma_tlast : out STD_LOGIC; + m_axis_eth_dma_tready : in STD_LOGIC; + m_axis_eth_dma_tvalid : out STD_LOGIC; + m_axi_rpu_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_rpu_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rpu_awvalid : out STD_LOGIC; + m_axi_rpu_awready : in STD_LOGIC; + m_axi_rpu_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rpu_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_rpu_wvalid : out STD_LOGIC; + m_axi_rpu_wready : in STD_LOGIC; + m_axi_rpu_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rpu_bvalid : in STD_LOGIC; + m_axi_rpu_bready : out STD_LOGIC; + m_axi_rpu_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_rpu_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rpu_arvalid : out STD_LOGIC; + m_axi_rpu_arready : in STD_LOGIC; + m_axi_rpu_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rpu_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rpu_rvalid : in STD_LOGIC; + m_axi_rpu_rready : out STD_LOGIC; + m_axi_core_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_core_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_core_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_core_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_core_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_core_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_core_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_core_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_core_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_core_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_mpm_ep_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mpm_ep_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mpm_ep_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_mpm_ep_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mpm_ep_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_mpm_ep_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mpm_ep_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch0_dout_i_tready : in STD_LOGIC; + adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC; + adc_tile224_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch0_dout_q_tready : in STD_LOGIC; + adc_tile224_ch0_dout_q_tvalid : out STD_LOGIC; + adc_tile224_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch1_dout_i_tready : in STD_LOGIC; + adc_tile224_ch1_dout_i_tvalid : out STD_LOGIC; + adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch1_dout_q_tready : in STD_LOGIC; + adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC; + adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch0_dout_i_tready : in STD_LOGIC; + adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC; + adc_tile226_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch0_dout_q_tready : in STD_LOGIC; + adc_tile226_ch0_dout_q_tvalid : out STD_LOGIC; + adc_tile226_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch1_dout_i_tready : in STD_LOGIC; + adc_tile226_ch1_dout_i_tvalid : out STD_LOGIC; + adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch1_dout_q_tready : in STD_LOGIC; + adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC; + dac_tile228_ch0_vout_v_n : out STD_LOGIC; + dac_tile228_ch0_vout_v_p : out STD_LOGIC; + dac_tile228_ch1_vout_v_n : out STD_LOGIC; + dac_tile228_ch1_vout_v_p : out STD_LOGIC; + dac_tile229_ch0_vout_v_n : out STD_LOGIC; + dac_tile229_ch0_vout_v_p : out STD_LOGIC; + dac_tile229_ch1_vout_v_n : out STD_LOGIC; + dac_tile229_ch1_vout_v_p : out STD_LOGIC; + dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile228_ch0_din_tvalid : in STD_LOGIC; + dac_tile228_ch0_din_tready : out STD_LOGIC; + dac_tile228_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile228_ch1_din_tvalid : in STD_LOGIC; + dac_tile228_ch1_din_tready : out STD_LOGIC; + dac_tile229_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile229_ch0_din_tvalid : in STD_LOGIC; + dac_tile229_ch0_din_tready : out STD_LOGIC; + dac_tile229_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile229_ch1_din_tvalid : in STD_LOGIC; + dac_tile229_ch1_din_tready : out STD_LOGIC; + s_axi_hpc1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hpc1_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + sysref_rf_in_diff_n : in STD_LOGIC; + sysref_rf_in_diff_p : in STD_LOGIC; + adc_tile224_ch0_vin_v_n : in STD_LOGIC; + adc_tile224_ch0_vin_v_p : in STD_LOGIC; + adc_tile224_ch1_vin_v_n : in STD_LOGIC; + adc_tile224_ch1_vin_v_p : in STD_LOGIC; + adc_tile226_ch0_vin_v_n : in STD_LOGIC; + adc_tile226_ch0_vin_v_p : in STD_LOGIC; + adc_tile226_ch1_vin_v_n : in STD_LOGIC; + adc_tile226_ch1_vin_v_p : in STD_LOGIC; + s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end entity x4xx_ps_rfdc_bd; + +architecture stub of x4xx_ps_rfdc_bd is +begin +end architecture stub; diff --git a/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl new file mode 100644 index 000000000..23eedcb0e --- /dev/null +++ b/fpga/usrp3/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl @@ -0,0 +1,3681 @@ + +################################################################ +# This is a generated script based on design: x4xx_ps_rfdc_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source x4xx_ps_rfdc_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# capture_sysref, clock_gates, rf_nco_reset, rf_reset_controller, gpio_to_axis_mux + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name x4xx_ps_rfdc_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable <design_name> to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + + # Add USER_COMMENTS on $design_name + set_property USER_COMMENTS.comment_2 "reg_reset_mmcm: +[0] = mmcm_reset_n (default b0)" [get_bd_designs $design_name] + set_property USER_COMMENTS.comment_3 "reg_invert_iq: +[15:8] = invert DAC channels +[7:0] = invert ADC channels" [get_bd_designs $design_name] + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +ettus.com:ip:axi_bitq:1.0\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:usp_rf_data_converter:2.1\ +xilinx.com:ip:xlslice:1.0\ +xilinx.com:ip:axi_protocol_converter:2.1\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:util_ds_buf:2.1\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +capture_sysref\ +clock_gates\ +rf_nco_reset\ +rf_reset_controller\ +gpio_to_axis_mux\ +" + + set list_mods_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: rf_clock_buffers +proc create_hier_cell_rf_clock_buffers { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir O -from 0 -to 0 rfdc_clk + create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x + create_bd_pin -dir I -from 0 -to 0 rfdc_clk_2x_ce + create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_2x_pll + create_bd_pin -dir I -from 0 -to 0 rfdc_clk_ce + create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll + + # Create instance: rfdc_clk_1x_buf, and set properties + set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_1x_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {BUFGCE} \ + ] $rfdc_clk_1x_buf + + # Create instance: rfdc_clk_2x_buf, and set properties + set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_2x_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {BUFGCE} \ + ] $rfdc_clk_2x_buf + + # Create port connections + connect_bd_net -net BUFGCE_I2_1 [get_bd_pins rfdc_clk_2x_pll] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_I] + connect_bd_net -net rfdc_clk_1 [get_bd_pins rfdc_clk_pll] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_I] + connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rfdc_clk] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rfdc_clk_2x] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins rfdc_clk_2x_ce] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_CE] + connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins rfdc_clk_ce] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_CE] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: calibration_muxes +proc create_hier_cell_calibration_muxes { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_1_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_2_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_3_0 + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk_0 + create_bd_pin -dir I -type rst s_axi_config_aresetn + create_bd_pin -dir I -type clk s_axi_config_clk + + # Create instance: axi_gpio_data, and set properties + set axi_gpio_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_data ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_GPIO2_WIDTH {8} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_data + + # Create instance: gpio_to_axis_mux_0, and set properties + set block_name gpio_to_axis_mux + set block_cell_name gpio_to_axis_mux_0 + if { [catch {set gpio_to_axis_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $gpio_to_axis_mux_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + set_property -dict [ list \ + CONFIG.kGpioWidth {32} \ + ] $gpio_to_axis_mux_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axis_0_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axis_1_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_1] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_2_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_2] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins m_axis_3_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_3] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dac_tile228_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_0] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dac_tile228_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_1] + connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_2] + connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_3] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins S_AXI_1] [get_bd_intf_pins axi_gpio_data/S_AXI] + + # Create port connections + connect_bd_net -net Net [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_data/s_axi_aclk] + connect_bd_net -net Net1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_data/s_axi_aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_data/gpio_io_o] [get_bd_pins gpio_to_axis_mux_0/gpio] + connect_bd_net -net axi_gpio_data_gpio2_io_o [get_bd_pins axi_gpio_data/gpio2_io_o] [get_bd_pins gpio_to_axis_mux_0/mux_select] + connect_bd_net -net s_axi_aclk_0_1 [get_bd_pins s_axi_aclk_0] [get_bd_pins gpio_to_axis_mux_0/m_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_3_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_3_aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: ThresholdRegister +proc create_hier_cell_ThresholdRegister { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + + # Create pins + create_bd_pin -dir I -from 0 -to 0 In0 + create_bd_pin -dir I -from 0 -to 0 In1 + create_bd_pin -dir I -from 0 -to 0 In2 + create_bd_pin -dir I -from 0 -to 0 In3 + create_bd_pin -dir I -from 0 -to 0 In5 + create_bd_pin -dir I -from 0 -to 0 In6 + create_bd_pin -dir I -from 0 -to 0 In7 + create_bd_pin -dir I -from 0 -to 0 In8 + create_bd_pin -dir I -type rst s_axi_config_aresetn + create_bd_pin -dir I -type clk s_axi_config_clk + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + CONFIG.C_GPIO_WIDTH {12} \ + ] $axi_gpio_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_WIDTH {4} \ + ] $xlconstant_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] + + # Create port connections + connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net In2_1 [get_bd_pins In2] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net In3_1 [get_bd_pins In3] [get_bd_pins xlconcat_0/In3] + connect_bd_net -net In5_1 [get_bd_pins In5] [get_bd_pins xlconcat_0/In5] + connect_bd_net -net In6_1 [get_bd_pins In6] [get_bd_pins xlconcat_0/In6] + connect_bd_net -net In7_1 [get_bd_pins In7] [get_bd_pins xlconcat_0/In7] + connect_bd_net -net In8_1 [get_bd_pins In8] [get_bd_pins xlconcat_0/In8] + connect_bd_net -net s_axi_config_aresetn_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] + connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_gpio_0/gpio_io_i] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In4] [get_bd_pins xlconstant_0/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: eth_dma_internal +proc create_hier_cell_eth_dma_internal { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_to_ps + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_eth_dma + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth_dma_ctrl + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_eth_dma + + + # Create pins + create_bd_pin -dir I -type clk bus_clk + create_bd_pin -dir I -type rst bus_rstn + create_bd_pin -dir I -type clk clk40 + create_bd_pin -dir I -type rst clk40_rstn + create_bd_pin -dir O -from 1 -to 0 irq + + # Create instance: axi_eth_dma_internal, and set properties + set axi_eth_dma_internal [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_eth_dma_internal ] + set_property -dict [ list \ + CONFIG.c_addr_width {36} \ + CONFIG.c_enable_multi_channel {0} \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_m_axi_mm2s_data_width {128} \ + CONFIG.c_m_axi_s2mm_data_width {128} \ + CONFIG.c_m_axis_mm2s_tdata_width {64} \ + CONFIG.c_micro_dma {0} \ + CONFIG.c_mm2s_burst_size {16} \ + CONFIG.c_s2mm_burst_size {16} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + ] $axi_eth_dma_internal + + # Create instance: pl_ps_irq1_concat, and set properties + set pl_ps_irq1_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pl_ps_irq1_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {2} \ + ] $pl_ps_irq1_concat + + # Create instance: smartconnect_dma, and set properties + set smartconnect_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_dma ] + set_property -dict [ list \ + CONFIG.NUM_SI {3} \ + ] $smartconnect_dma + + # Create interface connections + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_eth_dma] [get_bd_intf_pins axi_eth_dma_internal/M_AXIS_MM2S] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axis_eth_dma] [get_bd_intf_pins axi_eth_dma_internal/S_AXIS_S2MM] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_MM2S [get_bd_intf_pins axi_eth_dma_internal/M_AXI_MM2S] [get_bd_intf_pins smartconnect_dma/S01_AXI] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_S2MM [get_bd_intf_pins axi_eth_dma_internal/M_AXI_S2MM] [get_bd_intf_pins smartconnect_dma/S02_AXI] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_SG [get_bd_intf_pins axi_eth_dma_internal/M_AXI_SG] [get_bd_intf_pins smartconnect_dma/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_eth_dma_ctrl [get_bd_intf_pins s_axi_eth_dma_ctrl] [get_bd_intf_pins axi_eth_dma_internal/S_AXI_LITE] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins m_axi_to_ps] [get_bd_intf_pins smartconnect_dma/M00_AXI] + + # Create port connections + connect_bd_net -net axi_eth_dma_internal_mm2s_introut [get_bd_pins axi_eth_dma_internal/mm2s_introut] [get_bd_pins pl_ps_irq1_concat/In0] + connect_bd_net -net axi_eth_dma_internal_s2mm_introut [get_bd_pins axi_eth_dma_internal/s2mm_introut] [get_bd_pins pl_ps_irq1_concat/In1] + connect_bd_net -net bus_rstn_1 [get_bd_pins bus_rstn] [get_bd_pins smartconnect_dma/aresetn] + connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_eth_dma_internal/s_axi_lite_aclk] + connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_eth_dma_internal/axi_resetn] + connect_bd_net -net m_axi_sg_aclk_0_1 [get_bd_pins bus_clk] [get_bd_pins axi_eth_dma_internal/m_axi_mm2s_aclk] [get_bd_pins axi_eth_dma_internal/m_axi_s2mm_aclk] [get_bd_pins axi_eth_dma_internal/m_axi_sg_aclk] [get_bd_pins smartconnect_dma/aclk] + connect_bd_net -net xlconcat_0_dout [get_bd_pins irq] [get_bd_pins pl_ps_irq1_concat/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_interconnect_common +proc create_hier_cell_axi_interconnect_common { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_app + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_core + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_dma_ctrl + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_jtag + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mpm_ep + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rf + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rpu + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_common + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_lpd + + + # Create pins + create_bd_pin -dir I -type clk clk40 + create_bd_pin -dir I -type rst clk40_rstn + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {7} \ + ] $axi_interconnect_0 + + # Create instance: axi_protocol_convert_0, and set properties + set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_jtag] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins m_axi_app] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins m_axi_rf] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins m_axi_mpm_ep] [get_bd_intf_pins axi_interconnect_0/M03_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins m_axi_core] [get_bd_intf_pins axi_interconnect_0/M04_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins m_axi_eth_dma_ctrl] [get_bd_intf_pins axi_interconnect_0/M05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins m_axi_eth_internal] [get_bd_intf_pins axi_interconnect_0/M06_AXI] + connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins m_axi_rpu] [get_bd_intf_pins axi_protocol_convert_0/M_AXI] + connect_bd_intf_net -intf_net inst_zynq_ps_M_AXI_HPM0_FPD [get_bd_intf_pins s_axi_common] [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net s_axi_lpd_1 [get_bd_intf_pins s_axi_lpd] [get_bd_intf_pins axi_protocol_convert_0/S_AXI] + + # Create port connections + connect_bd_net -net M01_ARESETN_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_protocol_convert_0/aresetn] + connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_protocol_convert_0/aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rfdc +proc create_hier_cell_rfdc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch0_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch1_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch0_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch1_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_config + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_rf_in + + + # Create pins + create_bd_pin -dir O adc_data_out_resetn_dclk + create_bd_pin -dir O adc_enable_data_rclk + create_bd_pin -dir I adc_reset_pulse_dclk + create_bd_pin -dir O adc_rfdc_axi_resetn_rclk + create_bd_pin -dir O dac_data_in_resetn_dclk + create_bd_pin -dir O dac_data_in_resetn_dclk2x + create_bd_pin -dir O dac_data_in_resetn_rclk + create_bd_pin -dir O dac_data_in_resetn_rclk2x + create_bd_pin -dir I dac_reset_pulse_dclk + create_bd_pin -dir O -type clk data_clk + create_bd_pin -dir O -type clk data_clk_2x + create_bd_pin -dir O data_clock_locked + create_bd_pin -dir I enable_gated_clocks_clk40 + create_bd_pin -dir I enable_sysref_rclk + create_bd_pin -dir O fir_resetn_rclk2x + create_bd_pin -dir O gated_base_clks_valid_clk40 + create_bd_pin -dir O -from 7 -to 0 invert_adc_iq_rclk2 + create_bd_pin -dir O -from 7 -to 0 invert_dac_iq_rclk2 + create_bd_pin -dir O nco_reset_done_dclk + create_bd_pin -dir I -type clk pll_ref_clk_in + create_bd_pin -dir O -type clk pll_ref_clk_out + create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk + create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk + create_bd_pin -dir O -from 0 -to 0 rfdc_clk + create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x + create_bd_pin -dir O -type intr rfdc_irq + create_bd_pin -dir I -type rst s_axi_config_aresetn + create_bd_pin -dir I -type clk s_axi_config_clk + create_bd_pin -dir I start_nco_reset_dclk + create_bd_pin -dir O sysref_out_pclk + create_bd_pin -dir O sysref_out_rclk + create_bd_pin -dir I sysref_pl_in + + # Create instance: ThresholdRegister + create_hier_cell_ThresholdRegister $hier_obj ThresholdRegister + + # Create instance: axi_interconnect_rf, and set properties + set axi_interconnect_rf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_rf ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {9} \ + CONFIG.STRATEGY {1} \ + ] $axi_interconnect_rf + + # Create instance: calibration_muxes + create_hier_cell_calibration_muxes $hier_obj calibration_muxes + + # Create instance: capture_sysref, and set properties + set block_name capture_sysref + set block_cell_name capture_sysref + if { [catch {set capture_sysref [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $capture_sysref eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + set_property -dict [ list \ + CONFIG.FREQ_HZ {61440000} \ + CONFIG.PHASE {0} \ + CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_pll_ref_clk_in} \ + ] [get_bd_pins /rfdc/capture_sysref/pll_ref_clk] + + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.PHASE {0} \ + CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_pll_ref_clk_in} \ + ] [get_bd_pins /rfdc/capture_sysref/rfdc_clk] + + # Create instance: clock_gates_0, and set properties + set block_name clock_gates + set block_cell_name clock_gates_0 + if { [catch {set clock_gates_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $clock_gates_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: const_1, and set properties + set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] + + # Create instance: data_clock_mmcm, and set properties + set data_clock_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 data_clock_mmcm ] + set_property -dict [ list \ + CONFIG.AXI_DRP {true} \ + CONFIG.CLKIN1_JITTER_PS {162.76} \ + CONFIG.CLKOUT1_DRIVES {Buffer} \ + CONFIG.CLKOUT1_JITTER {116.960} \ + CONFIG.CLKOUT1_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {61.44} \ + CONFIG.CLKOUT2_DRIVES {Buffer} \ + CONFIG.CLKOUT2_JITTER {104.559} \ + CONFIG.CLKOUT2_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {122.88} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_DRIVES {Buffer} \ + CONFIG.CLKOUT3_JITTER {98.017} \ + CONFIG.CLKOUT3_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {184.32} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_DRIVES {Buffer} \ + CONFIG.CLKOUT4_JITTER {93.671} \ + CONFIG.CLKOUT4_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {245.76} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT5_DRIVES {Buffer} \ + CONFIG.CLKOUT5_JITTER {87.938} \ + CONFIG.CLKOUT5_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {368.64} \ + CONFIG.CLKOUT5_USED {true} \ + CONFIG.CLKOUT6_DRIVES {Buffer} \ + CONFIG.CLKOUT7_DRIVES {Buffer} \ + CONFIG.CLK_OUT1_PORT {pll_ref_clk_out} \ + CONFIG.CLK_OUT2_PORT {data_clk} \ + CONFIG.CLK_OUT3_PORT {rfdc_clk} \ + CONFIG.CLK_OUT4_PORT {data_clk_2x} \ + CONFIG.CLK_OUT5_PORT {rfdc_clk_2x} \ + CONFIG.ENABLE_CLOCK_MONITOR {false} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {16.276} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {12} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {8} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {6} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {4} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {5} \ + CONFIG.PHASE_DUTY_CONFIG {false} \ + CONFIG.PRIMITIVE {MMCM} \ + CONFIG.PRIM_IN_FREQ {61.44} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \ + CONFIG.USE_CLKFB_STOPPED {false} \ + CONFIG.USE_DYN_RECONFIG {true} \ + CONFIG.USE_INCLK_STOPPED {false} \ + CONFIG.USE_LOCKED {true} \ + CONFIG.USE_PHASE_ALIGNMENT {true} \ + CONFIG.USE_POWER_DOWN {false} \ + CONFIG.USE_RESET {true} \ + CONFIG.USE_SAFE_CLOCK_STARTUP {false} \ + ] $data_clock_mmcm + + # Create instance: reg_clock_gate_control, and set properties + set reg_clock_gate_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_clock_gate_control ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_clock_gate_control + + # Create instance: reg_invert_iq, and set properties + set reg_invert_iq [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_invert_iq ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + ] $reg_invert_iq + + # Create instance: reg_reset_mmcm, and set properties + set reg_reset_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_reset_mmcm ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + ] $reg_reset_mmcm + + # Create instance: reg_rf_axi_status, and set properties + set reg_rf_axi_status [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_axi_status ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {0} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rf_axi_status + + # Create instance: reg_rf_reset_control, and set properties + set reg_rf_reset_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_reset_control ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rf_reset_control + + # Create instance: rf_clock_buffers + create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers + + # Create instance: rf_data_converter, and set properties + set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.1 rf_data_converter ] + set_property -dict [ list \ + CONFIG.ADC0_Enable {1} \ + CONFIG.ADC0_Fabric_Freq {184.320} \ + CONFIG.ADC0_Multi_Tile_Sync {true} \ + CONFIG.ADC0_Outclk_Freq {184.320} \ + CONFIG.ADC0_Refclk_Freq {2949.120} \ + CONFIG.ADC0_Sampling_Rate {2.94912} \ + CONFIG.ADC1_Enable {0} \ + CONFIG.ADC1_Fabric_Freq {0.0} \ + CONFIG.ADC1_Multi_Tile_Sync {false} \ + CONFIG.ADC1_Outclk_Freq {15.625} \ + CONFIG.ADC1_Refclk_Freq {2000.000} \ + CONFIG.ADC1_Sampling_Rate {2.0} \ + CONFIG.ADC224_En {true} \ + CONFIG.ADC225_En {false} \ + CONFIG.ADC2_Enable {1} \ + CONFIG.ADC2_Fabric_Freq {184.320} \ + CONFIG.ADC2_Multi_Tile_Sync {true} \ + CONFIG.ADC2_Outclk_Freq {184.320} \ + CONFIG.ADC2_Refclk_Freq {2949.120} \ + CONFIG.ADC2_Sampling_Rate {2.94912} \ + CONFIG.ADC_Data_Type00 {1} \ + CONFIG.ADC_Data_Type01 {1} \ + CONFIG.ADC_Data_Type02 {1} \ + CONFIG.ADC_Data_Type03 {1} \ + CONFIG.ADC_Data_Type10 {0} \ + CONFIG.ADC_Data_Type11 {0} \ + CONFIG.ADC_Data_Type12 {0} \ + CONFIG.ADC_Data_Type13 {0} \ + CONFIG.ADC_Data_Type20 {1} \ + CONFIG.ADC_Data_Type21 {1} \ + CONFIG.ADC_Data_Type22 {1} \ + CONFIG.ADC_Data_Type23 {1} \ + CONFIG.ADC_Data_Width00 {8} \ + CONFIG.ADC_Data_Width01 {8} \ + CONFIG.ADC_Data_Width02 {8} \ + CONFIG.ADC_Data_Width03 {8} \ + CONFIG.ADC_Data_Width10 {8} \ + CONFIG.ADC_Data_Width11 {8} \ + CONFIG.ADC_Data_Width12 {8} \ + CONFIG.ADC_Data_Width13 {8} \ + CONFIG.ADC_Data_Width20 {8} \ + CONFIG.ADC_Data_Width21 {8} \ + CONFIG.ADC_Data_Width22 {8} \ + CONFIG.ADC_Data_Width23 {8} \ + CONFIG.ADC_Debug {false} \ + CONFIG.ADC_Decimation_Mode00 {2} \ + CONFIG.ADC_Decimation_Mode01 {2} \ + CONFIG.ADC_Decimation_Mode02 {2} \ + CONFIG.ADC_Decimation_Mode03 {2} \ + CONFIG.ADC_Decimation_Mode10 {0} \ + CONFIG.ADC_Decimation_Mode11 {0} \ + CONFIG.ADC_Decimation_Mode12 {0} \ + CONFIG.ADC_Decimation_Mode13 {0} \ + CONFIG.ADC_Decimation_Mode20 {2} \ + CONFIG.ADC_Decimation_Mode21 {2} \ + CONFIG.ADC_Decimation_Mode22 {2} \ + CONFIG.ADC_Decimation_Mode23 {2} \ + CONFIG.ADC_Dither00 {false} \ + CONFIG.ADC_Dither01 {false} \ + CONFIG.ADC_Dither02 {false} \ + CONFIG.ADC_Dither03 {false} \ + CONFIG.ADC_Dither10 {true} \ + CONFIG.ADC_Dither11 {true} \ + CONFIG.ADC_Dither12 {true} \ + CONFIG.ADC_Dither13 {true} \ + CONFIG.ADC_Dither20 {false} \ + CONFIG.ADC_Dither21 {false} \ + CONFIG.ADC_Dither22 {false} \ + CONFIG.ADC_Dither23 {false} \ + CONFIG.ADC_Mixer_Mode00 {0} \ + CONFIG.ADC_Mixer_Mode01 {0} \ + CONFIG.ADC_Mixer_Mode02 {0} \ + CONFIG.ADC_Mixer_Mode03 {0} \ + CONFIG.ADC_Mixer_Mode10 {2} \ + CONFIG.ADC_Mixer_Mode11 {2} \ + CONFIG.ADC_Mixer_Mode12 {2} \ + CONFIG.ADC_Mixer_Mode13 {2} \ + CONFIG.ADC_Mixer_Mode20 {0} \ + CONFIG.ADC_Mixer_Mode21 {0} \ + CONFIG.ADC_Mixer_Mode22 {0} \ + CONFIG.ADC_Mixer_Mode23 {0} \ + CONFIG.ADC_Mixer_Type00 {2} \ + CONFIG.ADC_Mixer_Type01 {2} \ + CONFIG.ADC_Mixer_Type02 {2} \ + CONFIG.ADC_Mixer_Type03 {2} \ + CONFIG.ADC_Mixer_Type10 {3} \ + CONFIG.ADC_Mixer_Type11 {3} \ + CONFIG.ADC_Mixer_Type12 {3} \ + CONFIG.ADC_Mixer_Type13 {3} \ + CONFIG.ADC_Mixer_Type20 {2} \ + CONFIG.ADC_Mixer_Type21 {2} \ + CONFIG.ADC_Mixer_Type22 {2} \ + CONFIG.ADC_Mixer_Type23 {2} \ + CONFIG.ADC_NCO_Freq00 {0.200} \ + CONFIG.ADC_NCO_Freq01 {0.200} \ + CONFIG.ADC_NCO_Freq02 {0.200} \ + CONFIG.ADC_NCO_Freq03 {0.200} \ + CONFIG.ADC_NCO_Freq10 {0.0} \ + CONFIG.ADC_NCO_Freq11 {0.0} \ + CONFIG.ADC_NCO_Freq12 {0.0} \ + CONFIG.ADC_NCO_Freq13 {0.0} \ + CONFIG.ADC_NCO_Freq20 {0.200} \ + CONFIG.ADC_NCO_Freq21 {0.200} \ + CONFIG.ADC_NCO_Freq22 {0.200} \ + CONFIG.ADC_NCO_Freq23 {0.200} \ + CONFIG.ADC_NCO_Freq30 {0.0} \ + CONFIG.ADC_NCO_Freq31 {0.0} \ + CONFIG.ADC_NCO_RTS {true} \ + CONFIG.ADC_RTS {true} \ + CONFIG.ADC_Slice00_Enable {true} \ + CONFIG.ADC_Slice01_Enable {true} \ + CONFIG.ADC_Slice02_Enable {true} \ + CONFIG.ADC_Slice03_Enable {true} \ + CONFIG.ADC_Slice10_Enable {false} \ + CONFIG.ADC_Slice11_Enable {false} \ + CONFIG.ADC_Slice12_Enable {false} \ + CONFIG.ADC_Slice13_Enable {false} \ + CONFIG.ADC_Slice20_Enable {true} \ + CONFIG.ADC_Slice21_Enable {true} \ + CONFIG.ADC_Slice22_Enable {true} \ + CONFIG.ADC_Slice23_Enable {true} \ + CONFIG.Axiclk_Freq {40} \ + CONFIG.Calibration_Freeze {true} \ + CONFIG.Converter_Setup {1} \ + CONFIG.DAC0_Band {0} \ + CONFIG.DAC0_Enable {1} \ + CONFIG.DAC0_Fabric_Freq {184.320} \ + CONFIG.DAC0_Multi_Tile_Sync {true} \ + CONFIG.DAC0_Outclk_Freq {184.320} \ + CONFIG.DAC0_Refclk_Freq {2949.120} \ + CONFIG.DAC0_Sampling_Rate {2.94912} \ + CONFIG.DAC1_Enable {1} \ + CONFIG.DAC1_Fabric_Freq {184.320} \ + CONFIG.DAC1_Multi_Tile_Sync {true} \ + CONFIG.DAC1_Outclk_Freq {184.320} \ + CONFIG.DAC1_Refclk_Freq {2949.120} \ + CONFIG.DAC1_Sampling_Rate {2.94912} \ + CONFIG.DAC228_En {true} \ + CONFIG.DAC_Data_Type00 {0} \ + CONFIG.DAC_Data_Type01 {0} \ + CONFIG.DAC_Data_Width00 {16} \ + CONFIG.DAC_Data_Width01 {16} \ + CONFIG.DAC_Data_Width02 {16} \ + CONFIG.DAC_Data_Width03 {16} \ + CONFIG.DAC_Data_Width10 {16} \ + CONFIG.DAC_Data_Width11 {16} \ + CONFIG.DAC_Debug {false} \ + CONFIG.DAC_Interpolation_Mode00 {2} \ + CONFIG.DAC_Interpolation_Mode01 {2} \ + CONFIG.DAC_Interpolation_Mode02 {0} \ + CONFIG.DAC_Interpolation_Mode03 {0} \ + CONFIG.DAC_Interpolation_Mode10 {2} \ + CONFIG.DAC_Interpolation_Mode11 {2} \ + CONFIG.DAC_Invsinc_Ctrl00 {false} \ + CONFIG.DAC_Mixer_Mode00 {0} \ + CONFIG.DAC_Mixer_Mode01 {0} \ + CONFIG.DAC_Mixer_Mode02 {2} \ + CONFIG.DAC_Mixer_Mode03 {2} \ + CONFIG.DAC_Mixer_Mode10 {0} \ + CONFIG.DAC_Mixer_Mode11 {0} \ + CONFIG.DAC_Mixer_Mode13 {2} \ + CONFIG.DAC_Mixer_Mode20 {2} \ + CONFIG.DAC_Mixer_Mode21 {2} \ + CONFIG.DAC_Mixer_Mode30 {2} \ + CONFIG.DAC_Mixer_Mode31 {2} \ + CONFIG.DAC_Mixer_Type00 {2} \ + CONFIG.DAC_Mixer_Type01 {2} \ + CONFIG.DAC_Mixer_Type02 {3} \ + CONFIG.DAC_Mixer_Type03 {3} \ + CONFIG.DAC_Mixer_Type10 {2} \ + CONFIG.DAC_Mixer_Type11 {2} \ + CONFIG.DAC_NCO_Freq00 {0.200} \ + CONFIG.DAC_NCO_Freq01 {0.200} \ + CONFIG.DAC_NCO_Freq10 {0.200} \ + CONFIG.DAC_NCO_Freq11 {0.200} \ + CONFIG.DAC_NCO_RTS {true} \ + CONFIG.DAC_Output_Current {1} \ + CONFIG.DAC_RTS {false} \ + CONFIG.DAC_Slice00_Enable {true} \ + CONFIG.DAC_Slice01_Enable {true} \ + CONFIG.DAC_Slice02_Enable {false} \ + CONFIG.DAC_Slice03_Enable {false} \ + CONFIG.DAC_Slice10_Enable {true} \ + CONFIG.DAC_Slice11_Enable {true} \ + CONFIG.mADC_Data_Type00 {0} \ + CONFIG.mADC_Data_Type01 {0} \ + CONFIG.mADC_Data_Type02 {0} \ + CONFIG.mADC_Data_Type03 {0} \ + CONFIG.mADC_Data_Width00 {8} \ + CONFIG.mADC_Data_Width01 {8} \ + CONFIG.mADC_Data_Width02 {8} \ + CONFIG.mADC_Data_Width03 {8} \ + CONFIG.mADC_Decimation_Mode00 {0} \ + CONFIG.mADC_Decimation_Mode01 {0} \ + CONFIG.mADC_Decimation_Mode02 {0} \ + CONFIG.mADC_Decimation_Mode03 {0} \ + CONFIG.mADC_Dither00 {true} \ + CONFIG.mADC_Dither01 {true} \ + CONFIG.mADC_Dither02 {true} \ + CONFIG.mADC_Dither03 {true} \ + CONFIG.mADC_Enable {0} \ + CONFIG.mADC_Fabric_Freq {0.0} \ + CONFIG.mADC_Mixer_Mode00 {2} \ + CONFIG.mADC_Mixer_Mode01 {2} \ + CONFIG.mADC_Mixer_Mode02 {2} \ + CONFIG.mADC_Mixer_Mode03 {2} \ + CONFIG.mADC_Mixer_Type00 {3} \ + CONFIG.mADC_Mixer_Type01 {3} \ + CONFIG.mADC_Mixer_Type02 {3} \ + CONFIG.mADC_Mixer_Type03 {3} \ + CONFIG.mADC_Multi_Tile_Sync {false} \ + CONFIG.mADC_NCO_Freq02 {0.0} \ + CONFIG.mADC_NCO_Freq03 {0.0} \ + CONFIG.mADC_Outclk_Freq {15.625} \ + CONFIG.mADC_Refclk_Freq {2000.000} \ + CONFIG.mADC_Sampling_Rate {2.0} \ + CONFIG.mADC_Slice00_Enable {false} \ + CONFIG.mADC_Slice01_Enable {false} \ + CONFIG.mADC_Slice02_Enable {false} \ + CONFIG.mADC_Slice03_Enable {false} \ + CONFIG.mDAC_Band {0} \ + CONFIG.mDAC_Data_Type00 {0} \ + CONFIG.mDAC_Data_Type01 {0} \ + CONFIG.mDAC_Data_Width00 {2} \ + CONFIG.mDAC_Data_Width01 {2} \ + CONFIG.mDAC_Data_Width02 {16} \ + CONFIG.mDAC_Data_Width03 {16} \ + CONFIG.mDAC_Enable {1} \ + CONFIG.mDAC_Fabric_Freq {368.640} \ + CONFIG.mDAC_Interpolation_Mode00 {8} \ + CONFIG.mDAC_Interpolation_Mode01 {8} \ + CONFIG.mDAC_Interpolation_Mode02 {0} \ + CONFIG.mDAC_Interpolation_Mode03 {0} \ + CONFIG.mDAC_Invsinc_Ctrl00 {false} \ + CONFIG.mDAC_Mixer_Mode00 {0} \ + CONFIG.mDAC_Mixer_Mode01 {0} \ + CONFIG.mDAC_Mixer_Mode02 {2} \ + CONFIG.mDAC_Mixer_Mode03 {2} \ + CONFIG.mDAC_Mixer_Type00 {2} \ + CONFIG.mDAC_Mixer_Type01 {2} \ + CONFIG.mDAC_Mixer_Type02 {3} \ + CONFIG.mDAC_Mixer_Type03 {3} \ + CONFIG.mDAC_Multi_Tile_Sync {false} \ + CONFIG.mDAC_NCO_Freq01 {0} \ + CONFIG.mDAC_Outclk_Freq {184.320} \ + CONFIG.mDAC_Refclk_Freq {2949.120} \ + CONFIG.mDAC_Sampling_Rate {2.94912} \ + CONFIG.mDAC_Slice00_Enable {true} \ + CONFIG.mDAC_Slice01_Enable {true} \ + CONFIG.mDAC_Slice02_Enable {false} \ + CONFIG.mDAC_Slice03_Enable {false} \ + ] $rf_data_converter + + # Create instance: rf_nco_reset_0, and set properties + set block_name rf_nco_reset + set block_cell_name rf_nco_reset_0 + if { [catch {set rf_nco_reset_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $rf_nco_reset_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: rf_reset_controller_0, and set properties + set block_name rf_reset_controller + set block_cell_name rf_reset_controller_0 + if { [catch {set rf_reset_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $rf_reset_controller_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: slice_15_8, and set properties + set slice_15_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_15_8 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {15} \ + CONFIG.DIN_TO {8} \ + CONFIG.DOUT_WIDTH {8} \ + ] $slice_15_8 + + # Create instance: slice_7_0, and set properties + set slice_7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_7_0 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DOUT_WIDTH {8} \ + ] $slice_7_0 + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_pins axi_interconnect_rf/M06_AXI] [get_bd_intf_pins calibration_muxes/S_AXI_1] + connect_bd_intf_net -intf_net adc0_clk_0_1 [get_bd_intf_pins adc0_clk] [get_bd_intf_pins rf_data_converter/adc0_clk] + connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_pins adc2_clk] [get_bd_intf_pins rf_data_converter/adc2_clk] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_rf/M00_AXI] [get_bd_intf_pins rf_data_converter/s_axi] + connect_bd_intf_net -intf_net axi_interconnect_rf_M01_AXI [get_bd_intf_pins axi_interconnect_rf/M01_AXI] [get_bd_intf_pins data_clock_mmcm/s_axi_lite] + connect_bd_intf_net -intf_net axi_interconnect_rf_M02_AXI [get_bd_intf_pins axi_interconnect_rf/M02_AXI] [get_bd_intf_pins reg_invert_iq/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M03_AXI [get_bd_intf_pins axi_interconnect_rf/M03_AXI] [get_bd_intf_pins reg_reset_mmcm/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M04_AXI [get_bd_intf_pins axi_interconnect_rf/M04_AXI] [get_bd_intf_pins reg_rf_reset_control/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M05_AXI [get_bd_intf_pins axi_interconnect_rf/M05_AXI] [get_bd_intf_pins reg_rf_axi_status/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M07_AXI [get_bd_intf_pins axi_interconnect_rf/M07_AXI] [get_bd_intf_pins reg_clock_gate_control/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M08_AXI [get_bd_intf_pins ThresholdRegister/S_AXI] [get_bd_intf_pins axi_interconnect_rf/M08_AXI] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_0_0 [get_bd_intf_pins calibration_muxes/m_axis_0_0] [get_bd_intf_pins rf_data_converter/s00_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_1_0 [get_bd_intf_pins calibration_muxes/m_axis_1_0] [get_bd_intf_pins rf_data_converter/s01_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_2_0 [get_bd_intf_pins calibration_muxes/m_axis_2_0] [get_bd_intf_pins rf_data_converter/s10_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_3_0 [get_bd_intf_pins calibration_muxes/m_axis_3_0] [get_bd_intf_pins rf_data_converter/s11_axis] + connect_bd_intf_net -intf_net dac0_clk_0_1 [get_bd_intf_pins dac0_clk] [get_bd_intf_pins rf_data_converter/dac0_clk] + connect_bd_intf_net -intf_net dac1_clk_0_1 [get_bd_intf_pins dac1_clk] [get_bd_intf_pins rf_data_converter/dac1_clk] + connect_bd_intf_net -intf_net dac_tile228_ch0_din_1 [get_bd_intf_pins dac_tile228_ch0_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch0_din] + connect_bd_intf_net -intf_net dac_tile228_ch1_din_1 [get_bd_intf_pins dac_tile228_ch1_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch1_din] + connect_bd_intf_net -intf_net dac_tile229_ch0_din_1 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch0_din] + connect_bd_intf_net -intf_net dac_tile229_ch1_din_1 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch1_din] + connect_bd_intf_net -intf_net rf_data_converter_m00_axis [get_bd_intf_pins adc_tile224_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m00_axis] + connect_bd_intf_net -intf_net rf_data_converter_m01_axis [get_bd_intf_pins adc_tile224_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m01_axis] + connect_bd_intf_net -intf_net rf_data_converter_m02_axis [get_bd_intf_pins adc_tile224_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m02_axis] + connect_bd_intf_net -intf_net rf_data_converter_m03_axis [get_bd_intf_pins adc_tile224_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m03_axis] + connect_bd_intf_net -intf_net rf_data_converter_m20_axis [get_bd_intf_pins adc_tile226_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m20_axis] + connect_bd_intf_net -intf_net rf_data_converter_m21_axis [get_bd_intf_pins adc_tile226_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m21_axis] + connect_bd_intf_net -intf_net rf_data_converter_m22_axis [get_bd_intf_pins adc_tile226_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m22_axis] + connect_bd_intf_net -intf_net rf_data_converter_m23_axis [get_bd_intf_pins adc_tile226_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m23_axis] + connect_bd_intf_net -intf_net rf_data_converter_vout00 [get_bd_intf_pins dac_tile228_ch0_vout] [get_bd_intf_pins rf_data_converter/vout00] + connect_bd_intf_net -intf_net rf_data_converter_vout01 [get_bd_intf_pins dac_tile228_ch1_vout] [get_bd_intf_pins rf_data_converter/vout01] + connect_bd_intf_net -intf_net rf_data_converter_vout10 [get_bd_intf_pins dac_tile229_ch0_vout] [get_bd_intf_pins rf_data_converter/vout10] + connect_bd_intf_net -intf_net rf_data_converter_vout11 [get_bd_intf_pins dac_tile229_ch1_vout] [get_bd_intf_pins rf_data_converter/vout11] + connect_bd_intf_net -intf_net s_axi_config_1 [get_bd_intf_pins s_axi_config] [get_bd_intf_pins axi_interconnect_rf/S00_AXI] + connect_bd_intf_net -intf_net sysref_in_0_1 [get_bd_intf_pins sysref_rf_in] [get_bd_intf_pins rf_data_converter/sysref_in] + connect_bd_intf_net -intf_net vin0_01_0_1 [get_bd_intf_pins adc_tile224_ch0_vin] [get_bd_intf_pins rf_data_converter/vin0_01] + connect_bd_intf_net -intf_net vin0_23_0_1 [get_bd_intf_pins adc_tile224_ch1_vin] [get_bd_intf_pins rf_data_converter/vin0_23] + connect_bd_intf_net -intf_net vin2_01_0_1 [get_bd_intf_pins adc_tile226_ch0_vin] [get_bd_intf_pins rf_data_converter/vin2_01] + connect_bd_intf_net -intf_net vin2_23_0_1 [get_bd_intf_pins adc_tile226_ch1_vin] [get_bd_intf_pins rf_data_converter/vin2_23] + + # Create port connections + connect_bd_net -net M02_ARESETN_1 [get_bd_pins axi_interconnect_rf/M02_ARESETN] [get_bd_pins const_1/dout] [get_bd_pins reg_invert_iq/s_axi_aresetn] + connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_pins adc_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dAdcResetPulse] + connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_rclk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] + connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk] [get_bd_pins rf_nco_reset_0/dSysref] + connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1] + connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i] + connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid] + connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked] + connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_ce] + connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins rf_clock_buffers/rfdc_clk_ce] + connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dDacResetPulse] + connect_bd_net -net data_clk_2x_pll [get_bd_pins clock_gates_0/DataClk2xPll] [get_bd_pins data_clock_mmcm/data_clk_2x] + connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins clock_gates_0/DataClk1x] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/DataClk] + connect_bd_net -net data_clock_mmcm_data_clk1 [get_bd_pins clock_gates_0/DataClk1xPll] [get_bd_pins data_clock_mmcm/data_clk] + connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins clock_gates_0/DataClk2x] [get_bd_pins rf_reset_controller_0/DataClk2x] + connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked] + connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] + connect_bd_net -net data_clock_mmcm_rfdc_clk1 [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk_pll] + connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins reg_invert_iq/s_axi_aclk] [get_bd_pins rf_clock_buffers/rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] + connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_pll] + connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] + connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks] + connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk] + connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i] + connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i] + connect_bd_net -net reg_reset_mmcm_gpio_io_o [get_bd_pins axi_interconnect_rf/M01_ARESETN] [get_bd_pins clock_gates_0/rPllReset_n] [get_bd_pins data_clock_mmcm/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/gpio_io_o] + connect_bd_net -net reg_rf_reset_control1_gpio_io_o [get_bd_pins clock_gates_0/rSoftwareControl] [get_bd_pins reg_clock_gate_control/gpio_io_o] + connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl] + connect_bd_net -net rf_data_converter_adc0_01_over_threshold1 [get_bd_pins ThresholdRegister/In0] [get_bd_pins rf_data_converter/adc0_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc0_01_over_threshold2 [get_bd_pins ThresholdRegister/In1] [get_bd_pins rf_data_converter/adc0_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc0_23_over_threshold1 [get_bd_pins ThresholdRegister/In2] [get_bd_pins rf_data_converter/adc0_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc0_23_over_threshold2 [get_bd_pins ThresholdRegister/In3] [get_bd_pins rf_data_converter/adc0_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc0_nco_update_busy [get_bd_pins rf_data_converter/adc0_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc0xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_adc2_01_over_threshold1 [get_bd_pins ThresholdRegister/In5] [get_bd_pins rf_data_converter/adc2_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc2_01_over_threshold2 [get_bd_pins ThresholdRegister/In6] [get_bd_pins rf_data_converter/adc2_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc2_23_over_threshold1 [get_bd_pins ThresholdRegister/In7] [get_bd_pins rf_data_converter/adc2_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc2_23_over_threshold2 [get_bd_pins ThresholdRegister/In8] [get_bd_pins rf_data_converter/adc2_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc2_nco_update_busy [get_bd_pins rf_data_converter/adc2_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc2xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_dac0_nco_update_busy [get_bd_pins rf_data_converter/dac0_nco_update_busy] [get_bd_pins rf_nco_reset_0/cDac0xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_dac1_nco_update_busy [get_bd_pins rf_data_converter/dac1_nco_update_busy] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_irq [get_bd_pins rfdc_irq] [get_bd_pins rf_data_converter/irq] + connect_bd_net -net rf_nco_reset_0_cAdc0xNcoUpdateReq [get_bd_pins rf_data_converter/adc0_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc0xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cAdc2xNcoUpdateReq [get_bd_pins rf_data_converter/adc2_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc2xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cDac0xNcoUpdateReq [get_bd_pins rf_data_converter/dac0_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac0xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cDac0xSysrefIntGating [get_bd_pins rf_data_converter/dac0_sysref_int_gating] [get_bd_pins rf_nco_reset_0/cDac0xSysrefIntGating] + connect_bd_net -net rf_nco_reset_0_cDac0xSysrefIntReenable [get_bd_pins rf_data_converter/dac0_sysref_int_reenable] [get_bd_pins rf_nco_reset_0/cDac0xSysrefIntReenable] + connect_bd_net -net rf_nco_reset_0_cDac1xNcoUpdateReq [get_bd_pins rf_data_converter/dac1_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cNcoPhaseRst [get_bd_pins rf_data_converter/adc0_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc0_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_23_nco_phase_rst] [get_bd_pins rf_data_converter/dac00_nco_phase_rst] [get_bd_pins rf_data_converter/dac01_nco_phase_rst] [get_bd_pins rf_data_converter/dac10_nco_phase_rst] [get_bd_pins rf_data_converter/dac11_nco_phase_rst] [get_bd_pins rf_nco_reset_0/cNcoPhaseRst] + connect_bd_net -net rf_nco_reset_0_cNcoUpdateEn [get_bd_pins rf_data_converter/adc0_01_nco_update_en] [get_bd_pins rf_data_converter/adc0_23_nco_update_en] [get_bd_pins rf_data_converter/adc2_01_nco_update_en] [get_bd_pins rf_data_converter/adc2_23_nco_update_en] [get_bd_pins rf_data_converter/dac00_nco_update_en] [get_bd_pins rf_data_converter/dac01_nco_update_en] [get_bd_pins rf_data_converter/dac10_nco_update_en] [get_bd_pins rf_data_converter/dac11_nco_update_en] [get_bd_pins rf_nco_reset_0/cNcoUpdateEn] + connect_bd_net -net rf_nco_reset_0_dNcoResetDone [get_bd_pins nco_reset_done_dclk] [get_bd_pins rf_nco_reset_0/dNcoResetDone] + connect_bd_net -net rf_reset_controller_0_cSoftwareStatus [get_bd_pins reg_rf_reset_control/gpio2_io_i] [get_bd_pins rf_reset_controller_0/cSoftwareStatus] + connect_bd_net -net rf_reset_controller_0_d2DacFirReset_n [get_bd_pins dac_data_in_resetn_dclk2x] [get_bd_pins rf_reset_controller_0/d2DacFirReset_n] + connect_bd_net -net rf_reset_controller_0_dAdcDataOutReset_n [get_bd_pins adc_data_out_resetn_dclk] [get_bd_pins rf_reset_controller_0/dAdcDataOutReset_n] + connect_bd_net -net rf_reset_controller_0_dDacDataInReset_n [get_bd_pins dac_data_in_resetn_dclk] [get_bd_pins rf_reset_controller_0/dDacDataInReset_n] + connect_bd_net -net rf_reset_controller_0_r2AdcFirReset_n [get_bd_pins fir_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2AdcFirReset_n] + connect_bd_net -net rf_reset_controller_0_r2DacFirReset_n [get_bd_pins dac_data_in_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2DacFirReset_n] + connect_bd_net -net rf_reset_controller_0_rAdcEnableData [get_bd_pins adc_enable_data_rclk] [get_bd_pins rf_reset_controller_0/rAdcEnableData] + connect_bd_net -net rf_reset_controller_0_rAdcGearboxReset_n [get_bd_pins adc_rfdc_axi_resetn_rclk] [get_bd_pins rf_reset_controller_0/rAdcGearboxReset_n] + connect_bd_net -net rf_reset_controller_0_rAdcRfdcAxiReset_n [get_bd_pins rf_data_converter/m0_axis_aresetn] [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_reset_controller_0/rAdcRfdcAxiReset_n] + connect_bd_net -net rf_reset_controller_0_rDacGearboxReset_n [get_bd_pins dac_data_in_resetn_rclk] [get_bd_pins rf_reset_controller_0/rDacGearboxReset_n] + connect_bd_net -net rf_reset_controller_0_rDacRfdcAxiReset_n [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacRfdcAxiReset_n] + connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq/gpio_io_o] [get_bd_pins slice_15_8/Din] [get_bd_pins slice_7_0/Din] + connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn] + connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] + connect_bd_net -net start_nco_reset_rclk_1 [get_bd_pins start_nco_reset_dclk] [get_bd_pins rf_nco_reset_0/dStartNcoReset] + connect_bd_net -net sysref_in_0_2 [get_bd_pins sysref_pl_in] [get_bd_pins capture_sysref/sysref_in] + connect_bd_net -net xlslice_0_Dout [get_bd_pins invert_adc_iq_rclk2] [get_bd_pins slice_7_0/Dout] + connect_bd_net -net xlslice_1_Dout [get_bd_pins invert_dac_iq_rclk2] [get_bd_pins slice_15_8/Dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: ps +proc create_hier_cell_ps { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ps() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_app + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_core + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mpm_ep + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rf + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rpu + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_eth_dma + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hpc0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hpc1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_eth_dma + + + # Create pins + create_bd_pin -dir I -type clk bus_clk + create_bd_pin -dir I -type rst bus_rstn + create_bd_pin -dir I -type clk clk40 + create_bd_pin -dir I -type rst clk40_rstn + create_bd_pin -dir I irq0_lpd_rpu_n + create_bd_pin -dir I irq1_lpd_rpu_n + create_bd_pin -dir IO jtag0_tck + create_bd_pin -dir IO jtag0_tdi + create_bd_pin -dir I jtag0_tdo + create_bd_pin -dir IO jtag0_tms + create_bd_pin -dir O -type clk pl_clk40 + create_bd_pin -dir O -type clk pl_clk100 + create_bd_pin -dir O -type clk pl_clk166 + create_bd_pin -dir O -type clk pl_clk200 + create_bd_pin -dir I -from 7 -to 0 -type intr pl_ps_irq0 + create_bd_pin -dir I -from 5 -to 0 pl_ps_irq1_1 + create_bd_pin -dir O -type rst pl_resetn0 + create_bd_pin -dir O -type rst pl_resetn1 + create_bd_pin -dir O -type rst pl_resetn2 + create_bd_pin -dir O -type rst pl_resetn3 + create_bd_pin -dir I -type clk s_axi_hp0_aclk + create_bd_pin -dir I -type clk s_axi_hp1_aclk + create_bd_pin -dir I -type clk s_axi_hpc0_aclk + + # Create instance: axi_interconnect_common + create_hier_cell_axi_interconnect_common $hier_obj axi_interconnect_common + + # Create instance: cpld_jtag_engine, and set properties + set cpld_jtag_engine [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 cpld_jtag_engine ] + + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \ + ] [get_bd_pins /ps/cpld_jtag_engine/S_AXI_ACLK] + + # Create instance: eth_dma_internal + create_hier_cell_eth_dma_internal $hier_obj eth_dma_internal + + # Create instance: hpc1_axi_interconnect, and set properties + set hpc1_axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 hpc1_axi_interconnect ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $hpc1_axi_interconnect + + # Create instance: inst_zynq_ps, and set properties + set inst_zynq_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 inst_zynq_ps ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {inout} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {slow} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {disable} \ + CONFIG.PSU_MIO_10_SLEW {slow} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {disable} \ + CONFIG.PSU_MIO_11_SLEW {slow} \ + CONFIG.PSU_MIO_12_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {slow} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {slow} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {slow} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {slow} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {slow} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {slow} \ + CONFIG.PSU_MIO_18_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {slow} \ + CONFIG.PSU_MIO_19_DIRECTION {inout} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {slow} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {slow} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {slow} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {slow} \ + CONFIG.PSU_MIO_22_DIRECTION {out} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {slow} \ + CONFIG.PSU_MIO_23_DIRECTION {out} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {slow} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {slow} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {slow} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {slow} \ + CONFIG.PSU_MIO_27_DIRECTION {inout} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {slow} \ + CONFIG.PSU_MIO_28_DIRECTION {inout} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {slow} \ + CONFIG.PSU_MIO_29_DIRECTION {inout} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {slow} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {out} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {slow} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {slow} \ + CONFIG.PSU_MIO_33_DIRECTION {in} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {slow} \ + CONFIG.PSU_MIO_36_DIRECTION {inout} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {slow} \ + CONFIG.PSU_MIO_37_DIRECTION {inout} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {slow} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {slow} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {slow} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {slow} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {slow} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {slow} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {slow} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {slow} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pulldown} \ + CONFIG.PSU_MIO_44_SLEW {slow} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {slow} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {slow} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {slow} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {slow} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {slow} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {slow} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {slow} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {slow} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {slow} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {slow} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {slow} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {slow} \ + CONFIG.PSU_MIO_5_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {slow} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {slow} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {slow} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {slow} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {slow} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {slow} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {slow} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {slow} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {slow} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {slow} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {slow} \ + CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pulldown} \ + CONFIG.PSU_MIO_6_SLEW {slow} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {slow} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {slow} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {slow} \ + CONFIG.PSU_MIO_8_DIRECTION {out} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {slow} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {slow} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART 1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1199.988037} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {320} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {64} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {266.664001} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {39.999599} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {10} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {40} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {166.664993} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {9} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {166.6667} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {48} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333000} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {0} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {16} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {Components} \ + CONFIG.PSU__DDRC__CWL {12} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {1} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {High (95 Max)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {32} \ + CONFIG.PSU__DDRC__T_RC {45.32} \ + CONFIG.PSU__DDRC__T_RCD {16} \ + CONFIG.PSU__DDRC__T_RP {16} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__FPGA_PL3_ENABLE {1} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {32} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {32} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 2 .. 3} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 36 .. 37} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {4} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__ECRC_CHECK {0} \ + CONFIG.PSU__PCIE__ECRC_ERR {0} \ + CONFIG.PSU__PCIE__ECRC_GEN {0} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PL_CLK3_BUF {TRUE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {0} \ + CONFIG.PSU__PMU__GPO1__ENABLE {0} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {high} \ + CONFIG.PSU__PMU__GPO4__ENABLE {0} \ + CONFIG.PSU__PMU__GPO5__ENABLE {0} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {0} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {<Select>} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {<Select>} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {<Select>} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {0} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ + CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD0__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE {1} \ + CONFIG.PSU__SD0__GRP_POW__IO {MIO 23} \ + CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 22} \ + CONFIG.PSU__SD0__RESET__ENABLE {1} \ + CONFIG.PSU__SD0__SLOT_TYPE {eMMC} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {8Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {<Select>} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {<Select>} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS1__IO {MIO 8} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS2__IO {MIO 7} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 30 .. 31} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 32 .. 33} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__RESET__ENABLE {0} \ + CONFIG.PSU__USB1_COHERENCY {0} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB1__RESET__ENABLE {0} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ + CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {1} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {1} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__S_AXI_GP1 {1} \ + CONFIG.PSU__USE__S_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP3 {1} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $inst_zynq_ps + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {1} \ + ] $xlconstant_1 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_core] [get_bd_intf_pins axi_interconnect_common/m_axi_core] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins s_axi_hpc0] [get_bd_intf_pins inst_zynq_ps/S_AXI_HPC0_FPD] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_eth_dma] [get_bd_intf_pins eth_dma_internal/m_axis_eth_dma] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axis_eth_dma] [get_bd_intf_pins eth_dma_internal/s_axis_eth_dma] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins m_axi_eth_internal] [get_bd_intf_pins axi_interconnect_common/m_axi_eth_internal] + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins eth_dma_internal/m_axi_to_ps] [get_bd_intf_pins hpc1_axi_interconnect/S00_AXI] + connect_bd_intf_net -intf_net S_AXI_HPC1_FPD_0_1 [get_bd_intf_pins s_axi_hpc1] [get_bd_intf_pins hpc1_axi_interconnect/S01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins hpc1_axi_interconnect/M00_AXI] [get_bd_intf_pins inst_zynq_ps/S_AXI_HPC1_FPD] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_pins m_axi_rf] [get_bd_intf_pins axi_interconnect_common/m_axi_rf] + connect_bd_intf_net -intf_net axi_interconnect_common_M01_AXI [get_bd_intf_pins axi_interconnect_common/m_axi_jtag] [get_bd_intf_pins cpld_jtag_engine/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_eth_dma_ctrl [get_bd_intf_pins axi_interconnect_common/m_axi_eth_dma_ctrl] [get_bd_intf_pins eth_dma_internal/s_axi_eth_dma_ctrl] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_mpm_ep [get_bd_intf_pins m_axi_mpm_ep] [get_bd_intf_pins axi_interconnect_common/m_axi_mpm_ep] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_rpu [get_bd_intf_pins m_axi_rpu] [get_bd_intf_pins axi_interconnect_common/m_axi_rpu] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_uhd [get_bd_intf_pins m_axi_app] [get_bd_intf_pins axi_interconnect_common/m_axi_app] + connect_bd_intf_net -intf_net inst_zynq_ps_GPIO_0 [get_bd_intf_pins gpio_0] [get_bd_intf_pins inst_zynq_ps/GPIO_0] + connect_bd_intf_net -intf_net inst_zynq_ps_M_AXI_HPM0_FPD [get_bd_intf_pins axi_interconnect_common/s_axi_common] [get_bd_intf_pins inst_zynq_ps/M_AXI_HPM0_FPD] + connect_bd_intf_net -intf_net inst_zynq_ps_M_AXI_HPM0_LPD [get_bd_intf_pins axi_interconnect_common/s_axi_lpd] [get_bd_intf_pins inst_zynq_ps/M_AXI_HPM0_LPD] + connect_bd_intf_net -intf_net s_axi_hp0_1 [get_bd_intf_pins s_axi_hp0] [get_bd_intf_pins inst_zynq_ps/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net s_axi_hp1_1 [get_bd_intf_pins s_axi_hp1] [get_bd_intf_pins inst_zynq_ps/S_AXI_HP1_FPD] + + # Create port connections + connect_bd_net -net Net [get_bd_pins jtag0_tck] [get_bd_pins cpld_jtag_engine/bit_clk] + connect_bd_net -net Net1 [get_bd_pins jtag0_tdi] [get_bd_pins cpld_jtag_engine/bit_out] + connect_bd_net -net Net2 [get_bd_pins jtag0_tms] [get_bd_pins cpld_jtag_engine/bit_stb] + connect_bd_net -net bus_rstn_1 [get_bd_pins bus_rstn] [get_bd_pins eth_dma_internal/bus_rstn] [get_bd_pins hpc1_axi_interconnect/ARESETN] [get_bd_pins hpc1_axi_interconnect/M00_ARESETN] [get_bd_pins hpc1_axi_interconnect/S00_ARESETN] [get_bd_pins hpc1_axi_interconnect/S01_ARESETN] + connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_interconnect_common/clk40] [get_bd_pins cpld_jtag_engine/S_AXI_ACLK] [get_bd_pins eth_dma_internal/clk40] [get_bd_pins inst_zynq_ps/maxihpm0_fpd_aclk] [get_bd_pins inst_zynq_ps/maxihpm0_lpd_aclk] + connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_interconnect_common/clk40_rstn] [get_bd_pins cpld_jtag_engine/S_AXI_ARESETN] [get_bd_pins eth_dma_internal/clk40_rstn] + connect_bd_net -net eth_dma_internal_irq [get_bd_pins eth_dma_internal/irq] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net inst_zynq_ps_pl_clk0 [get_bd_pins pl_clk100] [get_bd_pins inst_zynq_ps/pl_clk0] + connect_bd_net -net inst_zynq_ps_pl_clk1 [get_bd_pins pl_clk40] [get_bd_pins inst_zynq_ps/pl_clk1] + connect_bd_net -net inst_zynq_ps_pl_clk2 [get_bd_pins pl_clk166] [get_bd_pins inst_zynq_ps/pl_clk2] + connect_bd_net -net inst_zynq_ps_pl_clk3 [get_bd_pins pl_clk200] [get_bd_pins inst_zynq_ps/pl_clk3] + connect_bd_net -net inst_zynq_ps_pl_resetn0 [get_bd_pins pl_resetn0] [get_bd_pins inst_zynq_ps/pl_resetn0] + connect_bd_net -net inst_zynq_ps_pl_resetn1 [get_bd_pins pl_resetn1] [get_bd_pins inst_zynq_ps/pl_resetn1] + connect_bd_net -net inst_zynq_ps_pl_resetn2 [get_bd_pins pl_resetn2] [get_bd_pins inst_zynq_ps/pl_resetn2] + connect_bd_net -net inst_zynq_ps_pl_resetn3 [get_bd_pins pl_resetn3] [get_bd_pins inst_zynq_ps/pl_resetn3] + connect_bd_net -net jtag0_tdo_1 [get_bd_pins jtag0_tdo] [get_bd_pins cpld_jtag_engine/bit_in] + connect_bd_net -net m_axi_sg_aclk_0_1 [get_bd_pins bus_clk] [get_bd_pins eth_dma_internal/bus_clk] [get_bd_pins hpc1_axi_interconnect/ACLK] [get_bd_pins hpc1_axi_interconnect/M00_ACLK] [get_bd_pins hpc1_axi_interconnect/S00_ACLK] [get_bd_pins hpc1_axi_interconnect/S01_ACLK] [get_bd_pins inst_zynq_ps/saxihpc1_fpd_aclk] + connect_bd_net -net nirq0_lpd_rpu_0_1 [get_bd_pins irq0_lpd_rpu_n] [get_bd_pins inst_zynq_ps/nirq0_lpd_rpu] + connect_bd_net -net nirq1_lpd_rpu_0_1 [get_bd_pins irq1_lpd_rpu_n] [get_bd_pins inst_zynq_ps/nirq1_lpd_rpu] + connect_bd_net -net pl_ps_irq0_1 [get_bd_pins pl_ps_irq0] [get_bd_pins inst_zynq_ps/pl_ps_irq0] + connect_bd_net -net pl_ps_irq1_1_1 [get_bd_pins pl_ps_irq1_1] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net s_axi_hp0_aclk_1 [get_bd_pins s_axi_hp0_aclk] [get_bd_pins inst_zynq_ps/saxihp0_fpd_aclk] + connect_bd_net -net s_axi_hp1_aclk_1 [get_bd_pins s_axi_hp1_aclk] [get_bd_pins inst_zynq_ps/saxihp1_fpd_aclk] + connect_bd_net -net saxihpc0_fpd_aclk_0_1 [get_bd_pins s_axi_hpc0_aclk] [get_bd_pins inst_zynq_ps/saxihpc0_fpd_aclk] + connect_bd_net -net xlconcat_0_dout [get_bd_pins inst_zynq_ps/pl_ps_irq1] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins inst_zynq_ps/nfiq0_lpd_rpu] [get_bd_pins inst_zynq_ps/nfiq1_lpd_rpu] [get_bd_pins xlconstant_1/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] + + set adc2_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk ] + + set adc_tile224_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile224_ch0_dout_i + + set adc_tile224_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile224_ch0_dout_q + + set adc_tile224_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin ] + + set adc_tile224_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile224_ch1_dout_i + + set adc_tile224_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile224_ch1_dout_q + + set adc_tile224_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin ] + + set adc_tile226_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile226_ch0_dout_i + + set adc_tile226_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile226_ch0_dout_q + + set adc_tile226_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin ] + + set adc_tile226_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile226_ch1_dout_i + + set adc_tile226_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + ] $adc_tile226_ch1_dout_q + + set adc_tile226_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin ] + + set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] + + set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] + + set dac_tile228_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile228_ch0_din + + set dac_tile228_ch0_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch0_vout ] + + set dac_tile228_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile228_ch1_din + + set dac_tile228_ch1_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch1_vout ] + + set dac_tile229_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile229_ch0_din + + set dac_tile229_ch0_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch0_vout ] + + set dac_tile229_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile229_ch1_din + + set dac_tile229_ch1_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch1_vout ] + + set gpio_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_0 ] + + set m_axi_app [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_app ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_app + + set m_axi_core [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_core ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_core + + set m_axi_eth_internal [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_eth_internal + + set m_axi_mpm_ep [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mpm_ep ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_mpm_ep + + set m_axi_rpu [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rpu ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {40} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_rpu + + set m_axis_eth_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_eth_dma ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + ] $m_axis_eth_dma + + set s_axi_hp0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {1} \ + CONFIG.AWUSER_WIDTH {1} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp0 + + set s_axi_hp1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {1} \ + CONFIG.AWUSER_WIDTH {1} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp1 + + set s_axi_hpc0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hpc0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {1} \ + CONFIG.AWUSER_WIDTH {1} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hpc0 + + set s_axi_hpc1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hpc1 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {49} \ + CONFIG.ARUSER_WIDTH {1} \ + CONFIG.AWUSER_WIDTH {1} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {5} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {16} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {16} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hpc1 + + set s_axis_eth_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_eth_dma ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {200000000} \ + CONFIG.HAS_TKEEP {1} \ + CONFIG.HAS_TLAST {1} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $s_axis_eth_dma + + set sysref_rf_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_rf_in ] + + + # Create ports + set adc_data_out_resetn_dclk [ create_bd_port -dir O adc_data_out_resetn_dclk ] + set adc_enable_data_rclk [ create_bd_port -dir O adc_enable_data_rclk ] + set adc_reset_pulse_dclk [ create_bd_port -dir I -type rst adc_reset_pulse_dclk ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $adc_reset_pulse_dclk + set adc_rfdc_axi_resetn_rclk [ create_bd_port -dir O adc_rfdc_axi_resetn_rclk ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axis_eth_dma:s_axis_eth_dma:s_axi_hpc1} \ + CONFIG.ASSOCIATED_RESET {bus_rstn} \ + CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_app:m_axi_mpm_ep:m_axi_core:m_axi_rpu:m_axi_eth_internal} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + set dac_data_in_resetn_dclk [ create_bd_port -dir O dac_data_in_resetn_dclk ] + set dac_data_in_resetn_dclk2x [ create_bd_port -dir O dac_data_in_resetn_dclk2x ] + set dac_data_in_resetn_rclk [ create_bd_port -dir O dac_data_in_resetn_rclk ] + set dac_data_in_resetn_rclk2x [ create_bd_port -dir O dac_data_in_resetn_rclk2x ] + set dac_reset_pulse_dclk [ create_bd_port -dir I -type rst dac_reset_pulse_dclk ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $dac_reset_pulse_dclk + set data_clk [ create_bd_port -dir O -type clk data_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {122880000} \ + ] $data_clk + set data_clk_2x [ create_bd_port -dir O -type clk data_clk_2x ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {245760000} \ + ] $data_clk_2x + set data_clock_locked [ create_bd_port -dir O data_clock_locked ] + set enable_gated_clocks_clk40 [ create_bd_port -dir I enable_gated_clocks_clk40 ] + set enable_sysref_rclk [ create_bd_port -dir I enable_sysref_rclk ] + set fir_resetn_rclk2x [ create_bd_port -dir O fir_resetn_rclk2x ] + set gated_base_clks_valid_clk40 [ create_bd_port -dir O gated_base_clks_valid_clk40 ] + set invert_adc_iq_rclk2 [ create_bd_port -dir O -from 7 -to 0 invert_adc_iq_rclk2 ] + set invert_dac_iq_rclk2 [ create_bd_port -dir O -from 7 -to 0 invert_dac_iq_rclk2 ] + set irq0_lpd_rpu_n [ create_bd_port -dir I irq0_lpd_rpu_n ] + set irq1_lpd_rpu_n [ create_bd_port -dir I irq1_lpd_rpu_n ] + set jtag0_tck [ create_bd_port -dir IO jtag0_tck ] + set jtag0_tdi [ create_bd_port -dir IO jtag0_tdi ] + set jtag0_tdo [ create_bd_port -dir I jtag0_tdo ] + set jtag0_tms [ create_bd_port -dir IO jtag0_tms ] + set nco_reset_done_dclk [ create_bd_port -dir O nco_reset_done_dclk ] + set pl_clk40 [ create_bd_port -dir O -type clk pl_clk40 ] + set pl_clk100 [ create_bd_port -dir O -type clk pl_clk100 ] + set pl_clk166 [ create_bd_port -dir O -type clk pl_clk166 ] + set pl_clk200 [ create_bd_port -dir O -type clk pl_clk200 ] + set pl_ps_irq0 [ create_bd_port -dir I -from 7 -to 0 -type intr pl_ps_irq0 ] + set_property -dict [ list \ + CONFIG.PortWidth {8} \ + CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $pl_ps_irq0 + set pl_ps_irq1 [ create_bd_port -dir I -from 5 -to 0 -type intr pl_ps_irq1 ] + set_property -dict [ list \ + CONFIG.PortWidth {6} \ + CONFIG.SENSITIVITY {LEVEL_HIGH:LEVEL_HIGH} \ + ] $pl_ps_irq1 + set pl_resetn0 [ create_bd_port -dir O -type rst pl_resetn0 ] + set pl_resetn1 [ create_bd_port -dir O -type rst pl_resetn1 ] + set pl_resetn2 [ create_bd_port -dir O -type rst pl_resetn2 ] + set pl_resetn3 [ create_bd_port -dir O -type rst pl_resetn3 ] + set pll_ref_clk_in [ create_bd_port -dir I -type clk pll_ref_clk_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {61440000} \ + ] $pll_ref_clk_in + set pll_ref_clk_out [ create_bd_port -dir O -type clk pll_ref_clk_out ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {61440000} \ + ] $pll_ref_clk_out + set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ] + set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ] + set rfdc_clk [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \ + CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \ + CONFIG.FREQ_HZ {184320000} \ + ] $rfdc_clk + set rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk_2x ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {368640000} \ + ] $rfdc_clk_2x + set rfdc_irq [ create_bd_port -dir O -type intr rfdc_irq ] + set s_axi_hp0_aclk [ create_bd_port -dir I -type clk s_axi_hp0_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axi_hp0} \ + CONFIG.ASSOCIATED_RESET {s_axi_hp0_aresetn} \ + CONFIG.FREQ_HZ {40000000} \ + ] $s_axi_hp0_aclk + set s_axi_hp1_aclk [ create_bd_port -dir I -type clk s_axi_hp1_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axi_hp1} \ + CONFIG.FREQ_HZ {40000000} \ + ] $s_axi_hp1_aclk + set s_axi_hpc0_aclk [ create_bd_port -dir I -type clk s_axi_hpc0_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axi_hpc0} \ + ] $s_axi_hpc0_aclk + set start_nco_reset_dclk [ create_bd_port -dir I start_nco_reset_dclk ] + set sysref_out_pclk [ create_bd_port -dir O sysref_out_pclk ] + set sysref_out_rclk [ create_bd_port -dir O sysref_out_rclk ] + set sysref_pl_in [ create_bd_port -dir I sysref_pl_in ] + + # Create instance: ps + create_hier_cell_ps [current_bd_instance .] ps + + # Create instance: rfdc + create_hier_cell_rfdc [current_bd_instance .] rfdc + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_hp0] [get_bd_intf_pins ps/s_axi_hp0] + connect_bd_intf_net -intf_net S_AXIS_S2MM_1_1 [get_bd_intf_ports s_axis_eth_dma] [get_bd_intf_pins ps/s_axis_eth_dma] + connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports s_axi_hp1] [get_bd_intf_pins ps/s_axi_hp1] + connect_bd_intf_net -intf_net S_AXI_HPC0_FPD_0_1 [get_bd_intf_ports s_axi_hpc0] [get_bd_intf_pins ps/s_axi_hpc0] + connect_bd_intf_net -intf_net adc0_clk_0_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins rfdc/adc0_clk] + connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_ports adc2_clk] [get_bd_intf_pins rfdc/adc2_clk] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_uhd [get_bd_intf_ports m_axi_app] [get_bd_intf_pins ps/m_axi_app] + connect_bd_intf_net -intf_net dac0_clk_0_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins rfdc/dac0_clk] + connect_bd_intf_net -intf_net dac1_clk_0_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins rfdc/dac1_clk] + connect_bd_intf_net -intf_net inst_zynq_ps_GPIO_0 [get_bd_intf_ports gpio_0] [get_bd_intf_pins ps/gpio_0] + connect_bd_intf_net -intf_net ps_M07_AXI_0 [get_bd_intf_ports m_axi_eth_internal] [get_bd_intf_pins ps/m_axi_eth_internal] + connect_bd_intf_net -intf_net ps_M_AXIS_MM2S_1 [get_bd_intf_ports m_axis_eth_dma] [get_bd_intf_pins ps/m_axis_eth_dma] + connect_bd_intf_net -intf_net ps_M_AXI_0 [get_bd_intf_ports m_axi_rpu] [get_bd_intf_pins ps/m_axi_rpu] + connect_bd_intf_net -intf_net ps_m_axi_core_0 [get_bd_intf_ports m_axi_core] [get_bd_intf_pins ps/m_axi_core] + connect_bd_intf_net -intf_net ps_m_axi_mpm_ep [get_bd_intf_ports m_axi_mpm_ep] [get_bd_intf_pins ps/m_axi_mpm_ep] + connect_bd_intf_net -intf_net ps_m_axi_rf [get_bd_intf_pins ps/m_axi_rf] [get_bd_intf_pins rfdc/s_axi_config] + connect_bd_intf_net -intf_net rf_data_converter_m00_axis [get_bd_intf_ports adc_tile224_ch0_dout_i] [get_bd_intf_pins rfdc/adc_tile224_ch0_dout_i] + connect_bd_intf_net -intf_net rf_data_converter_m01_axis [get_bd_intf_ports adc_tile224_ch0_dout_q] [get_bd_intf_pins rfdc/adc_tile224_ch0_dout_q] + connect_bd_intf_net -intf_net rf_data_converter_m02_axis [get_bd_intf_ports adc_tile224_ch1_dout_i] [get_bd_intf_pins rfdc/adc_tile224_ch1_dout_i] + connect_bd_intf_net -intf_net rf_data_converter_m03_axis [get_bd_intf_ports adc_tile224_ch1_dout_q] [get_bd_intf_pins rfdc/adc_tile224_ch1_dout_q] + connect_bd_intf_net -intf_net rf_data_converter_m20_axis [get_bd_intf_ports adc_tile226_ch0_dout_i] [get_bd_intf_pins rfdc/adc_tile226_ch0_dout_i] + connect_bd_intf_net -intf_net rf_data_converter_m21_axis [get_bd_intf_ports adc_tile226_ch0_dout_q] [get_bd_intf_pins rfdc/adc_tile226_ch0_dout_q] + connect_bd_intf_net -intf_net rf_data_converter_m22_axis [get_bd_intf_ports adc_tile226_ch1_dout_i] [get_bd_intf_pins rfdc/adc_tile226_ch1_dout_i] + connect_bd_intf_net -intf_net rf_data_converter_m23_axis [get_bd_intf_ports adc_tile226_ch1_dout_q] [get_bd_intf_pins rfdc/adc_tile226_ch1_dout_q] + connect_bd_intf_net -intf_net rf_data_converter_vout00 [get_bd_intf_ports dac_tile228_ch0_vout] [get_bd_intf_pins rfdc/dac_tile228_ch0_vout] + connect_bd_intf_net -intf_net rf_data_converter_vout01 [get_bd_intf_ports dac_tile228_ch1_vout] [get_bd_intf_pins rfdc/dac_tile228_ch1_vout] + connect_bd_intf_net -intf_net rf_data_converter_vout10 [get_bd_intf_ports dac_tile229_ch0_vout] [get_bd_intf_pins rfdc/dac_tile229_ch0_vout] + connect_bd_intf_net -intf_net rf_data_converter_vout11 [get_bd_intf_ports dac_tile229_ch1_vout] [get_bd_intf_pins rfdc/dac_tile229_ch1_vout] + connect_bd_intf_net -intf_net s00_axis_0_1 [get_bd_intf_ports dac_tile228_ch0_din] [get_bd_intf_pins rfdc/dac_tile228_ch0_din] + connect_bd_intf_net -intf_net s01_axis_0_1 [get_bd_intf_ports dac_tile228_ch1_din] [get_bd_intf_pins rfdc/dac_tile228_ch1_din] + connect_bd_intf_net -intf_net s10_axis_0_1 [get_bd_intf_ports dac_tile229_ch0_din] [get_bd_intf_pins rfdc/dac_tile229_ch0_din] + connect_bd_intf_net -intf_net s11_axis_0_1 [get_bd_intf_ports dac_tile229_ch1_din] [get_bd_intf_pins rfdc/dac_tile229_ch1_din] + connect_bd_intf_net -intf_net s_axi_hpc1 [get_bd_intf_ports s_axi_hpc1] [get_bd_intf_pins ps/s_axi_hpc1] + connect_bd_intf_net -intf_net sysref_in_0_1 [get_bd_intf_ports sysref_rf_in] [get_bd_intf_pins rfdc/sysref_rf_in] + connect_bd_intf_net -intf_net vin0_01_0_1 [get_bd_intf_ports adc_tile224_ch0_vin] [get_bd_intf_pins rfdc/adc_tile224_ch0_vin] + connect_bd_intf_net -intf_net vin0_23_0_1 [get_bd_intf_ports adc_tile224_ch1_vin] [get_bd_intf_pins rfdc/adc_tile224_ch1_vin] + connect_bd_intf_net -intf_net vin2_01_0_1 [get_bd_intf_ports adc_tile226_ch0_vin] [get_bd_intf_pins rfdc/adc_tile226_ch0_vin] + connect_bd_intf_net -intf_net vin2_23_0_1 [get_bd_intf_ports adc_tile226_ch1_vin] [get_bd_intf_pins rfdc/adc_tile226_ch1_vin] + + # Create port connections + connect_bd_net -net Net [get_bd_ports jtag0_tck] [get_bd_pins ps/jtag0_tck] + connect_bd_net -net Net1 [get_bd_ports jtag0_tdi] [get_bd_pins ps/jtag0_tdi] + connect_bd_net -net Net2 [get_bd_ports jtag0_tms] [get_bd_pins ps/jtag0_tms] + connect_bd_net -net S02_ARESETN_0_1 [get_bd_ports bus_rstn] [get_bd_pins ps/bus_rstn] + connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_ports adc_reset_pulse_dclk] [get_bd_pins rfdc/adc_reset_pulse_dclk] + connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_ports sysref_out_rclk] [get_bd_pins rfdc/sysref_out_rclk] + connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_ports sysref_out_pclk] [get_bd_pins rfdc/sysref_out_pclk] + connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins ps/clk40] [get_bd_pins rfdc/s_axi_config_clk] + connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins ps/clk40_rstn] [get_bd_pins rfdc/s_axi_config_aresetn] + connect_bd_net -net clk_in1_0_1 [get_bd_ports pll_ref_clk_in] [get_bd_pins rfdc/pll_ref_clk_in] + connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_ports dac_reset_pulse_dclk] [get_bd_pins rfdc/dac_reset_pulse_dclk] + connect_bd_net -net data_clock_mmcm_data_clk [get_bd_ports data_clk] [get_bd_pins rfdc/data_clk] + connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_ports data_clk_2x] [get_bd_pins rfdc/data_clk_2x] + connect_bd_net -net data_clock_mmcm_locked [get_bd_ports data_clock_locked] [get_bd_pins rfdc/data_clock_locked] + connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_ports pll_ref_clk_out] [get_bd_pins rfdc/pll_ref_clk_out] + connect_bd_net -net enable_gated_clocks_1 [get_bd_ports enable_gated_clocks_clk40] [get_bd_pins rfdc/enable_gated_clocks_clk40] + connect_bd_net -net enable_rclk_0_1 [get_bd_ports enable_sysref_rclk] [get_bd_pins rfdc/enable_sysref_rclk] + connect_bd_net -net gpio2_io_i_0_2 [get_bd_ports rf_dsp_info_clk40] [get_bd_pins rfdc/rf_dsp_info_sclk] + connect_bd_net -net gpio_io_i_0_1 [get_bd_ports rf_axi_status_clk40] [get_bd_pins rfdc/rf_axi_status_sclk] + connect_bd_net -net inst_zynq_ps_pl_clk0 [get_bd_ports pl_clk100] [get_bd_pins ps/pl_clk100] + connect_bd_net -net inst_zynq_ps_pl_clk1 [get_bd_ports pl_clk40] [get_bd_pins ps/pl_clk40] + connect_bd_net -net inst_zynq_ps_pl_clk2 [get_bd_ports pl_clk166] [get_bd_pins ps/pl_clk166] + connect_bd_net -net inst_zynq_ps_pl_clk3 [get_bd_ports pl_clk200] [get_bd_pins ps/pl_clk200] + connect_bd_net -net inst_zynq_ps_pl_resetn0 [get_bd_ports pl_resetn0] [get_bd_pins ps/pl_resetn0] + connect_bd_net -net inst_zynq_ps_pl_resetn1 [get_bd_ports pl_resetn1] [get_bd_pins ps/pl_resetn1] + connect_bd_net -net inst_zynq_ps_pl_resetn2 [get_bd_ports pl_resetn2] [get_bd_pins ps/pl_resetn2] + connect_bd_net -net inst_zynq_ps_pl_resetn3 [get_bd_ports pl_resetn3] [get_bd_pins ps/pl_resetn3] + connect_bd_net -net jtag0_tdo_1 [get_bd_ports jtag0_tdo] [get_bd_pins ps/jtag0_tdo] + connect_bd_net -net m_axi_sg_aclk_0_1 [get_bd_ports bus_clk] [get_bd_pins ps/bus_clk] + connect_bd_net -net nirq0_lpd_rpu_0_1 [get_bd_ports irq0_lpd_rpu_n] [get_bd_pins ps/irq0_lpd_rpu_n] + connect_bd_net -net nirq1_lpd_rpu_0_1 [get_bd_ports irq1_lpd_rpu_n] [get_bd_pins ps/irq1_lpd_rpu_n] + connect_bd_net -net pl_ps_irq0_1 [get_bd_ports pl_ps_irq0] [get_bd_pins ps/pl_ps_irq0] + connect_bd_net -net pl_ps_irq1_0_1 [get_bd_ports pl_ps_irq1] [get_bd_pins ps/pl_ps_irq1_1] + connect_bd_net -net rStartNcoReset_0_1 [get_bd_ports start_nco_reset_dclk] [get_bd_pins rfdc/start_nco_reset_dclk] + connect_bd_net -net rf_data_converter_irq [get_bd_ports rfdc_irq] [get_bd_pins rfdc/rfdc_irq] + connect_bd_net -net rf_nco_reset_0_rNcoResetDone [get_bd_ports nco_reset_done_dclk] [get_bd_pins rfdc/nco_reset_done_dclk] + connect_bd_net -net rf_reset_controller_0_rAdcEnableData [get_bd_ports adc_enable_data_rclk] [get_bd_pins rfdc/adc_enable_data_rclk] + connect_bd_net -net rfdc_adc_rfdc_axi_resetn_rclk [get_bd_ports adc_rfdc_axi_resetn_rclk] [get_bd_pins rfdc/adc_rfdc_axi_resetn_rclk] + connect_bd_net -net rfdc_d2DacFirReset_n_0 [get_bd_ports dac_data_in_resetn_dclk2x] [get_bd_pins rfdc/dac_data_in_resetn_dclk2x] + connect_bd_net -net rfdc_dAdcDataOutReset_n_0 [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins rfdc/adc_data_out_resetn_dclk] + connect_bd_net -net rfdc_dDacDataInReset_n_0 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins rfdc/dac_data_in_resetn_dclk] + connect_bd_net -net rfdc_dac_data_in_resetn_rclk [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins rfdc/dac_data_in_resetn_rclk] + connect_bd_net -net rfdc_gated_base_clk_valid [get_bd_ports gated_base_clks_valid_clk40] [get_bd_pins rfdc/gated_base_clks_valid_clk40] + connect_bd_net -net rfdc_invert_adc_iq_rclk2 [get_bd_ports invert_adc_iq_rclk2] [get_bd_pins rfdc/invert_adc_iq_rclk2] + connect_bd_net -net rfdc_invert_dac_iq_rclk2 [get_bd_ports invert_dac_iq_rclk2] [get_bd_pins rfdc/invert_dac_iq_rclk2] + connect_bd_net -net rfdc_r2AdcFirReset_n_0 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins rfdc/fir_resetn_rclk2x] + connect_bd_net -net rfdc_r2DacFirReset_n_0 [get_bd_ports dac_data_in_resetn_rclk2x] [get_bd_pins rfdc/dac_data_in_resetn_rclk2x] + connect_bd_net -net rfdc_rfdc_clk [get_bd_ports rfdc_clk] [get_bd_pins rfdc/rfdc_clk] + connect_bd_net -net rfdc_rfdc_clk_2x [get_bd_ports rfdc_clk_2x] [get_bd_pins rfdc/rfdc_clk_2x] + connect_bd_net -net s_axi_hp0_aclk_1 [get_bd_ports s_axi_hp0_aclk] [get_bd_pins ps/s_axi_hp0_aclk] + connect_bd_net -net s_axi_hp1_aclk_1 [get_bd_ports s_axi_hp1_aclk] [get_bd_pins ps/s_axi_hp1_aclk] + connect_bd_net -net saxihpc0_fpd_aclk_0_1 [get_bd_ports s_axi_hpc0_aclk] [get_bd_pins ps/s_axi_hpc0_aclk] + connect_bd_net -net sysref_pl_in_1 [get_bd_ports sysref_pl_in] [get_bd_pins rfdc/sysref_pl_in] + + # Create address segments + create_bd_addr_seg -range 0x00004000 -offset 0x0010000A4000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] SEG_axi_eth_dma_internal_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000155000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000154000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] SEG_axi_gpio_data_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] SEG_cpld_jtag_engine_reg0 + create_bd_addr_seg -range 0x00010000 -offset 0x001000140000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] SEG_data_clock_mmcm_Reg + create_bd_addr_seg -range 0x000200000000 -offset 0x001200000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] SEG_m_axi_app_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x0010000A0000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] SEG_m_axi_core_0_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x0010000A8000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg + create_bd_addr_seg -range 0x00020000 -offset 0x001000080000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] SEG_m_axi_mpm_ep_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x80000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] SEG_m_axi_rpu_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000156000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] SEG_reg_clock_gate_control_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000150000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] SEG_reg_invert_iq_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000151000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] SEG_reg_reset_mmcm_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000153000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] SEG_reg_rf_axi_status_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x001000152000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] SEG_reg_rf_reset_control_Reg + create_bd_addr_seg -range 0x00040000 -offset 0x001000100000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] SEG_rf_data_converter_Reg + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] SEG_inst_zynq_ps_HP0_DDR_HIGH + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] SEG_inst_zynq_ps_HP0_DDR_LOW + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] SEG_inst_zynq_ps_HP0_LPS_OCM + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] SEG_inst_zynq_ps_HP1_DDR_HIGH + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] SEG_inst_zynq_ps_HP1_DDR_LOW + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] SEG_inst_zynq_ps_HP1_LPS_OCM + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] SEG_inst_zynq_ps_HPC0_DDR_HIGH + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] SEG_inst_zynq_ps_HPC0_DDR_LOW + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] SEG_inst_zynq_ps_HPC0_LPS_OCM + create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM + + # Exclude Address Segments + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM + exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S/SEG_inst_zynq_ps_HPC1_LPS_OCM] + + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM + exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM/SEG_inst_zynq_ps_HPC1_LPS_OCM] + + create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM + exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_SG/SEG_inst_zynq_ps_HPC1_LPS_OCM] + + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc b/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc new file mode 100644 index 000000000..4df9bcc5f --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc @@ -0,0 +1,47 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +XGE_PCS_PMA_SRCS = \ +$(IP_DIR)/xge_pcs_pma/ten_gige_phy.v \ +$(IP_DIR)/xge_pcs_pma/eth_10g.sv \ +$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) + +IP_XGE_PCS_PMA_HDL_SIM_SRCS = $(IP_DIR)/xge_pcs_pma/model_10gbe.sv \ +$(wildcard $(addprefix $(IP_BUILD_DIR)/xge_pcs_pma/, \ +xge_pcs_pma.v \ +hdl/xxv_ethernet_v3_0_vl_rfs.sv \ +ip_0/hdl/*.v \ +ip_0/sim/*.v \ +xxv_ethernet_v3_0_1/*.v \ +)) + +IP_XGE_PCS_PMA_EXAMPLE_SRCS = \ +$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_common_wrapper.v \ +$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_gt_gtye4_common_wrapper.v \ +$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/gtwizard_ultrascale_v1_7_gtye4_common.v \ + +# Describe the paths for the patch file, the file to be patched, and the +# patched copy of the file. +IP_XGE_FILE_PATCH = $(IP_DIR)/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch +IP_XGE_FILE_TO_PATCH = $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v3_0_1/xge_pcs_pma_wrapper.v +IP_XGE_PATCHED_FILE = $(IP_BUILD_DIR)/xge_pcs_pma_wrapper.v.patched + +IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_PATCHED_FILE) + +IP_XGE_PCS_PMA_OUTS = \ +$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci.out \ +$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.v \ + +$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS) + +$(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS) : $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_FILE_PATCH) + $(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_FILE_TO_PATCH).orig + cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_PATCHED_FILE) + patch $(IP_XGE_PATCHED_FILE) $(IP_XGE_FILE_PATCH) + $(call REBUILD_VIVADO_IP_WITH_PATCH,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0,$(call RESOLVE_PATH,$(IP_XGE_PATCHED_FILE)),$(call RESOLVE_PATH,$(IP_XGE_FILE_TO_PATCH))) diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/eth_10g.sv b/fpga/usrp3/top/x400/ip/xge_pcs_pma/eth_10g.sv new file mode 100644 index 000000000..41e60e789 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/eth_10g.sv @@ -0,0 +1,173 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: eth_10g +// +// Description: Wrapper for the 10G mac and phy + + +module eth_10g ( + + // Resets + input logic areset, + // Clock for misc stuff + input logic clk100, + // Shared Quad signals + output logic[0:0] qpll0_reset, + input logic[0:0] qpll0_lock, + input logic[0:0] qpll0_clk, + input logic[0:0] qpll0_refclk, + output logic[0:0] qpll1_reset, + input logic[0:0] qpll1_lock, + input logic[0:0] qpll1_clk, + input logic[0:0] qpll1_refclk, + // RX Clk for output + output logic rx_rec_clk_out, + // MGT high-speed IO + output logic tx_p, + output logic tx_n, + input logic rx_p, + input logic rx_n, + + // Data port + output logic mgt_clk, + output logic mgt_rst, + // Interface clocks for mgt_tx and mgt_rx are NOT used (logic uses using mgt_clk) + AxiStreamIf.slave mgt_tx, + AxiStreamIf.master mgt_rx, + // Axi port + AxiLiteIf.slave mgt_axil, + // Misc + output logic [31:0] phy_status, + input logic [31:0] mac_ctrl, + output logic [31:0] mac_status, + output logic phy_reset, + output logic link_up +); + + import PkgAxiLite::*; + + assign phy_status[31:8] = 24'h0; + assign mac_status[31:9] = 23'h0; + assign link_up = phy_status[0]; + + // respond with error if anyone reads this memory region + always_comb begin + mgt_axil.awready = 1'b1; + mgt_axil.wready = 1'b1; + mgt_axil.bresp= SLVERR; + mgt_axil.bvalid = 1'b1; + mgt_axil.arready = 1'b1; + mgt_axil.rdata = 'b0; + mgt_axil.rresp = SLVERR; + mgt_axil.rvalid = 1'b1; + end + + logic xgmii_clk; + logic [63:0] xgmii_txd; + logic [7:0] xgmii_txc; + logic [63:0] xgmii_rxd; + logic [7:0] xgmii_rxc; + logic xge_phy_resetdone; + + assign phy_reset = !xge_phy_resetdone; + assign mgt_clk = xgmii_clk; + + // This is a heavily replicated signal, add some pipeline + // to it to make it easier to spread out + logic mgt_rst_0; + + always_ff @(posedge mgt_clk,posedge areset) begin : reset_timing_dff + if (areset) begin + mgt_rst_0 = 1'b1; + mgt_rst = 1'b1; + end else begin + mgt_rst_0 = !link_up; + mgt_rst = mgt_rst_0; + end + end + + // areset pin notes - reset is used asynchronously + ten_gige_phy ten_gige_phy_i ( + .areset (areset), + .dclk (clk100), + .xgmii_clk (xgmii_clk), + .txp (tx_p), + .txn (tx_n), + .rxp (rx_p), + .rxn (rx_n), + .xgmii_txd (xgmii_txd), + .xgmii_txc (xgmii_txc), + .xgmii_rxd (xgmii_rxd), + .xgmii_rxc (xgmii_rxc), + .qpll0_refclk (qpll0_refclk), + .qpll0_clk (qpll0_clk), + .qpll0_lock (qpll0_lock), + .qpll0_reset (qpll0_reset), + .qpll1_refclk (qpll1_refclk), + .qpll1_clk (qpll1_clk), + .qpll1_lock (qpll1_lock), + .qpll1_reset (qpll1_reset), + .rxrecclkout (rx_rec_clk_out), + .core_status (phy_status[7:0]), + .reset_done (xge_phy_resetdone) + ); + + xge_mac_wrapper #( + .PORTNUM(0), + .WISHBONE(0), + .ADD_PREAMBLE(0), + .CROSS_TO_SYSCLK(0), + .CUT_THROUGH(15) + ) xge_mac_wrapper_i ( + // XGMII + .xgmii_clk(xgmii_clk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(1'b0), + .sys_rst(1'b0), + .rx_tdata(mgt_rx.tdata), + .rx_tuser(mgt_rx.tuser), + .rx_tlast(mgt_rx.tlast), + .rx_tvalid(mgt_rx.tvalid), + .rx_tready(mgt_rx.tready), + .tx_tdata(mgt_tx.tdata), + .tx_tuser(mgt_tx.tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(mgt_tx.tlast), + .tx_tvalid(mgt_tx.tvalid), + .tx_tready(mgt_tx.tready), + // Control and Status + .phy_ready(xge_phy_resetdone), + .ctrl_tx_enable(mac_ctrl[0]), + .status_crc_error(mac_status[0]), + .status_fragment_error(mac_status[1]), + .status_txdfifo_ovflow(mac_status[2]), + .status_txdfifo_udflow(mac_status[3]), + .status_rxdfifo_ovflow(mac_status[4]), + .status_rxdfifo_udflow(mac_status[5]), + .status_pause_frame_rx(mac_status[6]), + .status_local_fault(mac_status[7]), + .status_remote_fault(mac_status[8]), + // MDIO + .mdc(), + .mdio_in(), + .mdio_out(1'b0), + // Wishbone + .wb_ack_o(), + .wb_dat_o(), + .wb_adr_i(8'b0), + .wb_clk_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_i(32'b0), + .wb_rst_i(1'b0), + .wb_stb_i(1'b0), + .wb_we_i (1'b0), + .wb_int_o() + ); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv b/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv new file mode 100644 index 000000000..bda0c2c64 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/model_10gbe.sv @@ -0,0 +1,174 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: model_10gbe +// +// Description: +// +// A wrapper of the 10gbe core to axistream interface. this model can be used +// drive packets into the x400 translated to serial ethernet. This is far +// slower than just driving things in at the output of the mac with force's +// + +module model_10gbe #( + parameter [7:0] PORTNUM = 8'd0 +)( + input logic areset, + // 156.25 Mhz refclk + input logic ref_clk, + + // QSFP high-speed IO + output logic tx_p, + output logic tx_n, + input logic rx_p, + input logic rx_n, + + // CLK and RESET - 156.25 + output logic mgt_clk, + output logic mgt_rst, + output logic link_up, + + + // Data port + AxiStreamIf.slave mgt_tx, + AxiStreamIf.master mgt_rx + +); + + // Include macros and time declarations for use with PkgTestExec + `define TEST_EXEC_OBJ test + `include "test_exec.svh" + import PkgAxiLiteBfm::*; + import PkgTestExec::*; + + logic clk40,clk40_rst; + logic clk100,clk100_rst; + logic phy_reset; + + //interface + AxiLiteIf #(32,32) + mgt_axil (clk40, clk40_rst); + //bfm + AxiLiteBfm #(32, 32) axi = new(.master(mgt_axil)); + TestExec mac_test = new(); + + sim_clock_gen #(.PERIOD(25.0), .AUTOSTART(1)) + clk40_gen (.clk(clk40), .rst(clk40_rst)); + sim_clock_gen #(.PERIOD(100.0), .AUTOSTART(1)) + clk100_gen (.clk(clk100), .rst(clk100_rst)); + + // Register Docs for init_model + // MAC CTRL REG Bit positions + // ctrl_tx_enable = mac_ctrl[0] + // MAC STATUS REG Bit positions + // status_crc_error = mac_status[0] 1 + // status_fragment_error = mac_status[1] 2 + // status_txdfifo_ovflow = mac_status[2] 4 + // status_txdfifo_udflow = mac_status[3] 8 + // status_rxdfifo_ovflow = mac_status[4] 10 + // status_rxdfifo_udflow = mac_status[5] 20 + // status_pause_frame_rx = mac_status[6] 40 + // status_local_fault = mac_status[7] 80 + // status_remote_fault = mac_status[8] 100 + + logic [31:0] phy_status; + logic [31:0] mac_status; + logic [31:0] mac_ctrl; + + initial begin : init_model + mac_ctrl = 0; + + clk40_gen.reset(); + axi.run(); + wait(!clk40_rst); + repeat (10) @(posedge clk40); + + mac_test.start_test("model_10gbe::Wait for phy reset done", 150us); + wait(phy_reset===1'b0); + mac_test.end_test(); + + mac_test.start_test("model_10gbe::Wait for MAC link_up", 150us); + mac_ctrl[0] = 1; // turn on TX + wait(link_up===1'b1); + mac_test.end_test(); + end + + logic [0:0] qpll0_reset; + logic [0:0] qpll0_lock; + logic [0:0] qpll0_clk; + logic [0:0] qpll0_refclk; + logic [0:0] qpll1_reset; + logic [0:0] qpll1_lock; + logic [0:0] qpll1_clk; + logic [0:0] qpll1_refclk; + + xge_pcs_pma_common_wrapper xge_pcs_pma_common_wrapperx ( + .refclk (ref_clk), + .qpll0reset (qpll0_reset), + .qpll0lock (qpll0_lock), + .qpll0outclk (qpll0_clk), + .qpll0outrefclk (qpll0_refclk), + .qpll1reset (qpll1_reset), + .qpll1lock (qpll1_lock), + .qpll1outclk (qpll1_clk), + .qpll1outrefclk (qpll1_refclk) + ); + + AxiStreamIf #(.DATA_WIDTH(64),.USER_WIDTH(4)) + eth10g_rx(mgt_clk,mgt_rst); + + always_comb begin + mgt_rx.tdata = eth10g_rx.tdata; + mgt_rx.tuser = eth10g_rx.tuser; + mgt_rx.tkeep = eth10g_rx.trailing2keep(eth10g_rx.tuser); + mgt_rx.tvalid = eth10g_rx.tvalid; + mgt_rx.tlast = eth10g_rx.tlast; + // The MAC ignores hold off. Data must be consumed every clock it is valid. + if (!mgt_rst) begin + if (!mgt_rx.tready && mgt_rx.tvalid) begin + $error("Model 100Gbe : can't hold off the MAC"); + end + end + end + + eth_10g eth_10g_i ( + .areset(areset), + //-- Free running 100 MHz clock used for InitClk and AxiLite to mac + .clk100(clk100), + // Quad Info + .qpll0_refclk (qpll0_refclk), + .qpll0_clk (qpll0_clk), + .qpll0_lock (qpll0_lock), + .qpll0_reset (qpll0_reset), + .qpll1_refclk (qpll1_refclk), + .qpll1_clk (qpll1_clk), + .qpll1_lock (qpll1_lock), + .qpll1_reset (qpll1_reset), + // MGT TX/RX differential signals + .tx_p(tx_p), + .tx_n(tx_n), + .rx_p(rx_p), + .rx_n(rx_n), + // MAC system_clock + .mgt_clk(mgt_clk), + .mgt_rst(mgt_rst), + //------------------------ AXI Stream TX Interface ------------------------ + .mgt_tx(mgt_tx), + //---------------------- AXI Stream RX Interface ------------------------ + // There is no RxTReady signal support by the Ethernet100G IP. Received data has to + // be read immediately or it is lost. + // tUser indicates an error on rcvd packet + .mgt_rx(eth10g_rx), + // Axi-Lite bus for tie off + .mgt_axil(mgt_axil), + // LEDs of QSFP28 port + .phy_status(phy_status), + .mac_ctrl(mac_ctrl), + .mac_status(mac_status), + .phy_reset(phy_reset), + .link_up(link_up) + ); + +endmodule diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/x400/ip/xge_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..b419c45da --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/ten_gige_phy.v @@ -0,0 +1,274 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ten_gige_phy +// +// Description: +// +// Wrapper for the Xilinx xxv_ethernet IP (10G/25G Ethernet Subsystem). +// + + +module ten_gige_phy ( + input wire areset, + input wire dclk, + output wire xgmii_clk, + + // Transceiver IO + output wire txp, + output wire txn, + input wire rxp, + input wire rxn, + + // XGMII Interface + input wire [63:0] xgmii_txd, + input wire [ 7:0] xgmii_txc, + output wire [63:0] xgmii_rxd, + output wire [ 7:0] xgmii_rxc, + + // GTYE4_COMMON + input wire qpll0_refclk, + input wire qpll0_clk, + input wire qpll0_lock, + output wire qpll0_reset, + input wire qpll1_refclk, + input wire qpll1_clk, + input wire qpll1_lock, + output wire qpll1_reset, + + output wire rxrecclkout, + output wire [7:0] core_status, + output reg reset_done +); + + localparam XGMII_FREQ = 125_000_000; // xgmii_clk frequency in Hz + localparam RX_RST_WAIT = XGMII_FREQ/2; // Cycles to wait before resetting + localparam RX_RST_DURATION = 100; // Duration of reset in cycles + localparam RX_RST_COUNT_W = $clog2(RX_RST_WAIT); + + wire rx_serdes_reset; + wire tx_reset; + wire rx_reset; + + wire a_gt_reset_tx_done, gt_reset_tx_done; + wire a_gt_reset_rx_done, gt_reset_rx_done; + + wire stat_rx_status_tmp; + reg stat_rx_status; + + reg [RX_RST_COUNT_W-1:0] rst_count; + reg gt_rx_reset_in; + + //--------------------------------------------------------------------------- + // Xilinx 10G/25G IP High Speed Ethernet Subsystem Instance + //--------------------------------------------------------------------------- + + // All connections below follow the Xilinx IP example design, except that + // rx_core_clk is driven by tx_mii_clk instead of rx_clk_out. This puts the + // RX and TX interfaces on the same clock domain. + + // gtwiz_reset_qpll1reset_out is not connected to qpll1reset in the example + // design. Instead, qpll1reset is connected to 0. + assign qpll1_reset = 1'b0; + + xge_pcs_pma xge_pcs_pma_i ( + .gt_rxp_in_0 (rxp), + .gt_rxn_in_0 (rxn), + .gt_txp_out_0 (txp), + .gt_txn_out_0 (txn), + .rx_core_clk_0 (xgmii_clk), + .rx_serdes_reset_0 (rx_serdes_reset), + .txoutclksel_in_0 (3'b101), + .rxoutclksel_in_0 (3'b101), + .gt_dmonitorout_0 (), + .gt_eyescandataerror_0 (), + .gt_eyescanreset_0 (1'b0), + .gt_eyescantrigger_0 (1'b0), + .gt_pcsrsvdin_0 (16'b0), + .gt_rxbufreset_0 (1'b0), + .gt_rxbufstatus_0 (), + .gt_rxcdrhold_0 (1'b0), + .gt_rxcommadeten_0 (1'b0), + .gt_rxdfeagchold_0 (1'b0), + .gt_rxdfelpmreset_0 (1'b0), + .gt_rxlatclk_0 (1'b0), + .gt_rxlpmen_0 (1'b0), + .gt_rxpcsreset_0 (1'b0), + .gt_rxpmareset_0 (1'b0), + .gt_rxpolarity_0 (1'b0), + .gt_rxprbscntreset_0 (1'b0), + .gt_rxprbserr_0 (), + .gt_rxprbssel_0 (4'b0), + .gt_rxrate_0 (3'b0), + .gt_rxslide_in_0 (1'b0), + .gt_rxstartofseq_0 (), + .gt_txbufstatus_0 (), + .gt_txdiffctrl_0 (5'h18), + .gt_txinhibit_0 (1'b0), + .gt_txlatclk_0 (1'b0), + .gt_txmaincursor_0 (7'h50), + .gt_txpcsreset_0 (1'b0), + .gt_txpmareset_0 (1'b0), + .gt_txpolarity_0 (1'b0), + .gt_txpostcursor_0 (5'b0), + .gt_txprbsforceerr_0 (1'b0), + .gt_txprbssel_0 (4'b0), + .gt_txprecursor_0 (5'b0), + .rxrecclkout_0 (rxrecclkout), + .gt_drpclk_0 (dclk), + .gt_drpdo_0 (), + .gt_drprdy_0 (), + .gt_drpen_0 (1'b0), + .gt_drpwe_0 (1'b0), + .gt_drpaddr_0 (10'b0), + .gt_drpdi_0 (16'b0), + .sys_reset (areset), + .dclk (dclk), + .tx_mii_clk_0 (xgmii_clk), + .rx_clk_out_0 (), + .gtpowergood_out_0 (), + .qpll0clk_in (qpll0_clk), + .qpll0refclk_in (qpll0_refclk), + .qpll1clk_in (qpll1_clk), + .qpll1refclk_in (qpll1_refclk), + .gtwiz_reset_qpll0lock_in (qpll0_lock), + .gtwiz_reset_qpll1lock_in (qpll1_lock), + .gtwiz_reset_qpll0reset_out (qpll0_reset), + .gtwiz_reset_qpll1reset_out (), + .gt_reset_tx_done_out_0 (a_gt_reset_tx_done), + .gt_reset_rx_done_out_0 (a_gt_reset_rx_done), + .gt_reset_all_in_0 (areset), + .gt_tx_reset_in_0 (1'b0), + .gt_rx_reset_in_0 (gt_rx_reset_in), + .rx_reset_0 (rx_reset), + .rx_mii_d_0 (xgmii_rxd), + .rx_mii_c_0 (xgmii_rxc), + .ctl_rx_test_pattern_0 (1'b0), + .ctl_rx_test_pattern_enable_0 (1'b0), + .ctl_rx_data_pattern_select_0 (1'b0), + .ctl_rx_prbs31_test_pattern_enable_0 (1'b0), + .stat_rx_framing_err_0 (), + .stat_rx_framing_err_valid_0 (), + .stat_rx_local_fault_0 (), + .stat_rx_block_lock_0 (), + .stat_rx_valid_ctrl_code_0 (), + .stat_rx_status_0 (stat_rx_status_tmp), // rx_core_clk_0 domain + .stat_rx_hi_ber_0 (), + .stat_rx_bad_code_0 (), + .stat_rx_bad_code_valid_0 (), + .stat_rx_error_0 (), + .stat_rx_error_valid_0 (), + .stat_rx_fifo_error_0 (), + .tx_reset_0 (tx_reset), + .tx_mii_d_0 (xgmii_txd), + .tx_mii_c_0 (xgmii_txc), + .stat_tx_local_fault_0 (), + .ctl_tx_test_pattern_0 (1'b0), + .ctl_tx_test_pattern_enable_0 (1'b0), + .ctl_tx_test_pattern_select_0 (1'b0), + .ctl_tx_data_pattern_select_0 (1'b0), + .ctl_tx_test_pattern_seed_a_0 (58'b0), + .ctl_tx_test_pattern_seed_b_0 (58'b0), + .ctl_tx_prbs31_test_pattern_enable_0 (1'b0), + .gt_loopback_in_0 (3'b0) + ); + + + //--------------------------------------------------------------------------- + // Status + //--------------------------------------------------------------------------- + + assign core_status[7:1] = 0; // Unused + assign core_status[0] = stat_rx_status; // Link status + + // Safely combine the RX and TX reset done signals into a single glitch-free + // signal. + + synchronizer sync_reset_tx_done ( + .clk (xgmii_clk), + .rst (1'b0), + .in (a_gt_reset_tx_done), + .out (gt_reset_tx_done) + ); + + synchronizer sync_reset_rx_done ( + .clk (xgmii_clk), + .rst (1'b0), + .in (a_gt_reset_rx_done), + .out (gt_reset_rx_done) + ); + + always @(posedge xgmii_clk) begin : ResetDoneProc + reset_done <= gt_reset_tx_done & gt_reset_rx_done; + end + + + //--------------------------------------------------------------------------- + // Reset Logic + //--------------------------------------------------------------------------- + + // The reset synchronization below is taken from the example design, except + // that rx_clk_out was replaced by tx_mii_clk (xgmii_clk). + + synchronizer sync_rx_serdes_reset ( + .clk (xgmii_clk), + .rst (1'b0), + .in (~a_gt_reset_rx_done), + .out (rx_serdes_reset) + ); + + synchronizer sync_tx_reset ( + .clk (xgmii_clk), + .rst (1'b0), + .in (~a_gt_reset_tx_done), + .out (tx_reset) + ); + + synchronizer sync_rx_reset ( + .clk (xgmii_clk), + .rst (1'b0), + .in (~a_gt_reset_rx_done), + .out (rx_reset) + ); + + // This state machine resets the RX GT part of the core periodically when + // the link is down. This is necessary due to a bug in the Xilinx IP. + always @(posedge xgmii_clk, posedge areset) begin + if (areset) begin + gt_rx_reset_in <= 0; + rst_count <= 0; + stat_rx_status <= 0; + end else begin + stat_rx_status <= stat_rx_status_tmp; + + // Periodically reset until link is up + if (!stat_rx_status) begin + rst_count <= rst_count + 1; + + if (!gt_rx_reset_in) begin + // We're not in reset. Wait until RX_RST_WAIT cycles have elapsed, + // then reset. + if (rst_count == RX_RST_WAIT-1) begin + rst_count <= 0; + gt_rx_reset_in <= 1; + end + end else begin + // We're in reset. Wait until RX_RST_DURATION cycles have elapsed + // before deasserting reset. + if (rst_count == RX_RST_DURATION-1) begin + rst_count <= 0; + gt_rx_reset_in <= 0; + end + end + + // Currently linked, so all is well + end else begin + rst_count <= 0; + gt_rx_reset_in <= 0; + end + end + end + +endmodule diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci b/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci new file mode 100644 index 000000000..aeda24d44 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci @@ -0,0 +1,1184 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>xge_pcs_pma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xxv_ethernet" spirit:version="3.0"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RESET_ALL_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RESET_ALL_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RESET_ALL_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RESET_ALL_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RX_RESET_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RX_RESET_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RX_RESET_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_RX_RESET_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_TX_RESET_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_TX_RESET_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_TX_RESET_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTL_GT_TX_RESET_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_0_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_1_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_2_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_3_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_TX_DATAPATH_0_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_TX_DATAPATH_1_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_TX_DATAPATH_2_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_TX_DATAPATH_3_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REF_CLK.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_ALL_IN_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_ALL_IN_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_ALL_IN_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_ALL_IN_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_RX_DONE_OUT_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_RX_DONE_OUT_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_RX_DONE_OUT_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_RX_DONE_OUT_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_TX_DONE_OUT_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_TX_DONE_OUT_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_TX_DONE_OUT_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_TX_DONE_OUT_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_SERIAL_PORT.CAN_DEBUG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.FREQ_HZ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.FREQ_HZ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.FREQ_HZ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.FREQ_HZ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.ADDR_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.ARUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.AWUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.BUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.DATA_WIDTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_BRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_CACHE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_LOCK">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_PROT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_QOS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_REGION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_RRESP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_WSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.MAX_BURST_LENGTH">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_READ_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_WRITE_THREADS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.PROTOCOL">AXI4LITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.RUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.WUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_RX_RESET_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_RX_RESET_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_RX_RESET_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_RX_RESET_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_TX_RESET_0.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_TX_RESET_1.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_TX_RESET_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_TX_RESET_3.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ANLT_CLK_IN_MHZ">100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BASE_R_KR">BASE-R</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCKING">Asynchronous</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_INTERFACE">MII</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_DATAPATH_PARITY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINE_REG">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PREEMPTION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PREEMPTION_FIFO">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_TIME_STAMPING">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_TX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY_CHK">zynquplus</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAST_SIM_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_DIFFCTRL_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_DRP_CLK">100.00</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_GROUP_SELECT">Quad X0Y0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_LOCATION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_REF_CLK_FREQ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_TYPE">GTY</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_AUTO_NEG_LT_LOGIC">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_AXI4_INTERFACE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_FEC_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_HYBRID_CMAC_RSFEC_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_RSFEC_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_STATISTICS_COUNTERS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_USER_FIFO">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INS_LOSS_NYQ">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE1_GT_LOC">X0Y16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE2_GT_LOC">NA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE3_GT_LOC">NA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE4_GT_LOC">NA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LINE_RATE">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MII_CTRL_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MII_DATA_WIDTH">64</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_CORES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PTP_CLOCKING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PTP_OPERATION_MODE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RUNTIME_SWITCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_EQ_MODE">AUTO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATISTICS_REGS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SWITCH_1_10_25G">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_LATENCY_ADJUST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_TOTAL_BYTES_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XGMII_INTERFACE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_BOARD_PROJECT">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ANLT_CLK_IN_MHZ">100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BASE_R_KR">BASE-R</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCKING">Asynchronous</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xge_pcs_pma</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE">MII</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFFCLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATAPATH_PARITY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PIPELINE_REG">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PREEMPTION">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PREEMPTION_FIFO">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TIME_STAMPING">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FAST_SIM_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DRP_CLK">100.00</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_GROUP_SELECT">Quad_X0Y4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_LOCATION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_REF_CLK_FREQ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_TYPE">GTY</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_AUTO_NEG_LT_LOGIC">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_AXI4_INTERFACE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_FEC_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_HYBRID_CMAC_RSFEC_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_RSFEC_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_STATISTICS_COUNTERS">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_USER_FIFO">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">30</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE1_GT_LOC">X0Y16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE2_GT_LOC">NA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE3_GT_LOC">NA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE4_GT_LOC">NA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LINE_RATE">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_CORES">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PTP_CLOCKING_MODE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PTP_OPERATION_MODE">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUNTIME_SWITCH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_EQ_MODE">AUTO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATISTICS_REGS_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SWITCH_1_10_25G">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYS_CLK">4000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_LATENCY_ADJUST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XGMII_INTERFACE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplusRFSOC</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu28dr</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvg1517</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TREADY" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_0.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_1.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_2.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_3.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BASE_R_KR" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CORE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_PIPELINE_REG" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_GROUP_SELECT" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_REF_CLK_FREQ" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_SHARED_LOGIC" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_USER_FIFO" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LANE1_GT_LOC" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LINE_RATE" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch b/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch new file mode 100644 index 000000000..ba059bc44 --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch @@ -0,0 +1,30 @@ +692a693,712 +> +> //--------------------------------------------------------------------------- +> // Workaround for link status bug. See SR 10471238 for details. +> //--------------------------------------------------------------------------- +> +> reg [13:0] rx_clk_noctrlcode_count; +> +> always @(posedge rx_core_clk_0) begin +> if (rx_reset_done_0 == 1'b1) begin +> rx_clk_noctrlcode_count <= 14'h270F; +> end else begin +> if (stat_rx_valid_ctrl_code_0 == 1'b1) begin +> rx_clk_noctrlcode_count <= 14'h270F; +> end else begin +> rx_clk_noctrlcode_count <= rx_clk_noctrlcode_count - 1; +> end +> end +> end +> +> //--------------------------------------------------------------------------- +700c720,725 +< if(stat_rx_block_lock_0 == 1'b0) +--- +> //------------------------------------------------------------------------ +> // Workaround for link status bug. See SR 10471238 for details. +> // Original code: if(stat_rx_block_lock_0 == 1'b0) +> // New code: +> if(stat_rx_block_lock_0 == 1'b0 || rx_clk_noctrlcode_count ==14'h0) +> //------------------------------------------------------------------------ |