3 files changed, 92 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore
new file mode 100644
index 000000000..87dce88a7
--- /dev/null
+++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/.gitignore
@@ -0,0 +1,3 @@
+# generate files
+clkctrl/
+clkctrl.sopcinfo
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc
new file mode 100644
index 000000000..2015c6976
--- /dev/null
+++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/quartus_ip_builder.mak
+
+IP_CLKCTRL_SRCS = \
+$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys
+
+IP_CLKCTRL_OUTS = \
+$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo
+
+$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys
+	$(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys
new file mode 100644
index 000000000..7a77cfc14
--- /dev/null
+++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/ip/clkctrl/clkctrl.qsys
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element altclkctrl_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10M04SAU324I7G" />
+ <parameter name="deviceFamily" value="MAX 10" />
+ <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altclkctrl_input"
+   internal="altclkctrl_0.altclkctrl_input"
+   type="conduit"
+   dir="end">
+  <port name="inclk" internal="inclk" />
+  <port name="ena" internal="ena" />
+ </interface>
+ <interface
+   name="altclkctrl_output"
+   internal="altclkctrl_0.altclkctrl_output"
+   type="conduit"
+   dir="end">
+  <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="18.1"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CLOCK_TYPE" value="1" />
+  <parameter name="DEVICE_FAMILY" value="MAX 10" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="GUI_USE_ENA" value="true" />
+  <parameter name="NUMBER_OF_CLOCKS" value="1" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>