diff options
Diffstat (limited to 'fpga/usrp3/top/x400/cpld/regmap')
9 files changed, 735 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh new file mode 100644 index 000000000..4e5921f4c --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/constants_regmap_utils.vh @@ -0,0 +1,28 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: constants_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group CONSTANTS_GROUP +//=============================================================================== + + // Enumerated type CONSTANTS_ENUM + localparam CONSTANTS_ENUM_SIZE = 4; + localparam PS_CPLD_SIGNATURE = 'hA522D27; // CONSTANTS_ENUM:PS_CPLD_SIGNATURE + localparam OLDEST_CPLD_REVISION = 'h20122114; // CONSTANTS_ENUM:OLDEST_CPLD_REVISION + localparam CPLD_REVISION = 'h21012015; // CONSTANTS_ENUM:CPLD_REVISION + localparam PL_CPLD_SIGNATURE = 'h3FDC5C47; // CONSTANTS_ENUM:PL_CPLD_SIGNATURE diff --git a/fpga/usrp3/top/x400/cpld/regmap/jtag_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/jtag_regmap_utils.vh new file mode 100644 index 000000000..f57e28ea9 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/jtag_regmap_utils.vh @@ -0,0 +1,57 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: jtag_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // TX_DATA : 0x0 (ctrlport_to_jtag.v) + // STB_DATA : 0x4 (ctrlport_to_jtag.v) + // CONTROL : 0x8 (ctrlport_to_jtag.v) + // RX_DATA : 0xC (ctrlport_to_jtag.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group JTAG_REGS +//=============================================================================== + + // TX_DATA Register (from ctrlport_to_jtag.v) + localparam TX_DATA = 'h0; // Register Offset + localparam TX_DATA_SIZE = 32; // register width in bits + localparam TX_DATA_MASK = 32'h0; + + // STB_DATA Register (from ctrlport_to_jtag.v) + localparam STB_DATA = 'h4; // Register Offset + localparam STB_DATA_SIZE = 32; // register width in bits + localparam STB_DATA_MASK = 32'h0; + + // CONTROL Register (from ctrlport_to_jtag.v) + localparam CONTROL = 'h8; // Register Offset + localparam CONTROL_SIZE = 32; // register width in bits + localparam CONTROL_MASK = 32'h80001FFF; + localparam PRESCALAR_SIZE = 8; //CONTROL:prescalar + localparam PRESCALAR_MSB = 7; //CONTROL:prescalar + localparam PRESCALAR = 0; //CONTROL:prescalar + localparam LENGTH_SIZE = 5; //CONTROL:length + localparam LENGTH_MSB = 12; //CONTROL:length + localparam LENGTH = 8; //CONTROL:length + localparam RESET_SIZE = 1; //CONTROL:reset + localparam RESET_MSB = 31; //CONTROL:reset + localparam RESET = 31; //CONTROL:reset + localparam READY_SIZE = 1; //CONTROL:ready + localparam READY_MSB = 31; //CONTROL:ready + localparam READY = 31; //CONTROL:ready + + // RX_DATA Register (from ctrlport_to_jtag.v) + localparam RX_DATA = 'hC; // Register Offset + localparam RX_DATA_SIZE = 32; // register width in bits + localparam RX_DATA_MASK = 32'h0; diff --git a/fpga/usrp3/top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh new file mode 100644 index 000000000..d70590690 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh @@ -0,0 +1,36 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: mb_cpld_pl_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // PL_REGISTERS : 0x0 (mb_cpld.v) + // JTAG_DB0 : 0x60 (mb_cpld.v) + // JTAG_DB1 : 0x80 (mb_cpld.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group MB_CPLD_PL_WINDOWS +//=============================================================================== + + // PL_REGISTERS Window (from mb_cpld.v) + localparam PL_REGISTERS = 'h0; // Window Offset + localparam PL_REGISTERS_SIZE = 'h40; // size in bytes + + // JTAG_DB0 Window (from mb_cpld.v) + localparam JTAG_DB0 = 'h60; // Window Offset + localparam JTAG_DB0_SIZE = 'h20; // size in bytes + + // JTAG_DB1 Window (from mb_cpld.v) + localparam JTAG_DB1 = 'h80; // Window Offset + localparam JTAG_DB1_SIZE = 'h20; // size in bytes diff --git a/fpga/usrp3/top/x400/cpld/regmap/mb_cpld_ps_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/mb_cpld_ps_regmap_utils.vh new file mode 100644 index 000000000..9eb044c10 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/mb_cpld_ps_regmap_utils.vh @@ -0,0 +1,51 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: mb_cpld_ps_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // PS_REGISTERS : 0x0 (mb_cpld.v) + // RECONFIG : 0x40 (mb_cpld.v) + // POWER_REGISTERS : 0x60 (mb_cpld.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group MB_CPLD_PS_WINDOWS +//=============================================================================== + + // PS_REGISTERS Window (from mb_cpld.v) + localparam PS_REGISTERS = 'h0; // Window Offset + localparam PS_REGISTERS_SIZE = 'h40; // size in bytes + + // RECONFIG Window (from mb_cpld.v) + localparam RECONFIG = 'h40; // Window Offset + localparam RECONFIG_SIZE = 'h20; // size in bytes + + // POWER_REGISTERS Window (from mb_cpld.v) + localparam POWER_REGISTERS = 'h60; // Window Offset + localparam POWER_REGISTERS_SIZE = 'h20; // size in bytes + +//=============================================================================== +// Register Group PS_SPI_ENDPOINTS +//=============================================================================== + + // Enumerated type SPI_ENDPOINT + localparam SPI_ENDPOINT_SIZE = 8; + localparam PS_CS_MB_CPLD = 'h0; // SPI_ENDPOINT:PS_CS_MB_CPLD + localparam PS_CS_LMK32 = 'h1; // SPI_ENDPOINT:PS_CS_LMK32 + localparam PS_CS_TPM = 'h2; // SPI_ENDPOINT:PS_CS_TPM + localparam PS_CS_PHASE_DAC = 'h3; // SPI_ENDPOINT:PS_CS_PHASE_DAC + localparam PS_CS_DB0_CAL_EEPROM = 'h4; // SPI_ENDPOINT:PS_CS_DB0_CAL_EEPROM + localparam PS_CS_DB1_CAL_EEPROM = 'h5; // SPI_ENDPOINT:PS_CS_DB1_CAL_EEPROM + localparam PS_CS_CLK_AUX_DB = 'h6; // SPI_ENDPOINT:PS_CS_CLK_AUX_DB + localparam PS_CS_IDLE = 'h7; // SPI_ENDPOINT:PS_CS_IDLE diff --git a/fpga/usrp3/top/x400/cpld/regmap/pl_cpld_base_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/pl_cpld_base_regmap_utils.vh new file mode 100644 index 000000000..820216d71 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/pl_cpld_base_regmap_utils.vh @@ -0,0 +1,122 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: pl_cpld_base_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // SIGNATURE_REGISTER : 0x0 (pl_cpld_regs.v) + // REVISION_REGISTER : 0x4 (pl_cpld_regs.v) + // OLDEST_COMPATIBLE_REVISION_REGISTER : 0x8 (pl_cpld_regs.v) + // SCRATCH_REGISTER : 0xC (pl_cpld_regs.v) + // GIT_HASH_REGISTER : 0x10 (pl_cpld_regs.v) + // LED_REGISTER : 0x20 (pl_cpld_regs.v) + // CABLE_PRESENT_REG : 0x30 (pl_cpld_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group MB_CPLD_LED_REGS +//=============================================================================== + + // LED_REGISTER Register (from pl_cpld_regs.v) + localparam LED_REGISTER = 'h20; // Register Offset + localparam LED_REGISTER_SIZE = 16; // register width in bits + localparam LED_REGISTER_MASK = 16'hFFFF; + localparam QSFP0_LED_LINK_SIZE = 4; //LED_REGISTER:QSFP0_LED_LINK + localparam QSFP0_LED_LINK_MSB = 3; //LED_REGISTER:QSFP0_LED_LINK + localparam QSFP0_LED_LINK = 0; //LED_REGISTER:QSFP0_LED_LINK + localparam QSFP0_LED_ACTIVE_SIZE = 4; //LED_REGISTER:QSFP0_LED_ACTIVE + localparam QSFP0_LED_ACTIVE_MSB = 7; //LED_REGISTER:QSFP0_LED_ACTIVE + localparam QSFP0_LED_ACTIVE = 4; //LED_REGISTER:QSFP0_LED_ACTIVE + localparam QSFP1_LED_LINK_SIZE = 4; //LED_REGISTER:QSFP1_LED_LINK + localparam QSFP1_LED_LINK_MSB = 11; //LED_REGISTER:QSFP1_LED_LINK + localparam QSFP1_LED_LINK = 8; //LED_REGISTER:QSFP1_LED_LINK + localparam QSFP1_LED_ACTIVE_SIZE = 4; //LED_REGISTER:QSFP1_LED_ACTIVE + localparam QSFP1_LED_ACTIVE_MSB = 15; //LED_REGISTER:QSFP1_LED_ACTIVE + localparam QSFP1_LED_ACTIVE = 12; //LED_REGISTER:QSFP1_LED_ACTIVE + +//=============================================================================== +// Register Group PL_CMI_REGS +//=============================================================================== + + // CABLE_PRESENT_REG Register (from pl_cpld_regs.v) + localparam CABLE_PRESENT_REG = 'h30; // Register Offset + localparam CABLE_PRESENT_REG_SIZE = 2; // register width in bits + localparam CABLE_PRESENT_REG_MASK = 2'h3; + localparam IPASS0_CABLE_PRESENT_SIZE = 1; //CABLE_PRESENT_REG:IPASS0_CABLE_PRESENT + localparam IPASS0_CABLE_PRESENT_MSB = 0; //CABLE_PRESENT_REG:IPASS0_CABLE_PRESENT + localparam IPASS0_CABLE_PRESENT = 0; //CABLE_PRESENT_REG:IPASS0_CABLE_PRESENT + localparam IPASS1_CABLE_PRESENT_SIZE = 1; //CABLE_PRESENT_REG:IPASS1_CABLE_PRESENT + localparam IPASS1_CABLE_PRESENT_MSB = 1; //CABLE_PRESENT_REG:IPASS1_CABLE_PRESENT + localparam IPASS1_CABLE_PRESENT = 1; //CABLE_PRESENT_REG:IPASS1_CABLE_PRESENT + +//=============================================================================== +// Register Group PL_CPLD_BASE_REGS +//=============================================================================== + + // SIGNATURE_REGISTER Register (from pl_cpld_regs.v) + localparam SIGNATURE_REGISTER = 'h0; // Register Offset + localparam SIGNATURE_REGISTER_SIZE = 32; // register width in bits + localparam SIGNATURE_REGISTER_MASK = 32'hFFFFFFFF; + localparam PRODUCT_SIGNATURE_SIZE = 32; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + localparam PRODUCT_SIGNATURE_MSB = 31; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + localparam PRODUCT_SIGNATURE = 0; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + + // REVISION_REGISTER Register (from pl_cpld_regs.v) + localparam REVISION_REGISTER = 'h4; // Register Offset + localparam REVISION_REGISTER_SIZE = 32; // register width in bits + localparam REVISION_REGISTER_MASK = 32'hFFFFFFFF; + localparam REVISION_HH_SIZE = 8; //REVISION_REGISTER:REVISION_HH + localparam REVISION_HH_MSB = 7; //REVISION_REGISTER:REVISION_HH + localparam REVISION_HH = 0; //REVISION_REGISTER:REVISION_HH + localparam REVISION_DD_SIZE = 8; //REVISION_REGISTER:REVISION_DD + localparam REVISION_DD_MSB = 15; //REVISION_REGISTER:REVISION_DD + localparam REVISION_DD = 8; //REVISION_REGISTER:REVISION_DD + localparam REVISION_MM_SIZE = 8; //REVISION_REGISTER:REVISION_MM + localparam REVISION_MM_MSB = 23; //REVISION_REGISTER:REVISION_MM + localparam REVISION_MM = 16; //REVISION_REGISTER:REVISION_MM + localparam REVISION_YY_SIZE = 8; //REVISION_REGISTER:REVISION_YY + localparam REVISION_YY_MSB = 31; //REVISION_REGISTER:REVISION_YY + localparam REVISION_YY = 24; //REVISION_REGISTER:REVISION_YY + + // OLDEST_COMPATIBLE_REVISION_REGISTER Register (from pl_cpld_regs.v) + localparam OLDEST_COMPATIBLE_REVISION_REGISTER = 'h8; // Register Offset + localparam OLDEST_COMPATIBLE_REVISION_REGISTER_SIZE = 32; // register width in bits + localparam OLDEST_COMPATIBLE_REVISION_REGISTER_MASK = 32'hFFFFFFFF; + localparam OLD_REVISION_HH_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_HH + localparam OLD_REVISION_HH_MSB = 7; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_HH + localparam OLD_REVISION_HH = 0; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_HH + localparam OLD_REVISION_DD_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_DD + localparam OLD_REVISION_DD_MSB = 15; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_DD + localparam OLD_REVISION_DD = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_DD + localparam OLD_REVISION_MM_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_MM + localparam OLD_REVISION_MM_MSB = 23; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_MM + localparam OLD_REVISION_MM = 16; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_MM + localparam OLD_REVISION_YY_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_YY + localparam OLD_REVISION_YY_MSB = 31; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_YY + localparam OLD_REVISION_YY = 24; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_YY + + // SCRATCH_REGISTER Register (from pl_cpld_regs.v) + localparam SCRATCH_REGISTER = 'hC; // Register Offset + localparam SCRATCH_REGISTER_SIZE = 32; // register width in bits + localparam SCRATCH_REGISTER_MASK = 32'h0; + + // GIT_HASH_REGISTER Register (from pl_cpld_regs.v) + localparam GIT_HASH_REGISTER = 'h10; // Register Offset + localparam GIT_HASH_REGISTER_SIZE = 32; // register width in bits + localparam GIT_HASH_REGISTER_MASK = 32'hFFFFFFFF; + localparam GIT_HASH_SIZE = 28; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_HASH_MSB = 27; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_HASH = 0; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_CLEAN_SIZE = 4; //GIT_HASH_REGISTER:GIT_CLEAN + localparam GIT_CLEAN_MSB = 31; //GIT_HASH_REGISTER:GIT_CLEAN + localparam GIT_CLEAN = 28; //GIT_HASH_REGISTER:GIT_CLEAN diff --git a/fpga/usrp3/top/x400/cpld/regmap/ps_cpld_base_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/ps_cpld_base_regmap_utils.vh new file mode 100644 index 000000000..a5a067bb4 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/ps_cpld_base_regmap_utils.vh @@ -0,0 +1,183 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ps_cpld_base_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // SIGNATURE_REGISTER : 0x0 (ps_cpld_regs.v) + // REVISION_REGISTER : 0x4 (ps_cpld_regs.v) + // OLDEST_COMPATIBLE_REVISION_REGISTER : 0x8 (ps_cpld_regs.v) + // SCRATCH_REGISTER : 0xC (ps_cpld_regs.v) + // GIT_HASH_REGISTER : 0x10 (ps_cpld_regs.v) + // PL_DB_REGISTER : 0x20 (ps_cpld_regs.v) + // DIO_DIRECTION_REGISTER : 0x30 (ps_cpld_regs.v) + // SERIAL_NUM_LOW_REG : 0x34 (ps_cpld_regs.v) + // SERIAL_NUM_HIGH_REG : 0x38 (ps_cpld_regs.v) + // CMI_CONTROL_STATUS : 0x3C (ps_cpld_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group DIO_REGS +//=============================================================================== + + // DIO_DIRECTION_REGISTER Register (from ps_cpld_regs.v) + localparam DIO_DIRECTION_REGISTER = 'h30; // Register Offset + localparam DIO_DIRECTION_REGISTER_SIZE = 32; // register width in bits + localparam DIO_DIRECTION_REGISTER_MASK = 32'hFFF0FFF; + localparam DIO_DIRECTION_A_SIZE = 12; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A + localparam DIO_DIRECTION_A_MSB = 11; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A + localparam DIO_DIRECTION_A = 0; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A + localparam DIO_DIRECTION_B_SIZE = 12; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B + localparam DIO_DIRECTION_B_MSB = 27; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B + localparam DIO_DIRECTION_B = 16; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B + +//=============================================================================== +// Register Group PS_CMI_REGS +//=============================================================================== + + // SERIAL_NUM_LOW_REG Register (from ps_cpld_regs.v) + localparam SERIAL_NUM_LOW_REG = 'h34; // Register Offset + localparam SERIAL_NUM_LOW_REG_SIZE = 32; // register width in bits + localparam SERIAL_NUM_LOW_REG_MASK = 32'h0; + + // SERIAL_NUM_HIGH_REG Register (from ps_cpld_regs.v) + localparam SERIAL_NUM_HIGH_REG = 'h38; // Register Offset + localparam SERIAL_NUM_HIGH_REG_SIZE = 8; // register width in bits + localparam SERIAL_NUM_HIGH_REG_MASK = 8'h0; + + // CMI_CONTROL_STATUS Register (from ps_cpld_regs.v) + localparam CMI_CONTROL_STATUS = 'h3C; // Register Offset + localparam CMI_CONTROL_STATUS_SIZE = 32; // register width in bits + localparam CMI_CONTROL_STATUS_MASK = 32'h80000001; + localparam CMI_READY_SIZE = 1; //CMI_CONTROL_STATUS:CMI_READY + localparam CMI_READY_MSB = 0; //CMI_CONTROL_STATUS:CMI_READY + localparam CMI_READY = 0; //CMI_CONTROL_STATUS:CMI_READY + localparam OTHER_SIDE_DETECTED_SIZE = 1; //CMI_CONTROL_STATUS:OTHER_SIDE_DETECTED + localparam OTHER_SIDE_DETECTED_MSB = 31; //CMI_CONTROL_STATUS:OTHER_SIDE_DETECTED + localparam OTHER_SIDE_DETECTED = 31; //CMI_CONTROL_STATUS:OTHER_SIDE_DETECTED + +//=============================================================================== +// Register Group PS_CONTROL_REGS +//=============================================================================== + + // PL_DB_REGISTER Register (from ps_cpld_regs.v) + localparam PL_DB_REGISTER = 'h20; // Register Offset + localparam PL_DB_REGISTER_SIZE = 32; // register width in bits + localparam PL_DB_REGISTER_MASK = 32'h337737; + localparam DB0_CLOCK_ENABLED_SIZE = 1; //PL_DB_REGISTER:DB0_CLOCK_ENABLED + localparam DB0_CLOCK_ENABLED_MSB = 0; //PL_DB_REGISTER:DB0_CLOCK_ENABLED + localparam DB0_CLOCK_ENABLED = 0; //PL_DB_REGISTER:DB0_CLOCK_ENABLED + localparam DB1_CLOCK_ENABLED_SIZE = 1; //PL_DB_REGISTER:DB1_CLOCK_ENABLED + localparam DB1_CLOCK_ENABLED_MSB = 1; //PL_DB_REGISTER:DB1_CLOCK_ENABLED + localparam DB1_CLOCK_ENABLED = 1; //PL_DB_REGISTER:DB1_CLOCK_ENABLED + localparam PLL_REF_CLOCK_ENABLED_SIZE = 1; //PL_DB_REGISTER:PLL_REF_CLOCK_ENABLED + localparam PLL_REF_CLOCK_ENABLED_MSB = 2; //PL_DB_REGISTER:PLL_REF_CLOCK_ENABLED + localparam PLL_REF_CLOCK_ENABLED = 2; //PL_DB_REGISTER:PLL_REF_CLOCK_ENABLED + localparam DB0_RESET_ASSERTED_SIZE = 1; //PL_DB_REGISTER:DB0_RESET_ASSERTED + localparam DB0_RESET_ASSERTED_MSB = 4; //PL_DB_REGISTER:DB0_RESET_ASSERTED + localparam DB0_RESET_ASSERTED = 4; //PL_DB_REGISTER:DB0_RESET_ASSERTED + localparam DB1_RESET_ASSERTED_SIZE = 1; //PL_DB_REGISTER:DB1_RESET_ASSERTED + localparam DB1_RESET_ASSERTED_MSB = 5; //PL_DB_REGISTER:DB1_RESET_ASSERTED + localparam DB1_RESET_ASSERTED = 5; //PL_DB_REGISTER:DB1_RESET_ASSERTED + localparam ENABLE_CLOCK_DB0_SIZE = 1; //PL_DB_REGISTER:ENABLE_CLOCK_DB0 + localparam ENABLE_CLOCK_DB0_MSB = 8; //PL_DB_REGISTER:ENABLE_CLOCK_DB0 + localparam ENABLE_CLOCK_DB0 = 8; //PL_DB_REGISTER:ENABLE_CLOCK_DB0 + localparam ENABLE_CLOCK_DB1_SIZE = 1; //PL_DB_REGISTER:ENABLE_CLOCK_DB1 + localparam ENABLE_CLOCK_DB1_MSB = 9; //PL_DB_REGISTER:ENABLE_CLOCK_DB1 + localparam ENABLE_CLOCK_DB1 = 9; //PL_DB_REGISTER:ENABLE_CLOCK_DB1 + localparam ENABLE_PLL_REF_CLOCK_SIZE = 1; //PL_DB_REGISTER:ENABLE_PLL_REF_CLOCK + localparam ENABLE_PLL_REF_CLOCK_MSB = 10; //PL_DB_REGISTER:ENABLE_PLL_REF_CLOCK + localparam ENABLE_PLL_REF_CLOCK = 10; //PL_DB_REGISTER:ENABLE_PLL_REF_CLOCK + localparam DISABLE_CLOCK_DB0_SIZE = 1; //PL_DB_REGISTER:DISABLE_CLOCK_DB0 + localparam DISABLE_CLOCK_DB0_MSB = 12; //PL_DB_REGISTER:DISABLE_CLOCK_DB0 + localparam DISABLE_CLOCK_DB0 = 12; //PL_DB_REGISTER:DISABLE_CLOCK_DB0 + localparam DISABLE_CLOCK_DB1_SIZE = 1; //PL_DB_REGISTER:DISABLE_CLOCK_DB1 + localparam DISABLE_CLOCK_DB1_MSB = 13; //PL_DB_REGISTER:DISABLE_CLOCK_DB1 + localparam DISABLE_CLOCK_DB1 = 13; //PL_DB_REGISTER:DISABLE_CLOCK_DB1 + localparam DISABLE_PLL_REF_CLOCK_SIZE = 1; //PL_DB_REGISTER:DISABLE_PLL_REF_CLOCK + localparam DISABLE_PLL_REF_CLOCK_MSB = 14; //PL_DB_REGISTER:DISABLE_PLL_REF_CLOCK + localparam DISABLE_PLL_REF_CLOCK = 14; //PL_DB_REGISTER:DISABLE_PLL_REF_CLOCK + localparam RELEASE_RESET_DB0_SIZE = 1; //PL_DB_REGISTER:RELEASE_RESET_DB0 + localparam RELEASE_RESET_DB0_MSB = 16; //PL_DB_REGISTER:RELEASE_RESET_DB0 + localparam RELEASE_RESET_DB0 = 16; //PL_DB_REGISTER:RELEASE_RESET_DB0 + localparam RELEASE_RESET_DB1_SIZE = 1; //PL_DB_REGISTER:RELEASE_RESET_DB1 + localparam RELEASE_RESET_DB1_MSB = 17; //PL_DB_REGISTER:RELEASE_RESET_DB1 + localparam RELEASE_RESET_DB1 = 17; //PL_DB_REGISTER:RELEASE_RESET_DB1 + localparam ASSERT_RESET_DB0_SIZE = 1; //PL_DB_REGISTER:ASSERT_RESET_DB0 + localparam ASSERT_RESET_DB0_MSB = 20; //PL_DB_REGISTER:ASSERT_RESET_DB0 + localparam ASSERT_RESET_DB0 = 20; //PL_DB_REGISTER:ASSERT_RESET_DB0 + localparam ASSERT_RESET_DB1_SIZE = 1; //PL_DB_REGISTER:ASSERT_RESET_DB1 + localparam ASSERT_RESET_DB1_MSB = 21; //PL_DB_REGISTER:ASSERT_RESET_DB1 + localparam ASSERT_RESET_DB1 = 21; //PL_DB_REGISTER:ASSERT_RESET_DB1 + +//=============================================================================== +// Register Group PS_CPLD_BASE_REGS +//=============================================================================== + + // SIGNATURE_REGISTER Register (from ps_cpld_regs.v) + localparam SIGNATURE_REGISTER = 'h0; // Register Offset + localparam SIGNATURE_REGISTER_SIZE = 32; // register width in bits + localparam SIGNATURE_REGISTER_MASK = 32'hFFFFFFFF; + localparam PRODUCT_SIGNATURE_SIZE = 32; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + localparam PRODUCT_SIGNATURE_MSB = 31; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + localparam PRODUCT_SIGNATURE = 0; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + + // REVISION_REGISTER Register (from ps_cpld_regs.v) + localparam REVISION_REGISTER = 'h4; // Register Offset + localparam REVISION_REGISTER_SIZE = 32; // register width in bits + localparam REVISION_REGISTER_MASK = 32'hFFFFFFFF; + localparam REVISION_HH_SIZE = 8; //REVISION_REGISTER:REVISION_HH + localparam REVISION_HH_MSB = 7; //REVISION_REGISTER:REVISION_HH + localparam REVISION_HH = 0; //REVISION_REGISTER:REVISION_HH + localparam REVISION_DD_SIZE = 8; //REVISION_REGISTER:REVISION_DD + localparam REVISION_DD_MSB = 15; //REVISION_REGISTER:REVISION_DD + localparam REVISION_DD = 8; //REVISION_REGISTER:REVISION_DD + localparam REVISION_MM_SIZE = 8; //REVISION_REGISTER:REVISION_MM + localparam REVISION_MM_MSB = 23; //REVISION_REGISTER:REVISION_MM + localparam REVISION_MM = 16; //REVISION_REGISTER:REVISION_MM + localparam REVISION_YY_SIZE = 8; //REVISION_REGISTER:REVISION_YY + localparam REVISION_YY_MSB = 31; //REVISION_REGISTER:REVISION_YY + localparam REVISION_YY = 24; //REVISION_REGISTER:REVISION_YY + + // OLDEST_COMPATIBLE_REVISION_REGISTER Register (from ps_cpld_regs.v) + localparam OLDEST_COMPATIBLE_REVISION_REGISTER = 'h8; // Register Offset + localparam OLDEST_COMPATIBLE_REVISION_REGISTER_SIZE = 32; // register width in bits + localparam OLDEST_COMPATIBLE_REVISION_REGISTER_MASK = 32'hFFFFFFFF; + localparam OLD_REVISION_HH_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_HH + localparam OLD_REVISION_HH_MSB = 7; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_HH + localparam OLD_REVISION_HH = 0; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_HH + localparam OLD_REVISION_DD_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_DD + localparam OLD_REVISION_DD_MSB = 15; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_DD + localparam OLD_REVISION_DD = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_DD + localparam OLD_REVISION_MM_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_MM + localparam OLD_REVISION_MM_MSB = 23; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_MM + localparam OLD_REVISION_MM = 16; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_MM + localparam OLD_REVISION_YY_SIZE = 8; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_YY + localparam OLD_REVISION_YY_MSB = 31; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_YY + localparam OLD_REVISION_YY = 24; //OLDEST_COMPATIBLE_REVISION_REGISTER:OLD_REVISION_YY + + // SCRATCH_REGISTER Register (from ps_cpld_regs.v) + localparam SCRATCH_REGISTER = 'hC; // Register Offset + localparam SCRATCH_REGISTER_SIZE = 32; // register width in bits + localparam SCRATCH_REGISTER_MASK = 32'h0; + + // GIT_HASH_REGISTER Register (from ps_cpld_regs.v) + localparam GIT_HASH_REGISTER = 'h10; // Register Offset + localparam GIT_HASH_REGISTER_SIZE = 32; // register width in bits + localparam GIT_HASH_REGISTER_MASK = 32'hFFFFFFFF; + localparam GIT_HASH_SIZE = 28; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_HASH_MSB = 27; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_HASH = 0; //GIT_HASH_REGISTER:GIT_HASH + localparam GIT_CLEAN_SIZE = 4; //GIT_HASH_REGISTER:GIT_CLEAN + localparam GIT_CLEAN_MSB = 31; //GIT_HASH_REGISTER:GIT_CLEAN + localparam GIT_CLEAN = 28; //GIT_HASH_REGISTER:GIT_CLEAN diff --git a/fpga/usrp3/top/x400/cpld/regmap/ps_power_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/ps_power_regmap_utils.vh new file mode 100644 index 000000000..e4021b29e --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/ps_power_regmap_utils.vh @@ -0,0 +1,54 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ps_power_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // IPASS_POWER_REG : 0x0 (ps_power_regs.v) + // OSC_POWER_REG : 0x4 (ps_power_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group PS_POWER_REGS +//=============================================================================== + + // IPASS_POWER_REG Register (from ps_power_regs.v) + localparam IPASS_POWER_REG = 'h0; // Register Offset + localparam IPASS_POWER_REG_SIZE = 32; // register width in bits + localparam IPASS_POWER_REG_MASK = 32'hC0000001; + localparam IPASS_DISABLE_POWER_BIT_SIZE = 1; //IPASS_POWER_REG:IPASS_DISABLE_POWER_BIT + localparam IPASS_DISABLE_POWER_BIT_MSB = 0; //IPASS_POWER_REG:IPASS_DISABLE_POWER_BIT + localparam IPASS_DISABLE_POWER_BIT = 0; //IPASS_POWER_REG:IPASS_DISABLE_POWER_BIT + localparam IPASS_CLEAR_POWER_FAULT0_SIZE = 1; //IPASS_POWER_REG:IPASS_CLEAR_POWER_FAULT0 + localparam IPASS_CLEAR_POWER_FAULT0_MSB = 30; //IPASS_POWER_REG:IPASS_CLEAR_POWER_FAULT0 + localparam IPASS_CLEAR_POWER_FAULT0 = 30; //IPASS_POWER_REG:IPASS_CLEAR_POWER_FAULT0 + localparam IPASS_POWER_FAULT0_SIZE = 1; //IPASS_POWER_REG:IPASS_POWER_FAULT0 + localparam IPASS_POWER_FAULT0_MSB = 30; //IPASS_POWER_REG:IPASS_POWER_FAULT0 + localparam IPASS_POWER_FAULT0 = 30; //IPASS_POWER_REG:IPASS_POWER_FAULT0 + localparam IPASS_CLEAR_POWER_FAULT1_SIZE = 1; //IPASS_POWER_REG:IPASS_CLEAR_POWER_FAULT1 + localparam IPASS_CLEAR_POWER_FAULT1_MSB = 31; //IPASS_POWER_REG:IPASS_CLEAR_POWER_FAULT1 + localparam IPASS_CLEAR_POWER_FAULT1 = 31; //IPASS_POWER_REG:IPASS_CLEAR_POWER_FAULT1 + localparam IPASS_POWER_FAULT1_SIZE = 1; //IPASS_POWER_REG:IPASS_POWER_FAULT1 + localparam IPASS_POWER_FAULT1_MSB = 31; //IPASS_POWER_REG:IPASS_POWER_FAULT1 + localparam IPASS_POWER_FAULT1 = 31; //IPASS_POWER_REG:IPASS_POWER_FAULT1 + + // OSC_POWER_REG Register (from ps_power_regs.v) + localparam OSC_POWER_REG = 'h4; // Register Offset + localparam OSC_POWER_REG_SIZE = 32; // register width in bits + localparam OSC_POWER_REG_MASK = 32'h3; + localparam OSC_100_SIZE = 1; //OSC_POWER_REG:OSC_100 + localparam OSC_100_MSB = 0; //OSC_POWER_REG:OSC_100 + localparam OSC_100 = 0; //OSC_POWER_REG:OSC_100 + localparam OSC_122_88_SIZE = 1; //OSC_POWER_REG:OSC_122_88 + localparam OSC_122_88_MSB = 1; //OSC_POWER_REG:OSC_122_88 + localparam OSC_122_88 = 1; //OSC_POWER_REG:OSC_122_88 diff --git a/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh new file mode 100644 index 000000000..2ddc6a8b9 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/reconfig_regmap_utils.vh @@ -0,0 +1,135 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: reconfig_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // FLASH_STATUS_REG : 0x0 (reconfig_engine.v) + // FLASH_CONTROL_REG : 0x4 (reconfig_engine.v) + // FLASH_ADDR_REG : 0x8 (reconfig_engine.v) + // FLASH_WRITE_DATA_REG : 0xC (reconfig_engine.v) + // FLASH_READ_DATA_REG : 0x10 (reconfig_engine.v) + // FLASH_CFM0_START_ADDR_REG : 0x14 (reconfig_engine.v) + // FLASH_CFM0_END_ADDR_REG : 0x18 (reconfig_engine.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group RECONFIG_REGS +//=============================================================================== + + // Enumerated type FLASH_PRIMARY_IMAGE_ADDR_ENUM + localparam FLASH_PRIMARY_IMAGE_ADDR_ENUM_SIZE = 3; + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = 'h1000; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT + localparam FLASH_PRIMARY_IMAGE_START_ADDR = 'h9C00; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_START_ADDR + localparam FLASH_PRIMARY_IMAGE_END_ADDR = 'h127FF; // FLASH_PRIMARY_IMAGE_ADDR_ENUM:FLASH_PRIMARY_IMAGE_END_ADDR + + // FLASH_STATUS_REG Register (from reconfig_engine.v) + localparam FLASH_STATUS_REG = 'h0; // Register Offset + localparam FLASH_STATUS_REG_SIZE = 32; // register width in bits + localparam FLASH_STATUS_REG_MASK = 32'h13331; + localparam FLASH_WP_ENABLED_SIZE = 1; //FLASH_STATUS_REG:FLASH_WP_ENABLED + localparam FLASH_WP_ENABLED_MSB = 0; //FLASH_STATUS_REG:FLASH_WP_ENABLED + localparam FLASH_WP_ENABLED = 0; //FLASH_STATUS_REG:FLASH_WP_ENABLED + localparam FLASH_READ_IDLE_SIZE = 1; //FLASH_STATUS_REG:FLASH_READ_IDLE + localparam FLASH_READ_IDLE_MSB = 4; //FLASH_STATUS_REG:FLASH_READ_IDLE + localparam FLASH_READ_IDLE = 4; //FLASH_STATUS_REG:FLASH_READ_IDLE + localparam FLASH_READ_ERR_SIZE = 1; //FLASH_STATUS_REG:FLASH_READ_ERR + localparam FLASH_READ_ERR_MSB = 5; //FLASH_STATUS_REG:FLASH_READ_ERR + localparam FLASH_READ_ERR = 5; //FLASH_STATUS_REG:FLASH_READ_ERR + localparam FLASH_ERASE_IDLE_SIZE = 1; //FLASH_STATUS_REG:FLASH_ERASE_IDLE + localparam FLASH_ERASE_IDLE_MSB = 8; //FLASH_STATUS_REG:FLASH_ERASE_IDLE + localparam FLASH_ERASE_IDLE = 8; //FLASH_STATUS_REG:FLASH_ERASE_IDLE + localparam FLASH_ERASE_ERR_SIZE = 1; //FLASH_STATUS_REG:FLASH_ERASE_ERR + localparam FLASH_ERASE_ERR_MSB = 9; //FLASH_STATUS_REG:FLASH_ERASE_ERR + localparam FLASH_ERASE_ERR = 9; //FLASH_STATUS_REG:FLASH_ERASE_ERR + localparam FLASH_WRITE_IDLE_SIZE = 1; //FLASH_STATUS_REG:FLASH_WRITE_IDLE + localparam FLASH_WRITE_IDLE_MSB = 12; //FLASH_STATUS_REG:FLASH_WRITE_IDLE + localparam FLASH_WRITE_IDLE = 12; //FLASH_STATUS_REG:FLASH_WRITE_IDLE + localparam FLASH_WRITE_ERR_SIZE = 1; //FLASH_STATUS_REG:FLASH_WRITE_ERR + localparam FLASH_WRITE_ERR_MSB = 13; //FLASH_STATUS_REG:FLASH_WRITE_ERR + localparam FLASH_WRITE_ERR = 13; //FLASH_STATUS_REG:FLASH_WRITE_ERR + localparam FLASH_MEM_INIT_ENABLED_SIZE = 1; //FLASH_STATUS_REG:FLASH_MEM_INIT_ENABLED + localparam FLASH_MEM_INIT_ENABLED_MSB = 16; //FLASH_STATUS_REG:FLASH_MEM_INIT_ENABLED + localparam FLASH_MEM_INIT_ENABLED = 16; //FLASH_STATUS_REG:FLASH_MEM_INIT_ENABLED + + // FLASH_CONTROL_REG Register (from reconfig_engine.v) + localparam FLASH_CONTROL_REG = 'h4; // Register Offset + localparam FLASH_CONTROL_REG_SIZE = 32; // register width in bits + localparam FLASH_CONTROL_REG_MASK = 32'h7FF; + localparam FLASH_ENABLE_WP_STB_SIZE = 1; //FLASH_CONTROL_REG:FLASH_ENABLE_WP_STB + localparam FLASH_ENABLE_WP_STB_MSB = 0; //FLASH_CONTROL_REG:FLASH_ENABLE_WP_STB + localparam FLASH_ENABLE_WP_STB = 0; //FLASH_CONTROL_REG:FLASH_ENABLE_WP_STB + localparam FLASH_DISABLE_WP_STB_SIZE = 1; //FLASH_CONTROL_REG:FLASH_DISABLE_WP_STB + localparam FLASH_DISABLE_WP_STB_MSB = 1; //FLASH_CONTROL_REG:FLASH_DISABLE_WP_STB + localparam FLASH_DISABLE_WP_STB = 1; //FLASH_CONTROL_REG:FLASH_DISABLE_WP_STB + localparam FLASH_READ_STB_SIZE = 1; //FLASH_CONTROL_REG:FLASH_READ_STB + localparam FLASH_READ_STB_MSB = 2; //FLASH_CONTROL_REG:FLASH_READ_STB + localparam FLASH_READ_STB = 2; //FLASH_CONTROL_REG:FLASH_READ_STB + localparam FLASH_WRITE_STB_SIZE = 1; //FLASH_CONTROL_REG:FLASH_WRITE_STB + localparam FLASH_WRITE_STB_MSB = 3; //FLASH_CONTROL_REG:FLASH_WRITE_STB + localparam FLASH_WRITE_STB = 3; //FLASH_CONTROL_REG:FLASH_WRITE_STB + localparam FLASH_ERASE_STB_SIZE = 1; //FLASH_CONTROL_REG:FLASH_ERASE_STB + localparam FLASH_ERASE_STB_MSB = 4; //FLASH_CONTROL_REG:FLASH_ERASE_STB + localparam FLASH_ERASE_STB = 4; //FLASH_CONTROL_REG:FLASH_ERASE_STB + localparam FLASH_ERASE_SECTOR_SIZE = 3; //FLASH_CONTROL_REG:FLASH_ERASE_SECTOR + localparam FLASH_ERASE_SECTOR_MSB = 7; //FLASH_CONTROL_REG:FLASH_ERASE_SECTOR + localparam FLASH_ERASE_SECTOR = 5; //FLASH_CONTROL_REG:FLASH_ERASE_SECTOR + localparam CLEAR_FLASH_READ_ERROR_STB_SIZE = 1; //FLASH_CONTROL_REG:CLEAR_FLASH_READ_ERROR_STB + localparam CLEAR_FLASH_READ_ERROR_STB_MSB = 8; //FLASH_CONTROL_REG:CLEAR_FLASH_READ_ERROR_STB + localparam CLEAR_FLASH_READ_ERROR_STB = 8; //FLASH_CONTROL_REG:CLEAR_FLASH_READ_ERROR_STB + localparam CLEAR_FLASH_WRITE_ERROR_STB_SIZE = 1; //FLASH_CONTROL_REG:CLEAR_FLASH_WRITE_ERROR_STB + localparam CLEAR_FLASH_WRITE_ERROR_STB_MSB = 9; //FLASH_CONTROL_REG:CLEAR_FLASH_WRITE_ERROR_STB + localparam CLEAR_FLASH_WRITE_ERROR_STB = 9; //FLASH_CONTROL_REG:CLEAR_FLASH_WRITE_ERROR_STB + localparam CLEAR_FLASH_ERASE_ERROR_STB_SIZE = 1; //FLASH_CONTROL_REG:CLEAR_FLASH_ERASE_ERROR_STB + localparam CLEAR_FLASH_ERASE_ERROR_STB_MSB = 10; //FLASH_CONTROL_REG:CLEAR_FLASH_ERASE_ERROR_STB + localparam CLEAR_FLASH_ERASE_ERROR_STB = 10; //FLASH_CONTROL_REG:CLEAR_FLASH_ERASE_ERROR_STB + + // FLASH_ADDR_REG Register (from reconfig_engine.v) + localparam FLASH_ADDR_REG = 'h8; // Register Offset + localparam FLASH_ADDR_REG_SIZE = 32; // register width in bits + localparam FLASH_ADDR_REG_MASK = 32'h1FFFF; + localparam FLASH_ADDR_SIZE = 17; //FLASH_ADDR_REG:FLASH_ADDR + localparam FLASH_ADDR_MSB = 16; //FLASH_ADDR_REG:FLASH_ADDR + localparam FLASH_ADDR = 0; //FLASH_ADDR_REG:FLASH_ADDR + + // FLASH_WRITE_DATA_REG Register (from reconfig_engine.v) + localparam FLASH_WRITE_DATA_REG = 'hC; // Register Offset + localparam FLASH_WRITE_DATA_REG_SIZE = 32; // register width in bits + localparam FLASH_WRITE_DATA_REG_MASK = 32'hFFFFFFFF; + localparam FLASH_WRITE_DATA_SIZE = 32; //FLASH_WRITE_DATA_REG:FLASH_WRITE_DATA + localparam FLASH_WRITE_DATA_MSB = 31; //FLASH_WRITE_DATA_REG:FLASH_WRITE_DATA + localparam FLASH_WRITE_DATA = 0; //FLASH_WRITE_DATA_REG:FLASH_WRITE_DATA + + // FLASH_READ_DATA_REG Register (from reconfig_engine.v) + localparam FLASH_READ_DATA_REG = 'h10; // Register Offset + localparam FLASH_READ_DATA_REG_SIZE = 32; // register width in bits + localparam FLASH_READ_DATA_REG_MASK = 32'hFFFFFFFF; + localparam FLASH_READ_DATA_SIZE = 32; //FLASH_READ_DATA_REG:FLASH_READ_DATA + localparam FLASH_READ_DATA_MSB = 31; //FLASH_READ_DATA_REG:FLASH_READ_DATA + localparam FLASH_READ_DATA = 0; //FLASH_READ_DATA_REG:FLASH_READ_DATA + + // FLASH_CFM0_START_ADDR_REG Register (from reconfig_engine.v) + localparam FLASH_CFM0_START_ADDR_REG = 'h14; // Register Offset + localparam FLASH_CFM0_START_ADDR_REG_SIZE = 32; // register width in bits + localparam FLASH_CFM0_START_ADDR_REG_MASK = 32'hFFFFFFFF; + localparam FLASH_CFM0_START_ADDR_SIZE = 32; //FLASH_CFM0_START_ADDR_REG:FLASH_CFM0_START_ADDR + localparam FLASH_CFM0_START_ADDR_MSB = 31; //FLASH_CFM0_START_ADDR_REG:FLASH_CFM0_START_ADDR + localparam FLASH_CFM0_START_ADDR = 0; //FLASH_CFM0_START_ADDR_REG:FLASH_CFM0_START_ADDR + + // FLASH_CFM0_END_ADDR_REG Register (from reconfig_engine.v) + localparam FLASH_CFM0_END_ADDR_REG = 'h18; // Register Offset + localparam FLASH_CFM0_END_ADDR_REG_SIZE = 32; // register width in bits + localparam FLASH_CFM0_END_ADDR_REG_MASK = 32'hFFFFFFFF; + localparam FLASH_CFM0_END_ADDR_SIZE = 32; //FLASH_CFM0_END_ADDR_REG:FLASH_CFM0_END_ADDR + localparam FLASH_CFM0_END_ADDR_MSB = 31; //FLASH_CFM0_END_ADDR_REG:FLASH_CFM0_END_ADDR + localparam FLASH_CFM0_END_ADDR = 0; //FLASH_CFM0_END_ADDR_REG:FLASH_CFM0_END_ADDR diff --git a/fpga/usrp3/top/x400/cpld/regmap/spi_regmap_utils.vh b/fpga/usrp3/top/x400/cpld/regmap/spi_regmap_utils.vh new file mode 100644 index 000000000..bf25b6fd3 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/regmap/spi_regmap_utils.vh @@ -0,0 +1,69 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: spi_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // RX_DATA_LOW : 0x0 (ctrlport_to_spi.v) + // RX_DATA_HIGH : 0x4 (ctrlport_to_spi.v) + // TX_DATA_LOW : 0x8 (ctrlport_to_spi.v) + // TX_DATA_HIGH : 0xC (ctrlport_to_spi.v) + // CONTROL : 0x10 (ctrlport_to_spi.v) + // CLOCK_DIVIDER : 0x14 (ctrlport_to_spi.v) + // SLAVE_SELECT : 0x18 (ctrlport_to_spi.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group SPI_REGS +//=============================================================================== + + // RX_DATA_LOW Register (from ctrlport_to_spi.v) + localparam RX_DATA_LOW = 'h0; // Register Offset + localparam RX_DATA_LOW_SIZE = 32; // register width in bits + localparam RX_DATA_LOW_MASK = 32'h0; + + // RX_DATA_HIGH Register (from ctrlport_to_spi.v) + localparam RX_DATA_HIGH = 'h4; // Register Offset + localparam RX_DATA_HIGH_SIZE = 32; // register width in bits + localparam RX_DATA_HIGH_MASK = 32'h0; + + // TX_DATA_LOW Register (from ctrlport_to_spi.v) + localparam TX_DATA_LOW = 'h8; // Register Offset + localparam TX_DATA_LOW_SIZE = 32; // register width in bits + localparam TX_DATA_LOW_MASK = 32'h0; + + // TX_DATA_HIGH Register (from ctrlport_to_spi.v) + localparam TX_DATA_HIGH = 'hC; // Register Offset + localparam TX_DATA_HIGH_SIZE = 32; // register width in bits + localparam TX_DATA_HIGH_MASK = 32'h0; + + // CONTROL Register (from ctrlport_to_spi.v) + localparam CONTROL = 'h10; // Register Offset + localparam CONTROL_SIZE = 32; // register width in bits + localparam CONTROL_MASK = 32'h0; + + // CLOCK_DIVIDER Register (from ctrlport_to_spi.v) + localparam CLOCK_DIVIDER = 'h14; // Register Offset + localparam CLOCK_DIVIDER_SIZE = 8; // register width in bits + localparam CLOCK_DIVIDER_MASK = 8'hFF; + localparam DIVIDER_SIZE = 8; //CLOCK_DIVIDER:Divider + localparam DIVIDER_MSB = 7; //CLOCK_DIVIDER:Divider + localparam DIVIDER = 0; //CLOCK_DIVIDER:Divider + + // SLAVE_SELECT Register (from ctrlport_to_spi.v) + localparam SLAVE_SELECT = 'h18; // Register Offset + localparam SLAVE_SELECT_SIZE = 16; // register width in bits + localparam SLAVE_SELECT_MASK = 16'hFFFF; + localparam SS_SIZE = 16; //SLAVE_SELECT:SS + localparam SS_MSB = 15; //SLAVE_SELECT:SS + localparam SS = 0; //SLAVE_SELECT:SS |