diff options
Diffstat (limited to 'fpga/usrp3/top/x400/Makefile')
| -rw-r--r-- | fpga/usrp3/top/x400/Makefile | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile index ad519be73..5098e58b1 100644 --- a/fpga/usrp3/top/x400/Makefile +++ b/fpga/usrp3/top/x400/Makefile @@ -43,22 +43,24 @@ QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disa # Target specific variables X410_IP: DEFS += $(QSFP0_10GBE) RFBW_100M=1 -X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 -X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 -X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 -X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 -X410_CG_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 -X410_CG_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 -X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 -X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 -X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 -X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 -X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 - -# DRAM IP inclusion. Set to 1 to include DRAM IP in design, 0 to exclude it. +X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0 +X410_CG_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_CG_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0 +X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0 +X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0 + +# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to +# exclude it. Note that some targets exclude it regardless of this setting. DRAM ?= 1 -DEFS += $(OPTIONS) ENABLE_DRAM=$(DRAM) +DEFS += $(OPTIONS) # Defaults specific to the various targets: X410_100_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex) |