diff options
Diffstat (limited to 'fpga/usrp3/top/x300/timing.ucf')
| -rw-r--r-- | fpga/usrp3/top/x300/timing.ucf | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf index b638b2c99..c31a525f7 100644 --- a/fpga/usrp3/top/x300/timing.ucf +++ b/fpga/usrp3/top/x300/timing.ucf @@ -1,28 +1,32 @@ NET "FPGA_CLK_p" TNM_NET = "FPGA_CLK_p"; -TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50 %; +TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50%; NET "FPGA_CLK_n" TNM_NET = "FPGA_CLK_n"; -TIMESPEC "TS_FPGA_CLK_n" = PERIOD "FPGA_CLK_n" 5000 ps HIGH 50 %; +TIMESPEC TS_FPGA_CLK_n = PERIOD "FPGA_CLK_n" TS_FPGA_CLK_p HIGH 50%; -NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK"; -TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %; +NET "FPGA_REFCLK_10MHz_p" TNM_NET = "FPGA_REFCLK_10MHz_p"; +TIMESPEC "TS_FPGA_REFCLK_10MHz_p" = PERIOD "FPGA_REFCLK_10MHz_p" 100 ns HIGH 50%; -#NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P"; -#TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 8333 ps HIGH 50 %; +NET "FPGA_REFCLK_10MHz_n" TNM_NET = "FPGA_REFCLK_10MHz_n"; +TIMESPEC TS_FPGA_REFCLK_10MHz_n = PERIOD "FPGA_REFCLK_10MHz_n" TS_FPGA_REFCLK_10MHz_p HIGH 50%; -#NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P"; -#TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 8333 ps HIGH 50 %; +NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK"; +TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %; NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P"; TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 5000 ps HIGH 50 %; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING; +NET "DB0_ADC_DCLK_N" TNM_NET = DB0_ADC_DCLK_N; +TIMESPEC TS_DB0_ADC_DCLK_N = PERIOD "DB0_ADC_DCLK_N" TS_DB0_ADC_DCLK_P HIGH 50%; NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P"; TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 5000 ps HIGH 50 %; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING; -OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING; +#OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING; +NET "DB1_ADC_DCLK_N" TNM_NET = DB1_ADC_DCLK_N; +TIMESPEC TS_DB1_ADC_DCLK_N = PERIOD "DB1_ADC_DCLK_N" TS_DB1_ADC_DCLK_P HIGH 50%; NET "bus_clk" TNM = bus_clk_grp; NET "ioport2_clk" TNM = ioport2_clk_grp; @@ -38,4 +42,4 @@ TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_cl # to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent, # lock the locations of the MMCM and BUFG to generate radio_clk. INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0; -INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8;
\ No newline at end of file +INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8; |