diff options
Diffstat (limited to 'fpga/usrp3/top/x300/sim/sim_vfifo_tester/files.prj')
| -rw-r--r-- | fpga/usrp3/top/x300/sim/sim_vfifo_tester/files.prj | 267 |
1 files changed, 0 insertions, 267 deletions
diff --git a/fpga/usrp3/top/x300/sim/sim_vfifo_tester/files.prj b/fpga/usrp3/top/x300/sim/sim_vfifo_tester/files.prj deleted file mode 100644 index 2d927c1f3..000000000 --- a/fpga/usrp3/top/x300/sim/sim_vfifo_tester/files.prj +++ /dev/null @@ -1,267 +0,0 @@ - ---verilog work ../../coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/ddr2_ddr3_chipscope.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/mig_7series_v1_8_chk_win.v ---verilog work ../../coregen/ddr3_interface/example_design/rtl/example_top.v -verilog work ../../coregen/ddr3_32bit/example_design/sim/ddr3_model.v -d x4Gb -d sg125 -d x16 -i ./ - -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_arb_select.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_common.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_bank_state.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_col_mach.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_mc.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_rank_common.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_top.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v -verilog work ../../coregen/ddr3_32bit/user_design/rtl/ddr3_32bit.v -verilog work $XILINX/verilog/src/glbl.v --- verilog work ./sim_tb_top.v --- verilog work ./wiredly.v --- verilog work ./ddr3_model.v -d x4Gb -d sg125 -d x16 -i ./ -verilog work ../../../../lib/control/axi_test_vfifo.v -verilog work ../x300_tb.v ---verilog work ../ddr3.v -d den4096Mb -d sg125 -d x16 -i ./ - -verilog work ../../x300.v -d DDR3 -verilog work ../../x300_core.v -verilog work ../../bus_int.v -verilog work ../../capture_ddrlvds.v -verilog work ../../gen_ddrlvds.v -verilog work ../../gige_phy.v -verilog work ../../radio.v -verilog work ../../soft_ctrl.v --- Assorted coregen -verilog work ../../coregen/bootram.v -verilog work ../../coregen/radio_clk_gen.v -verilog work ../../coregen/bus_clk_gen.v -verilog work ../../coregen/axi64_8k_2clk_fifo.v --- CHIPSCOPE -verilog work ../../coregen/chipscope_icon.v -verilog work ../../coregen/chipscope_ila.v --- 1 GE SFP -verilog work ../../coregen/gige_sfp.v -d GLBL -verilog work ../../coregen/gige_sfp/example_design/gige_sfp_block.v -verilog work ../../coregen/gige_sfp/example_design/gige_sfp_example_design.v -verilog work ../../coregen/gige_sfp/example_design/gige_sfp_mod.v -verilog work ../../coregen/gige_sfp/example_design/gige_sfp_reset_sync.v -verilog work ../../coregen/gige_sfp/example_design/gige_sfp_sync_block.v -verilog work ../../coregen/gige_sfp/example_design/gige_sfp_tx_elastic_buffer.v -verilog work ../../coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v -verilog work ../../coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v -verilog work ../../coregen/gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v -verilog work ../../coregen/gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v -verilog work ../../coregen/gige_sfp/example_design/transceiver/gige_sfp_transceiver.v -verilog work ../../coregen/gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v --- AXI Crossbar -verilog work ../../coregen/axi_intercon_4x64_128_sim.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/axi_interconnect_v1_06_a.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_a_axi3_conv.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_addr_arbiter_sasd.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_addr_arbiter.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_addr_decoder.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_a_downsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_arbiter_resp.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_a_upsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi3_conv.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_fifo.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_clock_converter.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_register_slice.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_reg_srl_fifo.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_crossbar.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_sample_cycle_ratio.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_srl_fifo.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axic_sync_clock_converter.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_data_fifo.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_downsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_interconnect.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axilite_conv.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_protocol_converter.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_register_slice.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_axi_upsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_b_downsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_and.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_latch_and.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_latch_or.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry_or.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_carry.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_command_fifo.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_mask_static.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_mask.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel_mask_static.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel_mask.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel_static.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_sel.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator_static.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_comparator.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_converter_bank.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_crossbar_sasd.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_crossbar.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_data_fifo_bank.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_decerr_slave.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_fifo_gen.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_mux_enc.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_mux.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_ndeep_srl.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_nto1_mux.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_protocol_conv_bank.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_r_axi3_conv.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_r_downsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_register_slice_bank.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_r_upsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_si_transactor.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_splitter.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_w_axi3_conv.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_wdata_mux.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_wdata_router.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_w_downsizer.v -verilog work ../../coregen/axi_intercon_4x64_128/hdl/verilog/ict106_w_upsizer.v --- AXI VFIFO -verilog work ../../coregen/axi_vfifo_64_0x0.v -verilog work ../../coregen/axi_vfifo_64_0x2000000.v --- lib/timing -verilog work ../../../../lib/timing/time_64bit.v -verilog work ../../../../lib/timing/time_compare.v -verilog work ../../../../lib/timing/timekeeper.v --- 1GE MAC -verilog work ../../../../lib/simple_gemac/address_filter_promisc.v -verilog work ../../../../lib/simple_gemac/address_filter.v -verilog work ../../../../lib/simple_gemac/axi64_to_ll8.v -verilog work ../../../../lib/simple_gemac/crc.v -verilog work ../../../../lib/simple_gemac/delay_line.v -verilog work ../../../../lib/simple_gemac/flow_ctrl_rx.v -verilog work ../../../../lib/simple_gemac/flow_ctrl_tx.v -verilog work ../../../../lib/simple_gemac/ll8_to_axi64.v -verilog work ../../../../lib/simple_gemac/ll8_to_txmac.v -verilog work ../../../../lib/simple_gemac/rxmac_to_ll8.v -verilog work ../../../../lib/simple_gemac/simple_gemac_rx.v -verilog work ../../../../lib/simple_gemac/simple_gemac_tb.v -verilog work ../../../../lib/simple_gemac/simple_gemac_tx.v -verilog work ../../../../lib/simple_gemac/simple_gemac.v -verilog work ../../../../lib/simple_gemac/simple_gemac_wrapper.v --- lib/control -verilog work ../../../../lib/control/axi_crossbar.v -verilog work ../../../../lib/control/arb_qualify_master.v -verilog work ../../../../lib/control/axi_fifo_header.v -verilog work ../../../../lib/control/axi_forwarding_cam.v -verilog work ../../../../lib/control/axi_slave_mux.v -verilog work ../../../../lib/control/gpio_atr.v -verilog work ../../../../lib/control/radio_ctrl_proc.v -verilog work ../../../../lib/control/ram_2port.v -verilog work ../../../../lib/control/reset_sync.v -verilog work ../../../../lib/control/setting_reg.v -verilog work ../../../../lib/control/simple_i2c_core.v -verilog work ../../../../lib/control/simple_spi_core.v --- lib/packet_proc -verilog work ../../../../lib/packet_proc/compressed_vita_to_vrlp.v -verilog work ../../../../lib/packet_proc/eth_dispatch.v -verilog work ../../../../lib/packet_proc/eth_interface.v -verilog work ../../../../lib/packet_proc/ip_hdr_checksum.v -verilog work ../../../../lib/packet_proc/vita_eth_framer.v -verilog work ../../../../lib/packet_proc/vrlp_eth_framer.v -verilog work ../../../../lib/packet_proc/vrlp_to_compressed_vita.v --- lib/fifo -verilog work ../../../../lib/fifo/axi_mux4.v -verilog work ../../../../lib/fifo/axi_demux4.v -verilog work ../../../../lib/fifo/axi_fifo.v -verilog work ../../../../lib/fifo/axi_fifo_short.v -verilog work ../../../../lib/fifo/shortfifo.v --- lib/wishbone -verilog work ../../../../lib/wishbone/axi_stream_to_wb.v -verilog work ../../../../lib/wishbone/i2c_master_byte_ctrl.v -verilog work ../../../../lib/wishbone/i2c_master_bit_ctrl.v -verilog work ../../../../lib/wishbone/i2c_master_defines.v -verilog work ../../../../lib/wishbone/i2c_master_top.v -verilog work ../../../../lib/wishbone/settings_bus.v -verilog work ../../../../lib/wishbone/simple_uart_rx.v -verilog work ../../../../lib/wishbone/simple_uart_tx.v -verilog work ../../../../lib/wishbone/simple_uart.v -verilog work ../../../../lib/wishbone/wb_1master.v --- lib/zpu -vhdl work ../../../../lib/zpu/zpu_top_pkg.vhd -vhdl work ../../../../lib/zpu/zpu_wb_top.vhd -vhdl work ../../../../lib/zpu/core/zpu_config.vhd -vhdl work ../../../../lib/zpu/core/zpu_core.vhd -vhdl work ../../../../lib/zpu/core/zpupkg.vhd -vhdl work ../../../../lib/zpu/wishbone/wishbone_pkg.vhd -vhdl work ../../../../lib/zpu/wishbone/zpu_system.vhd -vhdl work ../../../../lib/zpu/wishbone/zpu_wb_bridge.vhd - - |