diff options
Diffstat (limited to 'fpga/usrp3/top/n3xx')
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_image_core.v | 951 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v | 1103 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh | 21 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_bist_image_core.v | 1247 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v | 1685 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh | 21 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_bist_image_core.v | 1117 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v | 1413 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh | 21 |
9 files changed, 3997 insertions, 3582 deletions
diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.v b/fpga/usrp3/top/n3xx/n300_bist_image_core.v index 31d4eeb86..77c3429dd 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_image_core.v +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.v @@ -1,19 +1,32 @@ // -// Copyright 2019 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // - // Module: rfnoc_image_core (for n300) -// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) -// Re-running that tool will overwrite this file! -// File generated on: 2019-11-08T15:58:13.938765 -// Source: ./n3xx/n300_bist_image_core.yml -// Source SHA256: 3bed6bab7b614594eb5ea4e49b34a6e9560b10ff4622c1033c206bec1f4a0f2c +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:04.740210 +// Source: n300_bist_image_core.yml +// Source SHA256: 209edc7c95f0a9fd8b96b6d10a40849f3ee84e5fc85a37696cc7510cd74c4af6 +// + +`default_nettype none + module rfnoc_image_core #( - parameter [15:0] PROTOVER = {8'd1, 8'd0} -)( + parameter CHDR_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( // Clocks input wire chdr_aclk, input wire ctrl_aclk, @@ -21,113 +34,118 @@ module rfnoc_image_core #( input wire radio_clk, input wire dram_clk, // Basic - input wire [15:0] device_id, -//// IO ports ////////////////////////////////// -// ctrlport_radio0 - output wire [ 1-1:0] m_ctrlport_radio0_req_wr, - output wire [ 1-1:0] m_ctrlport_radio0_req_rd, - output wire [ 20-1:0] m_ctrlport_radio0_req_addr, - output wire [ 32-1:0] m_ctrlport_radio0_req_data, - output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio0_req_time, - input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio0_resp_status, - input wire [ 32-1:0] m_ctrlport_radio0_resp_data, -// time_keeper - input wire [ 64-1:0] radio_time, -// x300_radio0 - input wire [ 64-1:0] radio_rx_data_radio0, - input wire [ 2-1:0] radio_rx_stb_radio0, - output wire [ 2-1:0] radio_rx_running_radio0, - output wire [ 64-1:0] radio_tx_data_radio0, - input wire [ 2-1:0] radio_tx_stb_radio0, - output wire [ 2-1:0] radio_tx_running_radio0, -// dram - input wire [ 1-1:0] axi_rst, - output wire [ 4-1:0] m_axi_awid, - output wire [128-1:0] m_axi_awaddr, - output wire [ 32-1:0] m_axi_awlen, - output wire [ 12-1:0] m_axi_awsize, - output wire [ 8-1:0] m_axi_awburst, - output wire [ 4-1:0] m_axi_awlock, - output wire [ 16-1:0] m_axi_awcache, - output wire [ 12-1:0] m_axi_awprot, - output wire [ 16-1:0] m_axi_awqos, - output wire [ 16-1:0] m_axi_awregion, - output wire [ 4-1:0] m_axi_awuser, - output wire [ 4-1:0] m_axi_awvalid, - input wire [ 4-1:0] m_axi_awready, - output wire [256-1:0] m_axi_wdata, - output wire [ 32-1:0] m_axi_wstrb, - output wire [ 4-1:0] m_axi_wlast, - output wire [ 4-1:0] m_axi_wuser, - output wire [ 4-1:0] m_axi_wvalid, - input wire [ 4-1:0] m_axi_wready, - input wire [ 4-1:0] m_axi_bid, - input wire [ 8-1:0] m_axi_bresp, - input wire [ 4-1:0] m_axi_buser, - input wire [ 4-1:0] m_axi_bvalid, - output wire [ 4-1:0] m_axi_bready, - output wire [ 4-1:0] m_axi_arid, - output wire [128-1:0] m_axi_araddr, - output wire [ 32-1:0] m_axi_arlen, - output wire [ 12-1:0] m_axi_arsize, - output wire [ 8-1:0] m_axi_arburst, - output wire [ 4-1:0] m_axi_arlock, - output wire [ 16-1:0] m_axi_arcache, - output wire [ 12-1:0] m_axi_arprot, - output wire [ 16-1:0] m_axi_arqos, - output wire [ 16-1:0] m_axi_arregion, - output wire [ 4-1:0] m_axi_aruser, - output wire [ 4-1:0] m_axi_arvalid, - input wire [ 4-1:0] m_axi_arready, - input wire [ 4-1:0] m_axi_rid, - input wire [256-1:0] m_axi_rdata, - input wire [ 8-1:0] m_axi_rresp, - input wire [ 4-1:0] m_axi_rlast, - input wire [ 4-1:0] m_axi_ruser, - input wire [ 4-1:0] m_axi_rvalid, - output wire [ 4-1:0] m_axi_rready, - // Transport 0 (eth0 1G) - input wire [64-1:0] s_eth0_tdata, - input wire s_eth0_tlast, - input wire s_eth0_tvalid, - output wire s_eth0_tready, - output wire [64-1:0] m_eth0_tdata, - output wire m_eth0_tlast, - output wire m_eth0_tvalid, - input wire m_eth0_tready, - // Transport 1 (eth1 10G) - input wire [64-1:0] s_eth1_tdata, - input wire s_eth1_tlast, - input wire s_eth1_tvalid, - output wire s_eth1_tready, - output wire [64-1:0] m_eth1_tdata, - output wire m_eth1_tlast, - output wire m_eth1_tvalid, - input wire m_eth1_tready, - // Transport 2 (dma dma) - input wire [64-1:0] s_dma_tdata, - input wire s_dma_tlast, - input wire s_dma_tvalid, - output wire s_dma_tready, - output wire [64-1:0] m_dma_tdata, - output wire m_dma_tlast, - output wire m_dma_tvalid, - input wire m_dma_tready + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // time_keeper + input wire [ 63:0] radio_time, + // x300_radio0 + input wire [ 63:0] radio_rx_data_radio0, + input wire [ 1:0] radio_rx_stb_radio0, + output wire [ 1:0] radio_rx_running_radio0, + output wire [ 63:0] radio_tx_data_radio0, + input wire [ 1:0] radio_tx_stb_radio0, + output wire [ 1:0] radio_tx_running_radio0, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [CHDR_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [CHDR_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [CHDR_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [CHDR_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma) + input wire [CHDR_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [CHDR_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready ); - localparam CHDR_W = 64; - localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // CHDR Crossbar - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; @@ -176,12 +194,12 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), - .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tdata ({ep5_to_xb_tdata , ep4_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep5_to_xb_tlast , ep4_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }), .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), - .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tdata ({xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }), .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), @@ -190,9 +208,18 @@ module rfnoc_image_core #( .ext_rtcfg_ack () ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Stream Endpoints - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 16384; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; @@ -202,8 +229,8 @@ module rfnoc_image_core #( wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; - wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; - wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; @@ -216,23 +243,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep0_tdata ), - .s_axis_chdr_tlast (xb_to_ep0_tlast ), - .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), - .s_axis_chdr_tready (xb_to_ep0_tready ), - .m_axis_chdr_tdata (ep0_to_xb_tdata ), - .m_axis_chdr_tlast (ep0_to_xb_tlast ), - .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), - .m_axis_chdr_tready (ep0_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), @@ -241,20 +268,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), - .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), - .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 16384; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; @@ -263,8 +298,8 @@ module rfnoc_image_core #( wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; - wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; - wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; @@ -277,23 +312,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep1_tdata ), - .s_axis_chdr_tlast (xb_to_ep1_tlast ), - .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), - .s_axis_chdr_tready (xb_to_ep1_tready ), - .m_axis_chdr_tdata (ep1_to_xb_tdata ), - .m_axis_chdr_tlast (ep1_to_xb_tlast ), - .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), - .m_axis_chdr_tready (ep1_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), @@ -302,20 +337,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), - .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), - .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP4 = 16384; + localparam INGRESS_BUFF_SIZE_EP4 = + REQ_BUFF_SIZE_EP4 == 0 ? 5 : + REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP4); + wire [CHDR_W-1:0] m_ep4_out0_tdata; wire m_ep4_out0_tlast; wire m_ep4_out0_tvalid; @@ -324,8 +367,8 @@ module rfnoc_image_core #( wire s_ep4_in0_tlast; wire s_ep4_in0_tvalid; wire s_ep4_in0_tready; - wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; - wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; + wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; @@ -338,23 +381,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep4_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep4_tdata ), - .s_axis_chdr_tlast (xb_to_ep4_tlast ), - .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), - .s_axis_chdr_tready (xb_to_ep4_tready ), - .m_axis_chdr_tdata (ep4_to_xb_tdata ), - .m_axis_chdr_tlast (ep4_to_xb_tlast ), - .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), - .m_axis_chdr_tready (ep4_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep4_tdata), + .s_axis_chdr_tlast (xb_to_ep4_tlast), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid), + .s_axis_chdr_tready (xb_to_ep4_tready), + .m_axis_chdr_tdata (ep4_to_xb_tdata), + .m_axis_chdr_tlast (ep4_to_xb_tlast), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid), + .m_axis_chdr_tready (ep4_to_xb_tready), .s_axis_data_tdata ({s_ep4_in0_tdata}), .s_axis_data_tlast ({s_ep4_in0_tlast}), .s_axis_data_tvalid ({s_ep4_in0_tvalid}), @@ -363,20 +406,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep4_out0_tlast}), .m_axis_data_tvalid ({m_ep4_out0_tvalid}), .m_axis_data_tready ({m_ep4_out0_tready}), - .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), .s_axis_ctrl_tready (s_ep4_ctrl_tready), - .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), .m_axis_ctrl_tready (m_ep4_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP5 = 16384; + localparam INGRESS_BUFF_SIZE_EP5 = + REQ_BUFF_SIZE_EP5 == 0 ? 5 : + REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP5); + wire [CHDR_W-1:0] m_ep5_out0_tdata; wire m_ep5_out0_tlast; wire m_ep5_out0_tvalid; @@ -385,8 +436,8 @@ module rfnoc_image_core #( wire s_ep5_in0_tlast; wire s_ep5_in0_tvalid; wire s_ep5_in0_tready; - wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; - wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; + wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; @@ -399,23 +450,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep5_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep5_tdata ), - .s_axis_chdr_tlast (xb_to_ep5_tlast ), - .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), - .s_axis_chdr_tready (xb_to_ep5_tready ), - .m_axis_chdr_tdata (ep5_to_xb_tdata ), - .m_axis_chdr_tlast (ep5_to_xb_tlast ), - .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), - .m_axis_chdr_tready (ep5_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep5_tdata), + .s_axis_chdr_tlast (xb_to_ep5_tlast), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid), + .s_axis_chdr_tready (xb_to_ep5_tready), + .m_axis_chdr_tdata (ep5_to_xb_tdata), + .m_axis_chdr_tlast (ep5_to_xb_tlast), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid), + .m_axis_chdr_tready (ep5_to_xb_tready), .s_axis_data_tdata ({s_ep5_in0_tdata}), .s_axis_data_tlast ({s_ep5_in0_tlast}), .s_axis_data_tvalid ({s_ep5_in0_tvalid}), @@ -424,38 +475,37 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep5_out0_tlast}), .m_axis_data_tvalid ({m_ep5_out0_tvalid}), .m_axis_data_tready ({m_ep5_out0_tready}), - .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), .s_axis_ctrl_tready (s_ep5_ctrl_tready), - .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), .m_axis_ctrl_tready (m_ep5_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Control Crossbar - // ---------------------------------------------------- - - wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; - wire m_core_ctrl_tlast , s_core_ctrl_tlast ; - wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; - wire m_core_ctrl_tready, s_core_ctrl_tready; - wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; - wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; - wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; - wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; - wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; - wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; - wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; - wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata, s_fifo0_ctrl_tdata; + wire m_fifo0_ctrl_tlast, s_fifo0_ctrl_tlast; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), @@ -479,9 +529,11 @@ module rfnoc_image_core #( .deadlock_detected() ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // RFNoC Core Kernel - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( @@ -506,12 +558,12 @@ module rfnoc_image_core #( .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), - .s_axis_ctrl_tdata (s_core_ctrl_tdata ), - .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), - .m_axis_ctrl_tdata (m_core_ctrl_tdata ), - .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), @@ -519,13 +571,15 @@ module rfnoc_image_core #( .rfnoc_core_status (rfnoc_core_status) ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Blocks - // ---------------------------------------------------- + //--------------------------------------------------------------------------- - // ---------------------------------------------------- + //----------------------------------- // radio0 - // ---------------------------------------------------- + //----------------------------------- + wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; @@ -536,79 +590,77 @@ module rfnoc_image_core #( wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tready, m_radio0_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio0_m_ctrlport_req_wr; - wire [ 1-1:0] radio0_m_ctrlport_req_rd; - wire [ 20-1:0] radio0_m_ctrlport_req_addr; - wire [ 32-1:0] radio0_m_ctrlport_req_data; - wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio0_m_ctrlport_req_has_time; - wire [ 64-1:0] radio0_m_ctrlport_req_time; - wire [ 1-1:0] radio0_m_ctrlport_resp_ack; - wire [ 2-1:0] radio0_m_ctrlport_resp_status; - wire [ 32-1:0] radio0_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio0_radio_time; - // x300_radio - wire [ 64-1:0] radio0_radio_rx_data; - wire [ 2-1:0] radio0_radio_rx_stb; - wire [ 2-1:0] radio0_radio_rx_running; - wire [ 64-1:0] radio0_radio_tx_data; - wire [ 2-1:0] radio0_radio_tx_stb; - wire [ 2-1:0] radio0_radio_tx_running; + // ctrl_port + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio0_radio_time; + // x300_radio + wire [ 63:0] radio0_radio_rx_data; + wire [ 1:0] radio0_radio_rx_stb; + wire [ 1:0] radio0_radio_rx_running; + wire [ 63:0] radio0_radio_tx_data; + wire [ 1:0] radio0_radio_tx_stb; + wire [ 1:0] radio0_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(2), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MTU(MTU) + .THIS_PORTID (2), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MTU (MTU) ) b_radio0_0 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio0_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), - .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), - - .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio0_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), - .radio_time(radio0_radio_time), - .radio_rx_data(radio0_radio_rx_data), - .radio_rx_stb(radio0_radio_rx_stb), - .radio_rx_running(radio0_radio_rx_running), - .radio_tx_data(radio0_radio_tx_data), - .radio_tx_stb(radio0_radio_tx_stb), - .radio_tx_running(radio0_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // fifo0 - // ---------------------------------------------------- + //----------------------------------- + wire fifo0_mem_clk; wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; @@ -619,182 +671,181 @@ module rfnoc_image_core #( wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; - // axi_ram - wire [ 1-1:0] fifo0_axi_rst; - wire [ 4-1:0] fifo0_m_axi_awid; - wire [128-1:0] fifo0_m_axi_awaddr; - wire [ 32-1:0] fifo0_m_axi_awlen; - wire [ 12-1:0] fifo0_m_axi_awsize; - wire [ 8-1:0] fifo0_m_axi_awburst; - wire [ 4-1:0] fifo0_m_axi_awlock; - wire [ 16-1:0] fifo0_m_axi_awcache; - wire [ 12-1:0] fifo0_m_axi_awprot; - wire [ 16-1:0] fifo0_m_axi_awqos; - wire [ 16-1:0] fifo0_m_axi_awregion; - wire [ 4-1:0] fifo0_m_axi_awuser; - wire [ 4-1:0] fifo0_m_axi_awvalid; - wire [ 4-1:0] fifo0_m_axi_awready; - wire [256-1:0] fifo0_m_axi_wdata; - wire [ 32-1:0] fifo0_m_axi_wstrb; - wire [ 4-1:0] fifo0_m_axi_wlast; - wire [ 4-1:0] fifo0_m_axi_wuser; - wire [ 4-1:0] fifo0_m_axi_wvalid; - wire [ 4-1:0] fifo0_m_axi_wready; - wire [ 4-1:0] fifo0_m_axi_bid; - wire [ 8-1:0] fifo0_m_axi_bresp; - wire [ 4-1:0] fifo0_m_axi_buser; - wire [ 4-1:0] fifo0_m_axi_bvalid; - wire [ 4-1:0] fifo0_m_axi_bready; - wire [ 4-1:0] fifo0_m_axi_arid; - wire [128-1:0] fifo0_m_axi_araddr; - wire [ 32-1:0] fifo0_m_axi_arlen; - wire [ 12-1:0] fifo0_m_axi_arsize; - wire [ 8-1:0] fifo0_m_axi_arburst; - wire [ 4-1:0] fifo0_m_axi_arlock; - wire [ 16-1:0] fifo0_m_axi_arcache; - wire [ 12-1:0] fifo0_m_axi_arprot; - wire [ 16-1:0] fifo0_m_axi_arqos; - wire [ 16-1:0] fifo0_m_axi_arregion; - wire [ 4-1:0] fifo0_m_axi_aruser; - wire [ 4-1:0] fifo0_m_axi_arvalid; - wire [ 4-1:0] fifo0_m_axi_arready; - wire [ 4-1:0] fifo0_m_axi_rid; - wire [256-1:0] fifo0_m_axi_rdata; - wire [ 8-1:0] fifo0_m_axi_rresp; - wire [ 4-1:0] fifo0_m_axi_rlast; - wire [ 4-1:0] fifo0_m_axi_ruser; - wire [ 4-1:0] fifo0_m_axi_rvalid; - wire [ 4-1:0] fifo0_m_axi_rready; + // axi_ram + wire [ 0:0] fifo0_axi_rst; + wire [ 3:0] fifo0_m_axi_awid; + wire [ 127:0] fifo0_m_axi_awaddr; + wire [ 31:0] fifo0_m_axi_awlen; + wire [ 11:0] fifo0_m_axi_awsize; + wire [ 7:0] fifo0_m_axi_awburst; + wire [ 3:0] fifo0_m_axi_awlock; + wire [ 15:0] fifo0_m_axi_awcache; + wire [ 11:0] fifo0_m_axi_awprot; + wire [ 15:0] fifo0_m_axi_awqos; + wire [ 15:0] fifo0_m_axi_awregion; + wire [ 3:0] fifo0_m_axi_awuser; + wire [ 3:0] fifo0_m_axi_awvalid; + wire [ 3:0] fifo0_m_axi_awready; + wire [ 255:0] fifo0_m_axi_wdata; + wire [ 31:0] fifo0_m_axi_wstrb; + wire [ 3:0] fifo0_m_axi_wlast; + wire [ 3:0] fifo0_m_axi_wuser; + wire [ 3:0] fifo0_m_axi_wvalid; + wire [ 3:0] fifo0_m_axi_wready; + wire [ 3:0] fifo0_m_axi_bid; + wire [ 7:0] fifo0_m_axi_bresp; + wire [ 3:0] fifo0_m_axi_buser; + wire [ 3:0] fifo0_m_axi_bvalid; + wire [ 3:0] fifo0_m_axi_bready; + wire [ 3:0] fifo0_m_axi_arid; + wire [ 127:0] fifo0_m_axi_araddr; + wire [ 31:0] fifo0_m_axi_arlen; + wire [ 11:0] fifo0_m_axi_arsize; + wire [ 7:0] fifo0_m_axi_arburst; + wire [ 3:0] fifo0_m_axi_arlock; + wire [ 15:0] fifo0_m_axi_arcache; + wire [ 11:0] fifo0_m_axi_arprot; + wire [ 15:0] fifo0_m_axi_arqos; + wire [ 15:0] fifo0_m_axi_arregion; + wire [ 3:0] fifo0_m_axi_aruser; + wire [ 3:0] fifo0_m_axi_arvalid; + wire [ 3:0] fifo0_m_axi_arready; + wire [ 3:0] fifo0_m_axi_rid; + wire [ 255:0] fifo0_m_axi_rdata; + wire [ 7:0] fifo0_m_axi_rresp; + wire [ 3:0] fifo0_m_axi_rlast; + wire [ 3:0] fifo0_m_axi_ruser; + wire [ 3:0] fifo0_m_axi_rvalid; + wire [ 3:0] fifo0_m_axi_rready; rfnoc_block_axi_ram_fifo #( - .THIS_PORTID(3), - .CHDR_W(CHDR_W), - .NUM_PORTS(4), - .MEM_DATA_W(64), - .MEM_ADDR_W(31), - .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), - .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), - .MEM_CLK_RATE(303819444), - .MTU(MTU) + .THIS_PORTID (3), + .CHDR_W (CHDR_W), + .NUM_PORTS (4), + .MEM_DATA_W (64), + .MEM_ADDR_W (31), + .FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE (303819444), + .MTU (MTU) ) b_fifo0_1 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk(fifo0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), - .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), - - .axi_rst(fifo0_axi_rst), - .m_axi_awid(fifo0_m_axi_awid), - .m_axi_awaddr(fifo0_m_axi_awaddr), - .m_axi_awlen(fifo0_m_axi_awlen), - .m_axi_awsize(fifo0_m_axi_awsize), - .m_axi_awburst(fifo0_m_axi_awburst), - .m_axi_awlock(fifo0_m_axi_awlock), - .m_axi_awcache(fifo0_m_axi_awcache), - .m_axi_awprot(fifo0_m_axi_awprot), - .m_axi_awqos(fifo0_m_axi_awqos), - .m_axi_awregion(fifo0_m_axi_awregion), - .m_axi_awuser(fifo0_m_axi_awuser), - .m_axi_awvalid(fifo0_m_axi_awvalid), - .m_axi_awready(fifo0_m_axi_awready), - .m_axi_wdata(fifo0_m_axi_wdata), - .m_axi_wstrb(fifo0_m_axi_wstrb), - .m_axi_wlast(fifo0_m_axi_wlast), - .m_axi_wuser(fifo0_m_axi_wuser), - .m_axi_wvalid(fifo0_m_axi_wvalid), - .m_axi_wready(fifo0_m_axi_wready), - .m_axi_bid(fifo0_m_axi_bid), - .m_axi_bresp(fifo0_m_axi_bresp), - .m_axi_buser(fifo0_m_axi_buser), - .m_axi_bvalid(fifo0_m_axi_bvalid), - .m_axi_bready(fifo0_m_axi_bready), - .m_axi_arid(fifo0_m_axi_arid), - .m_axi_araddr(fifo0_m_axi_araddr), - .m_axi_arlen(fifo0_m_axi_arlen), - .m_axi_arsize(fifo0_m_axi_arsize), - .m_axi_arburst(fifo0_m_axi_arburst), - .m_axi_arlock(fifo0_m_axi_arlock), - .m_axi_arcache(fifo0_m_axi_arcache), - .m_axi_arprot(fifo0_m_axi_arprot), - .m_axi_arqos(fifo0_m_axi_arqos), - .m_axi_arregion(fifo0_m_axi_arregion), - .m_axi_aruser(fifo0_m_axi_aruser), - .m_axi_arvalid(fifo0_m_axi_arvalid), - .m_axi_arready(fifo0_m_axi_arready), - .m_axi_rid(fifo0_m_axi_rid), - .m_axi_rdata(fifo0_m_axi_rdata), - .m_axi_rresp(fifo0_m_axi_rresp), - .m_axi_rlast(fifo0_m_axi_rlast), - .m_axi_ruser(fifo0_m_axi_ruser), - .m_axi_rvalid(fifo0_m_axi_rvalid), - .m_axi_rready(fifo0_m_axi_rready), - - .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .axi_rst (fifo0_axi_rst), + .m_axi_awid (fifo0_m_axi_awid), + .m_axi_awaddr (fifo0_m_axi_awaddr), + .m_axi_awlen (fifo0_m_axi_awlen), + .m_axi_awsize (fifo0_m_axi_awsize), + .m_axi_awburst (fifo0_m_axi_awburst), + .m_axi_awlock (fifo0_m_axi_awlock), + .m_axi_awcache (fifo0_m_axi_awcache), + .m_axi_awprot (fifo0_m_axi_awprot), + .m_axi_awqos (fifo0_m_axi_awqos), + .m_axi_awregion (fifo0_m_axi_awregion), + .m_axi_awuser (fifo0_m_axi_awuser), + .m_axi_awvalid (fifo0_m_axi_awvalid), + .m_axi_awready (fifo0_m_axi_awready), + .m_axi_wdata (fifo0_m_axi_wdata), + .m_axi_wstrb (fifo0_m_axi_wstrb), + .m_axi_wlast (fifo0_m_axi_wlast), + .m_axi_wuser (fifo0_m_axi_wuser), + .m_axi_wvalid (fifo0_m_axi_wvalid), + .m_axi_wready (fifo0_m_axi_wready), + .m_axi_bid (fifo0_m_axi_bid), + .m_axi_bresp (fifo0_m_axi_bresp), + .m_axi_buser (fifo0_m_axi_buser), + .m_axi_bvalid (fifo0_m_axi_bvalid), + .m_axi_bready (fifo0_m_axi_bready), + .m_axi_arid (fifo0_m_axi_arid), + .m_axi_araddr (fifo0_m_axi_araddr), + .m_axi_arlen (fifo0_m_axi_arlen), + .m_axi_arsize (fifo0_m_axi_arsize), + .m_axi_arburst (fifo0_m_axi_arburst), + .m_axi_arlock (fifo0_m_axi_arlock), + .m_axi_arcache (fifo0_m_axi_arcache), + .m_axi_arprot (fifo0_m_axi_arprot), + .m_axi_arqos (fifo0_m_axi_arqos), + .m_axi_arregion (fifo0_m_axi_arregion), + .m_axi_aruser (fifo0_m_axi_aruser), + .m_axi_arvalid (fifo0_m_axi_arvalid), + .m_axi_arready (fifo0_m_axi_arready), + .m_axi_rid (fifo0_m_axi_rid), + .m_axi_rdata (fifo0_m_axi_rdata), + .m_axi_rresp (fifo0_m_axi_rresp), + .m_axi_rlast (fifo0_m_axi_rlast), + .m_axi_ruser (fifo0_m_axi_ruser), + .m_axi_rvalid (fifo0_m_axi_rvalid), + .m_axi_rready (fifo0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Static Router - // ---------------------------------------------------- - assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; - assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + //--------------------------------------------------------------------------- + + assign s_radio0_in_0_tdata = m_ep0_out0_tdata; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_radio0_in_0_tready; - assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; - assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tdata = m_radio0_out_0_tdata; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast; assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ep0_in0_tready; - assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; - assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tdata = m_ep1_out0_tdata; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast; assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; assign m_ep1_out0_tready = s_radio0_in_1_tready; - assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; - assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tdata = m_radio0_out_1_tdata; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast; assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; assign m_radio0_out_1_tready = s_ep1_in0_tready; - assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; - assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast; assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; assign m_ep4_out0_tready = s_fifo0_in_0_tready; - assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; - assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast; assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; assign m_fifo0_out_0_tready = s_ep4_in0_tready; - assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; - assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast; assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; assign m_ep5_out0_tready = s_fifo0_in_1_tready; - assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; - assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast; assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; assign m_fifo0_out_1_tready = s_ep5_in0_tready; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Unused Ports - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; assign s_fifo0_in_2_tlast = 1'b0; assign s_fifo0_in_2_tvalid = 1'b0; @@ -804,16 +855,19 @@ module rfnoc_image_core #( assign m_fifo0_out_2_tready = 1'b1; assign m_fifo0_out_3_tready = 1'b1; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Clock Domains - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign radio0_radio_clk = radio_clk; assign fifo0_mem_clk = dram_clk; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // IO Port Connection - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; @@ -883,3 +937,6 @@ module rfnoc_image_core #( assign radio0_radio_time = radio_time; endmodule + + +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v index 43b9ffc81..19807fa9b 100644 --- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v @@ -1,19 +1,32 @@ // -// Copyright 2020 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // - // Module: rfnoc_image_core (for n300) -// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) -// Re-running that tool will overwrite this file! -// File generated on: 2020-09-02T12:02:55.936585 -// Source: ./n300_rfnoc_image_core.yml -// Source SHA256: e9dd3107c1f434abca5d183f64dfc5e53d52192f5d488cab07b239c3b44b2593 +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:08.459279 +// Source: n300_rfnoc_image_core.yml +// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861 +// + +`default_nettype none + module rfnoc_image_core #( - parameter [15:0] PROTOVER = {8'd1, 8'd0} -)( + parameter CHDR_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( // Clocks input wire chdr_aclk, input wire ctrl_aclk, @@ -21,113 +34,118 @@ module rfnoc_image_core #( input wire radio_clk, input wire dram_clk, // Basic - input wire [15:0] device_id, -//// IO ports ////////////////////////////////// -// ctrlport_radio0 - output wire [ 1-1:0] m_ctrlport_radio0_req_wr, - output wire [ 1-1:0] m_ctrlport_radio0_req_rd, - output wire [ 20-1:0] m_ctrlport_radio0_req_addr, - output wire [ 32-1:0] m_ctrlport_radio0_req_data, - output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio0_req_time, - input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio0_resp_status, - input wire [ 32-1:0] m_ctrlport_radio0_resp_data, -// time_keeper - input wire [ 64-1:0] radio_time, -// x300_radio0 - input wire [ 64-1:0] radio_rx_data_radio0, - input wire [ 2-1:0] radio_rx_stb_radio0, - output wire [ 2-1:0] radio_rx_running_radio0, - output wire [ 64-1:0] radio_tx_data_radio0, - input wire [ 2-1:0] radio_tx_stb_radio0, - output wire [ 2-1:0] radio_tx_running_radio0, -// dram - input wire [ 1-1:0] axi_rst, - output wire [ 4-1:0] m_axi_awid, - output wire [128-1:0] m_axi_awaddr, - output wire [ 32-1:0] m_axi_awlen, - output wire [ 12-1:0] m_axi_awsize, - output wire [ 8-1:0] m_axi_awburst, - output wire [ 4-1:0] m_axi_awlock, - output wire [ 16-1:0] m_axi_awcache, - output wire [ 12-1:0] m_axi_awprot, - output wire [ 16-1:0] m_axi_awqos, - output wire [ 16-1:0] m_axi_awregion, - output wire [ 4-1:0] m_axi_awuser, - output wire [ 4-1:0] m_axi_awvalid, - input wire [ 4-1:0] m_axi_awready, - output wire [256-1:0] m_axi_wdata, - output wire [ 32-1:0] m_axi_wstrb, - output wire [ 4-1:0] m_axi_wlast, - output wire [ 4-1:0] m_axi_wuser, - output wire [ 4-1:0] m_axi_wvalid, - input wire [ 4-1:0] m_axi_wready, - input wire [ 4-1:0] m_axi_bid, - input wire [ 8-1:0] m_axi_bresp, - input wire [ 4-1:0] m_axi_buser, - input wire [ 4-1:0] m_axi_bvalid, - output wire [ 4-1:0] m_axi_bready, - output wire [ 4-1:0] m_axi_arid, - output wire [128-1:0] m_axi_araddr, - output wire [ 32-1:0] m_axi_arlen, - output wire [ 12-1:0] m_axi_arsize, - output wire [ 8-1:0] m_axi_arburst, - output wire [ 4-1:0] m_axi_arlock, - output wire [ 16-1:0] m_axi_arcache, - output wire [ 12-1:0] m_axi_arprot, - output wire [ 16-1:0] m_axi_arqos, - output wire [ 16-1:0] m_axi_arregion, - output wire [ 4-1:0] m_axi_aruser, - output wire [ 4-1:0] m_axi_arvalid, - input wire [ 4-1:0] m_axi_arready, - input wire [ 4-1:0] m_axi_rid, - input wire [256-1:0] m_axi_rdata, - input wire [ 8-1:0] m_axi_rresp, - input wire [ 4-1:0] m_axi_rlast, - input wire [ 4-1:0] m_axi_ruser, - input wire [ 4-1:0] m_axi_rvalid, - output wire [ 4-1:0] m_axi_rready, - // Transport 0 (eth0 1G) - input wire [64-1:0] s_eth0_tdata, - input wire s_eth0_tlast, - input wire s_eth0_tvalid, - output wire s_eth0_tready, - output wire [64-1:0] m_eth0_tdata, - output wire m_eth0_tlast, - output wire m_eth0_tvalid, - input wire m_eth0_tready, - // Transport 1 (eth1 10G) - input wire [64-1:0] s_eth1_tdata, - input wire s_eth1_tlast, - input wire s_eth1_tvalid, - output wire s_eth1_tready, - output wire [64-1:0] m_eth1_tdata, - output wire m_eth1_tlast, - output wire m_eth1_tvalid, - input wire m_eth1_tready, - // Transport 2 (dma dma) - input wire [64-1:0] s_dma_tdata, - input wire s_dma_tlast, - input wire s_dma_tvalid, - output wire s_dma_tready, - output wire [64-1:0] m_dma_tdata, - output wire m_dma_tlast, - output wire m_dma_tvalid, - input wire m_dma_tready + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // time_keeper + input wire [ 63:0] radio_time, + // x300_radio0 + input wire [ 63:0] radio_rx_data_radio0, + input wire [ 1:0] radio_rx_stb_radio0, + output wire [ 1:0] radio_rx_running_radio0, + output wire [ 63:0] radio_tx_data_radio0, + input wire [ 1:0] radio_tx_stb_radio0, + output wire [ 1:0] radio_tx_running_radio0, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [CHDR_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [CHDR_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [CHDR_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [CHDR_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma) + input wire [CHDR_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [CHDR_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready ); - localparam CHDR_W = 64; - localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // CHDR Crossbar - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; @@ -176,12 +194,12 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), - .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tdata ({ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }), .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), - .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tdata ({xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }), .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), @@ -190,9 +208,18 @@ module rfnoc_image_core #( .ext_rtcfg_ack () ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Stream Endpoints - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 32768; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; @@ -202,8 +229,8 @@ module rfnoc_image_core #( wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; - wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; - wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; @@ -216,23 +243,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep0_tdata ), - .s_axis_chdr_tlast (xb_to_ep0_tlast ), - .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), - .s_axis_chdr_tready (xb_to_ep0_tready ), - .m_axis_chdr_tdata (ep0_to_xb_tdata ), - .m_axis_chdr_tlast (ep0_to_xb_tlast ), - .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), - .m_axis_chdr_tready (ep0_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), @@ -241,20 +268,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), - .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), - .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 32768; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; @@ -263,8 +298,8 @@ module rfnoc_image_core #( wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; - wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; - wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; @@ -277,23 +312,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep1_tdata ), - .s_axis_chdr_tlast (xb_to_ep1_tlast ), - .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), - .s_axis_chdr_tready (xb_to_ep1_tready ), - .m_axis_chdr_tdata (ep1_to_xb_tdata ), - .m_axis_chdr_tlast (ep1_to_xb_tlast ), - .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), - .m_axis_chdr_tready (ep1_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), @@ -302,20 +337,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), - .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), - .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 4096; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + wire [CHDR_W-1:0] m_ep2_out0_tdata; wire m_ep2_out0_tlast; wire m_ep2_out0_tvalid; @@ -324,8 +367,8 @@ module rfnoc_image_core #( wire s_ep2_in0_tlast; wire s_ep2_in0_tvalid; wire s_ep2_in0_tready; - wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; - wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; @@ -338,23 +381,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep2_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep2_tdata ), - .s_axis_chdr_tlast (xb_to_ep2_tlast ), - .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), - .s_axis_chdr_tready (xb_to_ep2_tready ), - .m_axis_chdr_tdata (ep2_to_xb_tdata ), - .m_axis_chdr_tlast (ep2_to_xb_tlast ), - .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), - .m_axis_chdr_tready (ep2_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), .s_axis_data_tdata ({s_ep2_in0_tdata}), .s_axis_data_tlast ({s_ep2_in0_tlast}), .s_axis_data_tvalid ({s_ep2_in0_tvalid}), @@ -363,20 +406,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep2_out0_tlast}), .m_axis_data_tvalid ({m_ep2_out0_tvalid}), .m_axis_data_tready ({m_ep2_out0_tready}), - .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), .s_axis_ctrl_tready (s_ep2_ctrl_tready), - .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), .m_axis_ctrl_tready (m_ep2_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 4096; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + wire [CHDR_W-1:0] m_ep3_out0_tdata; wire m_ep3_out0_tlast; wire m_ep3_out0_tvalid; @@ -385,8 +436,8 @@ module rfnoc_image_core #( wire s_ep3_in0_tlast; wire s_ep3_in0_tvalid; wire s_ep3_in0_tready; - wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; - wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; @@ -399,23 +450,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep3_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep3_tdata ), - .s_axis_chdr_tlast (xb_to_ep3_tlast ), - .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), - .s_axis_chdr_tready (xb_to_ep3_tready ), - .m_axis_chdr_tdata (ep3_to_xb_tdata ), - .m_axis_chdr_tlast (ep3_to_xb_tlast ), - .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), - .m_axis_chdr_tready (ep3_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), .s_axis_data_tdata ({s_ep3_in0_tdata}), .s_axis_data_tlast ({s_ep3_in0_tlast}), .s_axis_data_tvalid ({s_ep3_in0_tvalid}), @@ -424,46 +475,45 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep3_out0_tlast}), .m_axis_data_tvalid ({m_ep3_out0_tvalid}), .m_axis_data_tready ({m_ep3_out0_tready}), - .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), .s_axis_ctrl_tready (s_ep3_ctrl_tready), - .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), .m_axis_ctrl_tready (m_ep3_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Control Crossbar - // ---------------------------------------------------- - - wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; - wire m_core_ctrl_tlast , s_core_ctrl_tlast ; - wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; - wire m_core_ctrl_tready, s_core_ctrl_tready; - wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; - wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; - wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; - wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; - wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; - wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; - wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; - wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; - wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; - wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; - wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; - wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; - wire [31:0] m_replay0_ctrl_tdata , s_replay0_ctrl_tdata ; - wire m_replay0_ctrl_tlast , s_replay0_ctrl_tlast ; - wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; - wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata, s_duc0_ctrl_tdata; + wire m_duc0_ctrl_tlast, s_duc0_ctrl_tlast; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata, s_ddc0_ctrl_tdata; + wire m_ddc0_ctrl_tlast, s_ddc0_ctrl_tlast; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_replay0_ctrl_tdata, s_replay0_ctrl_tdata; + wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast; + wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; + wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), @@ -487,9 +537,11 @@ module rfnoc_image_core #( .deadlock_detected() ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // RFNoC Core Kernel - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( @@ -514,12 +566,12 @@ module rfnoc_image_core #( .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), - .s_axis_ctrl_tdata (s_core_ctrl_tdata ), - .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), - .m_axis_ctrl_tdata (m_core_ctrl_tdata ), - .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), @@ -527,13 +579,15 @@ module rfnoc_image_core #( .rfnoc_core_status (rfnoc_core_status) ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Blocks - // ---------------------------------------------------- + //--------------------------------------------------------------------------- - // ---------------------------------------------------- + //----------------------------------- // duc0 - // ---------------------------------------------------- + //----------------------------------- + wire duc0_ce_clk; wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; @@ -544,44 +598,41 @@ module rfnoc_image_core #( wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tready, m_duc0_out_0_tready; - rfnoc_block_duc #( - .THIS_PORTID(2), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .NUM_HB(3), - .CIC_MAX_INTERP(255), - .MTU(MTU) + .THIS_PORTID (2), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (MTU) ) b_duc0_0 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(duc0_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), - .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), - - - .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // ddc0 - // ---------------------------------------------------- + //----------------------------------- + wire ddc0_ce_clk; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; @@ -592,44 +643,41 @@ module rfnoc_image_core #( wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; - rfnoc_block_ddc #( - .THIS_PORTID(3), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .NUM_HB(3), - .CIC_MAX_DECIM(255), - .MTU(MTU) + .THIS_PORTID (3), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (MTU) ) b_ddc0_1 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(ddc0_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), - .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), - - - .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio0 - // ---------------------------------------------------- + //----------------------------------- + wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; @@ -640,79 +688,77 @@ module rfnoc_image_core #( wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tready, m_radio0_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio0_m_ctrlport_req_wr; - wire [ 1-1:0] radio0_m_ctrlport_req_rd; - wire [ 20-1:0] radio0_m_ctrlport_req_addr; - wire [ 32-1:0] radio0_m_ctrlport_req_data; - wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio0_m_ctrlport_req_has_time; - wire [ 64-1:0] radio0_m_ctrlport_req_time; - wire [ 1-1:0] radio0_m_ctrlport_resp_ack; - wire [ 2-1:0] radio0_m_ctrlport_resp_status; - wire [ 32-1:0] radio0_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio0_radio_time; - // x300_radio - wire [ 64-1:0] radio0_radio_rx_data; - wire [ 2-1:0] radio0_radio_rx_stb; - wire [ 2-1:0] radio0_radio_rx_running; - wire [ 64-1:0] radio0_radio_tx_data; - wire [ 2-1:0] radio0_radio_tx_stb; - wire [ 2-1:0] radio0_radio_tx_running; + // ctrl_port + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio0_radio_time; + // x300_radio + wire [ 63:0] radio0_radio_rx_data; + wire [ 1:0] radio0_radio_rx_stb; + wire [ 1:0] radio0_radio_rx_running; + wire [ 63:0] radio0_radio_tx_data; + wire [ 1:0] radio0_radio_tx_stb; + wire [ 1:0] radio0_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(4), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MTU(MTU) + .THIS_PORTID (4), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MTU (MTU) ) b_radio0_2 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio0_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), - .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), - - .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio0_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), - .radio_time(radio0_radio_time), - .radio_rx_data(radio0_radio_rx_data), - .radio_rx_stb(radio0_radio_rx_stb), - .radio_rx_running(radio0_radio_rx_running), - .radio_tx_data(radio0_radio_tx_data), - .radio_tx_stb(radio0_radio_tx_stb), - .radio_tx_running(radio0_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // replay0 - // ---------------------------------------------------- + //----------------------------------- + wire replay0_mem_clk; wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; @@ -723,212 +769,214 @@ module rfnoc_image_core #( wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_1_tready, m_replay0_out_0_tready; - // axi_ram - wire [ 1-1:0] replay0_axi_rst; - wire [ 4-1:0] replay0_m_axi_awid; - wire [128-1:0] replay0_m_axi_awaddr; - wire [ 32-1:0] replay0_m_axi_awlen; - wire [ 12-1:0] replay0_m_axi_awsize; - wire [ 8-1:0] replay0_m_axi_awburst; - wire [ 4-1:0] replay0_m_axi_awlock; - wire [ 16-1:0] replay0_m_axi_awcache; - wire [ 12-1:0] replay0_m_axi_awprot; - wire [ 16-1:0] replay0_m_axi_awqos; - wire [ 16-1:0] replay0_m_axi_awregion; - wire [ 4-1:0] replay0_m_axi_awuser; - wire [ 4-1:0] replay0_m_axi_awvalid; - wire [ 4-1:0] replay0_m_axi_awready; - wire [256-1:0] replay0_m_axi_wdata; - wire [ 32-1:0] replay0_m_axi_wstrb; - wire [ 4-1:0] replay0_m_axi_wlast; - wire [ 4-1:0] replay0_m_axi_wuser; - wire [ 4-1:0] replay0_m_axi_wvalid; - wire [ 4-1:0] replay0_m_axi_wready; - wire [ 4-1:0] replay0_m_axi_bid; - wire [ 8-1:0] replay0_m_axi_bresp; - wire [ 4-1:0] replay0_m_axi_buser; - wire [ 4-1:0] replay0_m_axi_bvalid; - wire [ 4-1:0] replay0_m_axi_bready; - wire [ 4-1:0] replay0_m_axi_arid; - wire [128-1:0] replay0_m_axi_araddr; - wire [ 32-1:0] replay0_m_axi_arlen; - wire [ 12-1:0] replay0_m_axi_arsize; - wire [ 8-1:0] replay0_m_axi_arburst; - wire [ 4-1:0] replay0_m_axi_arlock; - wire [ 16-1:0] replay0_m_axi_arcache; - wire [ 12-1:0] replay0_m_axi_arprot; - wire [ 16-1:0] replay0_m_axi_arqos; - wire [ 16-1:0] replay0_m_axi_arregion; - wire [ 4-1:0] replay0_m_axi_aruser; - wire [ 4-1:0] replay0_m_axi_arvalid; - wire [ 4-1:0] replay0_m_axi_arready; - wire [ 4-1:0] replay0_m_axi_rid; - wire [256-1:0] replay0_m_axi_rdata; - wire [ 8-1:0] replay0_m_axi_rresp; - wire [ 4-1:0] replay0_m_axi_rlast; - wire [ 4-1:0] replay0_m_axi_ruser; - wire [ 4-1:0] replay0_m_axi_rvalid; - wire [ 4-1:0] replay0_m_axi_rready; + // axi_ram + wire [ 0:0] replay0_axi_rst; + wire [ 3:0] replay0_m_axi_awid; + wire [ 127:0] replay0_m_axi_awaddr; + wire [ 31:0] replay0_m_axi_awlen; + wire [ 11:0] replay0_m_axi_awsize; + wire [ 7:0] replay0_m_axi_awburst; + wire [ 3:0] replay0_m_axi_awlock; + wire [ 15:0] replay0_m_axi_awcache; + wire [ 11:0] replay0_m_axi_awprot; + wire [ 15:0] replay0_m_axi_awqos; + wire [ 15:0] replay0_m_axi_awregion; + wire [ 3:0] replay0_m_axi_awuser; + wire [ 3:0] replay0_m_axi_awvalid; + wire [ 3:0] replay0_m_axi_awready; + wire [ 255:0] replay0_m_axi_wdata; + wire [ 31:0] replay0_m_axi_wstrb; + wire [ 3:0] replay0_m_axi_wlast; + wire [ 3:0] replay0_m_axi_wuser; + wire [ 3:0] replay0_m_axi_wvalid; + wire [ 3:0] replay0_m_axi_wready; + wire [ 3:0] replay0_m_axi_bid; + wire [ 7:0] replay0_m_axi_bresp; + wire [ 3:0] replay0_m_axi_buser; + wire [ 3:0] replay0_m_axi_bvalid; + wire [ 3:0] replay0_m_axi_bready; + wire [ 3:0] replay0_m_axi_arid; + wire [ 127:0] replay0_m_axi_araddr; + wire [ 31:0] replay0_m_axi_arlen; + wire [ 11:0] replay0_m_axi_arsize; + wire [ 7:0] replay0_m_axi_arburst; + wire [ 3:0] replay0_m_axi_arlock; + wire [ 15:0] replay0_m_axi_arcache; + wire [ 11:0] replay0_m_axi_arprot; + wire [ 15:0] replay0_m_axi_arqos; + wire [ 15:0] replay0_m_axi_arregion; + wire [ 3:0] replay0_m_axi_aruser; + wire [ 3:0] replay0_m_axi_arvalid; + wire [ 3:0] replay0_m_axi_arready; + wire [ 3:0] replay0_m_axi_rid; + wire [ 255:0] replay0_m_axi_rdata; + wire [ 7:0] replay0_m_axi_rresp; + wire [ 3:0] replay0_m_axi_rlast; + wire [ 3:0] replay0_m_axi_ruser; + wire [ 3:0] replay0_m_axi_rvalid; + wire [ 3:0] replay0_m_axi_rready; rfnoc_block_replay #( - .THIS_PORTID(5), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MEM_ADDR_W(31), - .MEM_DATA_W(64), - .MTU(MTU) + .THIS_PORTID (5), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MEM_ADDR_W (31), + .MEM_DATA_W (64), + .MTU (MTU) ) b_replay0_3 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk(replay0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), - .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), - - .axi_rst(replay0_axi_rst), - .m_axi_awid(replay0_m_axi_awid), - .m_axi_awaddr(replay0_m_axi_awaddr), - .m_axi_awlen(replay0_m_axi_awlen), - .m_axi_awsize(replay0_m_axi_awsize), - .m_axi_awburst(replay0_m_axi_awburst), - .m_axi_awlock(replay0_m_axi_awlock), - .m_axi_awcache(replay0_m_axi_awcache), - .m_axi_awprot(replay0_m_axi_awprot), - .m_axi_awqos(replay0_m_axi_awqos), - .m_axi_awregion(replay0_m_axi_awregion), - .m_axi_awuser(replay0_m_axi_awuser), - .m_axi_awvalid(replay0_m_axi_awvalid), - .m_axi_awready(replay0_m_axi_awready), - .m_axi_wdata(replay0_m_axi_wdata), - .m_axi_wstrb(replay0_m_axi_wstrb), - .m_axi_wlast(replay0_m_axi_wlast), - .m_axi_wuser(replay0_m_axi_wuser), - .m_axi_wvalid(replay0_m_axi_wvalid), - .m_axi_wready(replay0_m_axi_wready), - .m_axi_bid(replay0_m_axi_bid), - .m_axi_bresp(replay0_m_axi_bresp), - .m_axi_buser(replay0_m_axi_buser), - .m_axi_bvalid(replay0_m_axi_bvalid), - .m_axi_bready(replay0_m_axi_bready), - .m_axi_arid(replay0_m_axi_arid), - .m_axi_araddr(replay0_m_axi_araddr), - .m_axi_arlen(replay0_m_axi_arlen), - .m_axi_arsize(replay0_m_axi_arsize), - .m_axi_arburst(replay0_m_axi_arburst), - .m_axi_arlock(replay0_m_axi_arlock), - .m_axi_arcache(replay0_m_axi_arcache), - .m_axi_arprot(replay0_m_axi_arprot), - .m_axi_arqos(replay0_m_axi_arqos), - .m_axi_arregion(replay0_m_axi_arregion), - .m_axi_aruser(replay0_m_axi_aruser), - .m_axi_arvalid(replay0_m_axi_arvalid), - .m_axi_arready(replay0_m_axi_arready), - .m_axi_rid(replay0_m_axi_rid), - .m_axi_rdata(replay0_m_axi_rdata), - .m_axi_rresp(replay0_m_axi_rresp), - .m_axi_rlast(replay0_m_axi_rlast), - .m_axi_ruser(replay0_m_axi_ruser), - .m_axi_rvalid(replay0_m_axi_rvalid), - .m_axi_rready(replay0_m_axi_rready), - - .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (replay0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + .axi_rst (replay0_axi_rst), + .m_axi_awid (replay0_m_axi_awid), + .m_axi_awaddr (replay0_m_axi_awaddr), + .m_axi_awlen (replay0_m_axi_awlen), + .m_axi_awsize (replay0_m_axi_awsize), + .m_axi_awburst (replay0_m_axi_awburst), + .m_axi_awlock (replay0_m_axi_awlock), + .m_axi_awcache (replay0_m_axi_awcache), + .m_axi_awprot (replay0_m_axi_awprot), + .m_axi_awqos (replay0_m_axi_awqos), + .m_axi_awregion (replay0_m_axi_awregion), + .m_axi_awuser (replay0_m_axi_awuser), + .m_axi_awvalid (replay0_m_axi_awvalid), + .m_axi_awready (replay0_m_axi_awready), + .m_axi_wdata (replay0_m_axi_wdata), + .m_axi_wstrb (replay0_m_axi_wstrb), + .m_axi_wlast (replay0_m_axi_wlast), + .m_axi_wuser (replay0_m_axi_wuser), + .m_axi_wvalid (replay0_m_axi_wvalid), + .m_axi_wready (replay0_m_axi_wready), + .m_axi_bid (replay0_m_axi_bid), + .m_axi_bresp (replay0_m_axi_bresp), + .m_axi_buser (replay0_m_axi_buser), + .m_axi_bvalid (replay0_m_axi_bvalid), + .m_axi_bready (replay0_m_axi_bready), + .m_axi_arid (replay0_m_axi_arid), + .m_axi_araddr (replay0_m_axi_araddr), + .m_axi_arlen (replay0_m_axi_arlen), + .m_axi_arsize (replay0_m_axi_arsize), + .m_axi_arburst (replay0_m_axi_arburst), + .m_axi_arlock (replay0_m_axi_arlock), + .m_axi_arcache (replay0_m_axi_arcache), + .m_axi_arprot (replay0_m_axi_arprot), + .m_axi_arqos (replay0_m_axi_arqos), + .m_axi_arregion (replay0_m_axi_arregion), + .m_axi_aruser (replay0_m_axi_aruser), + .m_axi_arvalid (replay0_m_axi_arvalid), + .m_axi_arready (replay0_m_axi_arready), + .m_axi_rid (replay0_m_axi_rid), + .m_axi_rdata (replay0_m_axi_rdata), + .m_axi_rresp (replay0_m_axi_rresp), + .m_axi_rlast (replay0_m_axi_rlast), + .m_axi_ruser (replay0_m_axi_ruser), + .m_axi_rvalid (replay0_m_axi_rvalid), + .m_axi_rready (replay0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_replay0_in_1_tready, s_replay0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Static Router - // ---------------------------------------------------- - assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; - assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + //--------------------------------------------------------------------------- + + assign s_duc0_in_0_tdata = m_ep0_out0_tdata; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_duc0_in_0_tready; - assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; - assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast; assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; assign m_duc0_out_0_tready = s_radio0_in_0_tready; - assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; - assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast; assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ddc0_in_0_tready; - assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; - assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast; assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; assign m_ddc0_out_0_tready = s_ep0_in0_tready; - assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; - assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tdata = m_ep1_out0_tdata; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast; assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; assign m_ep1_out0_tready = s_duc0_in_1_tready; - assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; - assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast; assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; assign m_duc0_out_1_tready = s_radio0_in_1_tready; - assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; - assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast; assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; assign m_radio0_out_1_tready = s_ddc0_in_1_tready; - assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; - assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast; assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; assign m_ddc0_out_1_tready = s_ep1_in0_tready; - assign s_replay0_in_0_tdata = m_ep2_out0_tdata ; - assign s_replay0_in_0_tlast = m_ep2_out0_tlast ; + assign s_replay0_in_0_tdata = m_ep2_out0_tdata; + assign s_replay0_in_0_tlast = m_ep2_out0_tlast; assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid; assign m_ep2_out0_tready = s_replay0_in_0_tready; - assign s_ep2_in0_tdata = m_replay0_out_0_tdata ; - assign s_ep2_in0_tlast = m_replay0_out_0_tlast ; + assign s_ep2_in0_tdata = m_replay0_out_0_tdata; + assign s_ep2_in0_tlast = m_replay0_out_0_tlast; assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid; assign m_replay0_out_0_tready = s_ep2_in0_tready; - assign s_replay0_in_1_tdata = m_ep3_out0_tdata ; - assign s_replay0_in_1_tlast = m_ep3_out0_tlast ; + assign s_replay0_in_1_tdata = m_ep3_out0_tdata; + assign s_replay0_in_1_tlast = m_ep3_out0_tlast; assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid; assign m_ep3_out0_tready = s_replay0_in_1_tready; - assign s_ep3_in0_tdata = m_replay0_out_1_tdata ; - assign s_ep3_in0_tlast = m_replay0_out_1_tlast ; + assign s_ep3_in0_tdata = m_replay0_out_1_tdata; + assign s_ep3_in0_tlast = m_replay0_out_1_tlast; assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid; assign m_replay0_out_1_tready = s_ep3_in0_tready; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Unused Ports - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Clock Domains - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign radio0_radio_clk = radio_clk; assign ddc0_ce_clk = rfnoc_chdr_clk; assign duc0_ce_clk = rfnoc_chdr_clk; assign replay0_mem_clk = dram_clk; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // IO Port Connection - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; @@ -998,3 +1046,6 @@ module rfnoc_image_core #( assign radio0_radio_time = radio_time; endmodule + + +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh new file mode 100644 index 000000000..4c2d73748 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh @@ -0,0 +1,21 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for n300) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:08.505495 +// Source: n300_rfnoc_image_core.yml +// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861 +// + +`define CHDR_WIDTH 64 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.v b/fpga/usrp3/top/n3xx/n310_bist_image_core.v index 64989fb3f..5d08da4af 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_image_core.v +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.v @@ -1,19 +1,32 @@ // -// Copyright 2019 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // - // Module: rfnoc_image_core (for n310) -// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) -// Re-running that tool will overwrite this file! -// File generated on: 2019-11-08T15:58:14.371732 -// Source: ./n3xx/n310_bist_image_core.yml -// Source SHA256: 1a9ffb97d9678e700ad2aa172d206b6be9af30c7c0b014c21007d1de028a59d4 +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:05.500549 +// Source: n310_bist_image_core.yml +// Source SHA256: fe5a985fa2e6edde671a8fb818d11a583d818a74f707df9bb107901060780eea +// + +`default_nettype none + module rfnoc_image_core #( - parameter [15:0] PROTOVER = {8'd1, 8'd0} -)( + parameter CHDR_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( // Clocks input wire chdr_aclk, input wire ctrl_aclk, @@ -21,131 +34,136 @@ module rfnoc_image_core #( input wire radio_clk, input wire dram_clk, // Basic - input wire [15:0] device_id, -//// IO ports ////////////////////////////////// -// ctrlport_radio0 - output wire [ 1-1:0] m_ctrlport_radio0_req_wr, - output wire [ 1-1:0] m_ctrlport_radio0_req_rd, - output wire [ 20-1:0] m_ctrlport_radio0_req_addr, - output wire [ 32-1:0] m_ctrlport_radio0_req_data, - output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio0_req_time, - input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio0_resp_status, - input wire [ 32-1:0] m_ctrlport_radio0_resp_data, -// ctrlport_radio1 - output wire [ 1-1:0] m_ctrlport_radio1_req_wr, - output wire [ 1-1:0] m_ctrlport_radio1_req_rd, - output wire [ 20-1:0] m_ctrlport_radio1_req_addr, - output wire [ 32-1:0] m_ctrlport_radio1_req_data, - output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio1_req_time, - input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio1_resp_status, - input wire [ 32-1:0] m_ctrlport_radio1_resp_data, -// time_keeper - input wire [ 64-1:0] radio_time, -// x300_radio0 - input wire [ 64-1:0] radio_rx_data_radio0, - input wire [ 2-1:0] radio_rx_stb_radio0, - output wire [ 2-1:0] radio_rx_running_radio0, - output wire [ 64-1:0] radio_tx_data_radio0, - input wire [ 2-1:0] radio_tx_stb_radio0, - output wire [ 2-1:0] radio_tx_running_radio0, -// x300_radio1 - input wire [ 64-1:0] radio_rx_data_radio1, - input wire [ 2-1:0] radio_rx_stb_radio1, - output wire [ 2-1:0] radio_rx_running_radio1, - output wire [ 64-1:0] radio_tx_data_radio1, - input wire [ 2-1:0] radio_tx_stb_radio1, - output wire [ 2-1:0] radio_tx_running_radio1, -// dram - input wire [ 1-1:0] axi_rst, - output wire [ 4-1:0] m_axi_awid, - output wire [128-1:0] m_axi_awaddr, - output wire [ 32-1:0] m_axi_awlen, - output wire [ 12-1:0] m_axi_awsize, - output wire [ 8-1:0] m_axi_awburst, - output wire [ 4-1:0] m_axi_awlock, - output wire [ 16-1:0] m_axi_awcache, - output wire [ 12-1:0] m_axi_awprot, - output wire [ 16-1:0] m_axi_awqos, - output wire [ 16-1:0] m_axi_awregion, - output wire [ 4-1:0] m_axi_awuser, - output wire [ 4-1:0] m_axi_awvalid, - input wire [ 4-1:0] m_axi_awready, - output wire [256-1:0] m_axi_wdata, - output wire [ 32-1:0] m_axi_wstrb, - output wire [ 4-1:0] m_axi_wlast, - output wire [ 4-1:0] m_axi_wuser, - output wire [ 4-1:0] m_axi_wvalid, - input wire [ 4-1:0] m_axi_wready, - input wire [ 4-1:0] m_axi_bid, - input wire [ 8-1:0] m_axi_bresp, - input wire [ 4-1:0] m_axi_buser, - input wire [ 4-1:0] m_axi_bvalid, - output wire [ 4-1:0] m_axi_bready, - output wire [ 4-1:0] m_axi_arid, - output wire [128-1:0] m_axi_araddr, - output wire [ 32-1:0] m_axi_arlen, - output wire [ 12-1:0] m_axi_arsize, - output wire [ 8-1:0] m_axi_arburst, - output wire [ 4-1:0] m_axi_arlock, - output wire [ 16-1:0] m_axi_arcache, - output wire [ 12-1:0] m_axi_arprot, - output wire [ 16-1:0] m_axi_arqos, - output wire [ 16-1:0] m_axi_arregion, - output wire [ 4-1:0] m_axi_aruser, - output wire [ 4-1:0] m_axi_arvalid, - input wire [ 4-1:0] m_axi_arready, - input wire [ 4-1:0] m_axi_rid, - input wire [256-1:0] m_axi_rdata, - input wire [ 8-1:0] m_axi_rresp, - input wire [ 4-1:0] m_axi_rlast, - input wire [ 4-1:0] m_axi_ruser, - input wire [ 4-1:0] m_axi_rvalid, - output wire [ 4-1:0] m_axi_rready, - // Transport 0 (eth0 1G) - input wire [64-1:0] s_eth0_tdata, - input wire s_eth0_tlast, - input wire s_eth0_tvalid, - output wire s_eth0_tready, - output wire [64-1:0] m_eth0_tdata, - output wire m_eth0_tlast, - output wire m_eth0_tvalid, - input wire m_eth0_tready, - // Transport 1 (eth1 10G) - input wire [64-1:0] s_eth1_tdata, - input wire s_eth1_tlast, - input wire s_eth1_tvalid, - output wire s_eth1_tready, - output wire [64-1:0] m_eth1_tdata, - output wire m_eth1_tlast, - output wire m_eth1_tvalid, - input wire m_eth1_tready, - // Transport 2 (dma dma) - input wire [64-1:0] s_dma_tdata, - input wire s_dma_tlast, - input wire s_dma_tvalid, - output wire s_dma_tready, - output wire [64-1:0] m_dma_tdata, - output wire m_dma_tlast, - output wire m_dma_tvalid, - input wire m_dma_tready + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time_keeper + input wire [ 63:0] radio_time, + // x300_radio0 + input wire [ 63:0] radio_rx_data_radio0, + input wire [ 1:0] radio_rx_stb_radio0, + output wire [ 1:0] radio_rx_running_radio0, + output wire [ 63:0] radio_tx_data_radio0, + input wire [ 1:0] radio_tx_stb_radio0, + output wire [ 1:0] radio_tx_running_radio0, + // x300_radio1 + input wire [ 63:0] radio_rx_data_radio1, + input wire [ 1:0] radio_rx_stb_radio1, + output wire [ 1:0] radio_rx_running_radio1, + output wire [ 63:0] radio_tx_data_radio1, + input wire [ 1:0] radio_tx_stb_radio1, + output wire [ 1:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [CHDR_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [CHDR_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [CHDR_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [CHDR_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma) + input wire [CHDR_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [CHDR_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready ); - localparam CHDR_W = 64; - localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // CHDR Crossbar - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; @@ -210,12 +228,12 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), - .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tdata ({ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }), .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), - .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tdata ({xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }), .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), @@ -224,9 +242,18 @@ module rfnoc_image_core #( .ext_rtcfg_ack () ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Stream Endpoints - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 16384; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; @@ -236,8 +263,8 @@ module rfnoc_image_core #( wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; - wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; - wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; @@ -250,23 +277,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep0_tdata ), - .s_axis_chdr_tlast (xb_to_ep0_tlast ), - .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), - .s_axis_chdr_tready (xb_to_ep0_tready ), - .m_axis_chdr_tdata (ep0_to_xb_tdata ), - .m_axis_chdr_tlast (ep0_to_xb_tlast ), - .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), - .m_axis_chdr_tready (ep0_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), @@ -275,20 +302,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), - .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), - .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 16384; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; @@ -297,8 +332,8 @@ module rfnoc_image_core #( wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; - wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; - wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; @@ -311,23 +346,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep1_tdata ), - .s_axis_chdr_tlast (xb_to_ep1_tlast ), - .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), - .s_axis_chdr_tready (xb_to_ep1_tready ), - .m_axis_chdr_tdata (ep1_to_xb_tdata ), - .m_axis_chdr_tlast (ep1_to_xb_tlast ), - .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), - .m_axis_chdr_tready (ep1_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), @@ -336,20 +371,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), - .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), - .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 16384; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + wire [CHDR_W-1:0] m_ep2_out0_tdata; wire m_ep2_out0_tlast; wire m_ep2_out0_tvalid; @@ -358,8 +401,8 @@ module rfnoc_image_core #( wire s_ep2_in0_tlast; wire s_ep2_in0_tvalid; wire s_ep2_in0_tready; - wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; - wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; @@ -372,23 +415,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep2_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep2_tdata ), - .s_axis_chdr_tlast (xb_to_ep2_tlast ), - .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), - .s_axis_chdr_tready (xb_to_ep2_tready ), - .m_axis_chdr_tdata (ep2_to_xb_tdata ), - .m_axis_chdr_tlast (ep2_to_xb_tlast ), - .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), - .m_axis_chdr_tready (ep2_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), .s_axis_data_tdata ({s_ep2_in0_tdata}), .s_axis_data_tlast ({s_ep2_in0_tlast}), .s_axis_data_tvalid ({s_ep2_in0_tvalid}), @@ -397,20 +440,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep2_out0_tlast}), .m_axis_data_tvalid ({m_ep2_out0_tvalid}), .m_axis_data_tready ({m_ep2_out0_tready}), - .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), .s_axis_ctrl_tready (s_ep2_ctrl_tready), - .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), .m_axis_ctrl_tready (m_ep2_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 16384; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + wire [CHDR_W-1:0] m_ep3_out0_tdata; wire m_ep3_out0_tlast; wire m_ep3_out0_tvalid; @@ -419,8 +470,8 @@ module rfnoc_image_core #( wire s_ep3_in0_tlast; wire s_ep3_in0_tvalid; wire s_ep3_in0_tready; - wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; - wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; @@ -433,23 +484,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep3_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep3_tdata ), - .s_axis_chdr_tlast (xb_to_ep3_tlast ), - .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), - .s_axis_chdr_tready (xb_to_ep3_tready ), - .m_axis_chdr_tdata (ep3_to_xb_tdata ), - .m_axis_chdr_tlast (ep3_to_xb_tlast ), - .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), - .m_axis_chdr_tready (ep3_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), .s_axis_data_tdata ({s_ep3_in0_tdata}), .s_axis_data_tlast ({s_ep3_in0_tlast}), .s_axis_data_tvalid ({s_ep3_in0_tvalid}), @@ -458,20 +509,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep3_out0_tlast}), .m_axis_data_tvalid ({m_ep3_out0_tvalid}), .m_axis_data_tready ({m_ep3_out0_tready}), - .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), .s_axis_ctrl_tready (s_ep3_ctrl_tready), - .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), .m_axis_ctrl_tready (m_ep3_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP4 = 16384; + localparam INGRESS_BUFF_SIZE_EP4 = + REQ_BUFF_SIZE_EP4 == 0 ? 5 : + REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP4); + wire [CHDR_W-1:0] m_ep4_out0_tdata; wire m_ep4_out0_tlast; wire m_ep4_out0_tvalid; @@ -480,8 +539,8 @@ module rfnoc_image_core #( wire s_ep4_in0_tlast; wire s_ep4_in0_tvalid; wire s_ep4_in0_tready; - wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; - wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; + wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; @@ -494,23 +553,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (4), .CTRL_XBAR_PORT (5), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep4_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep4_tdata ), - .s_axis_chdr_tlast (xb_to_ep4_tlast ), - .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), - .s_axis_chdr_tready (xb_to_ep4_tready ), - .m_axis_chdr_tdata (ep4_to_xb_tdata ), - .m_axis_chdr_tlast (ep4_to_xb_tlast ), - .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), - .m_axis_chdr_tready (ep4_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep4_tdata), + .s_axis_chdr_tlast (xb_to_ep4_tlast), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid), + .s_axis_chdr_tready (xb_to_ep4_tready), + .m_axis_chdr_tdata (ep4_to_xb_tdata), + .m_axis_chdr_tlast (ep4_to_xb_tlast), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid), + .m_axis_chdr_tready (ep4_to_xb_tready), .s_axis_data_tdata ({s_ep4_in0_tdata}), .s_axis_data_tlast ({s_ep4_in0_tlast}), .s_axis_data_tvalid ({s_ep4_in0_tvalid}), @@ -519,20 +578,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep4_out0_tlast}), .m_axis_data_tvalid ({m_ep4_out0_tvalid}), .m_axis_data_tready ({m_ep4_out0_tready}), - .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), .s_axis_ctrl_tready (s_ep4_ctrl_tready), - .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), .m_axis_ctrl_tready (m_ep4_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP5 = 16384; + localparam INGRESS_BUFF_SIZE_EP5 = + REQ_BUFF_SIZE_EP5 == 0 ? 5 : + REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP5); + wire [CHDR_W-1:0] m_ep5_out0_tdata; wire m_ep5_out0_tlast; wire m_ep5_out0_tvalid; @@ -541,8 +608,8 @@ module rfnoc_image_core #( wire s_ep5_in0_tlast; wire s_ep5_in0_tvalid; wire s_ep5_in0_tready; - wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; - wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; + wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; @@ -555,23 +622,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (5), .CTRL_XBAR_PORT (6), - .INGRESS_BUFF_SIZE (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep5_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep5_tdata ), - .s_axis_chdr_tlast (xb_to_ep5_tlast ), - .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), - .s_axis_chdr_tready (xb_to_ep5_tready ), - .m_axis_chdr_tdata (ep5_to_xb_tdata ), - .m_axis_chdr_tlast (ep5_to_xb_tlast ), - .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), - .m_axis_chdr_tready (ep5_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep5_tdata), + .s_axis_chdr_tlast (xb_to_ep5_tlast), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid), + .s_axis_chdr_tready (xb_to_ep5_tready), + .m_axis_chdr_tdata (ep5_to_xb_tdata), + .m_axis_chdr_tlast (ep5_to_xb_tlast), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid), + .m_axis_chdr_tready (ep5_to_xb_tready), .s_axis_data_tdata ({s_ep5_in0_tdata}), .s_axis_data_tlast ({s_ep5_in0_tlast}), .s_axis_data_tvalid ({s_ep5_in0_tvalid}), @@ -580,42 +647,41 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep5_out0_tlast}), .m_axis_data_tvalid ({m_ep5_out0_tvalid}), .m_axis_data_tready ({m_ep5_out0_tready}), - .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), .s_axis_ctrl_tready (s_ep5_ctrl_tready), - .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), .m_axis_ctrl_tready (m_ep5_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Control Crossbar - // ---------------------------------------------------- - - wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; - wire m_core_ctrl_tlast , s_core_ctrl_tlast ; - wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; - wire m_core_ctrl_tready, s_core_ctrl_tready; - wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; - wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; - wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; - wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; - wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; - wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; - wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; - wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; - wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; - wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; - wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; - wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata, s_fifo0_ctrl_tdata; + wire m_fifo0_ctrl_tlast, s_fifo0_ctrl_tlast; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), @@ -639,9 +705,11 @@ module rfnoc_image_core #( .deadlock_detected() ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // RFNoC Core Kernel - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( @@ -666,12 +734,12 @@ module rfnoc_image_core #( .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), - .s_axis_ctrl_tdata (s_core_ctrl_tdata ), - .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), - .m_axis_ctrl_tdata (m_core_ctrl_tdata ), - .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), @@ -679,13 +747,15 @@ module rfnoc_image_core #( .rfnoc_core_status (rfnoc_core_status) ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Blocks - // ---------------------------------------------------- + //--------------------------------------------------------------------------- - // ---------------------------------------------------- + //----------------------------------- // radio0 - // ---------------------------------------------------- + //----------------------------------- + wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; @@ -696,79 +766,77 @@ module rfnoc_image_core #( wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tready, m_radio0_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio0_m_ctrlport_req_wr; - wire [ 1-1:0] radio0_m_ctrlport_req_rd; - wire [ 20-1:0] radio0_m_ctrlport_req_addr; - wire [ 32-1:0] radio0_m_ctrlport_req_data; - wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio0_m_ctrlport_req_has_time; - wire [ 64-1:0] radio0_m_ctrlport_req_time; - wire [ 1-1:0] radio0_m_ctrlport_resp_ack; - wire [ 2-1:0] radio0_m_ctrlport_resp_status; - wire [ 32-1:0] radio0_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio0_radio_time; - // x300_radio - wire [ 64-1:0] radio0_radio_rx_data; - wire [ 2-1:0] radio0_radio_rx_stb; - wire [ 2-1:0] radio0_radio_rx_running; - wire [ 64-1:0] radio0_radio_tx_data; - wire [ 2-1:0] radio0_radio_tx_stb; - wire [ 2-1:0] radio0_radio_tx_running; + // ctrl_port + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio0_radio_time; + // x300_radio + wire [ 63:0] radio0_radio_rx_data; + wire [ 1:0] radio0_radio_rx_stb; + wire [ 1:0] radio0_radio_rx_running; + wire [ 63:0] radio0_radio_tx_data; + wire [ 1:0] radio0_radio_tx_stb; + wire [ 1:0] radio0_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(2), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MTU(MTU) + .THIS_PORTID (2), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MTU (MTU) ) b_radio0_0 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio0_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), - .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), - - .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio0_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), - .radio_time(radio0_radio_time), - .radio_rx_data(radio0_radio_rx_data), - .radio_rx_stb(radio0_radio_rx_stb), - .radio_rx_running(radio0_radio_rx_running), - .radio_tx_data(radio0_radio_tx_data), - .radio_tx_stb(radio0_radio_tx_stb), - .radio_tx_running(radio0_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio1 - // ---------------------------------------------------- + //----------------------------------- + wire radio1_radio_clk; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; @@ -779,79 +847,77 @@ module rfnoc_image_core #( wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tready, m_radio1_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio1_m_ctrlport_req_wr; - wire [ 1-1:0] radio1_m_ctrlport_req_rd; - wire [ 20-1:0] radio1_m_ctrlport_req_addr; - wire [ 32-1:0] radio1_m_ctrlport_req_data; - wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio1_m_ctrlport_req_has_time; - wire [ 64-1:0] radio1_m_ctrlport_req_time; - wire [ 1-1:0] radio1_m_ctrlport_resp_ack; - wire [ 2-1:0] radio1_m_ctrlport_resp_status; - wire [ 32-1:0] radio1_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio1_radio_time; - // x300_radio - wire [ 64-1:0] radio1_radio_rx_data; - wire [ 2-1:0] radio1_radio_rx_stb; - wire [ 2-1:0] radio1_radio_rx_running; - wire [ 64-1:0] radio1_radio_tx_data; - wire [ 2-1:0] radio1_radio_tx_stb; - wire [ 2-1:0] radio1_radio_tx_running; + // ctrl_port + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio1_radio_time; + // x300_radio + wire [ 63:0] radio1_radio_rx_data; + wire [ 1:0] radio1_radio_rx_stb; + wire [ 1:0] radio1_radio_rx_running; + wire [ 63:0] radio1_radio_tx_data; + wire [ 1:0] radio1_radio_tx_stb; + wire [ 1:0] radio1_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(3), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MTU(MTU) + .THIS_PORTID (3), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MTU (MTU) ) b_radio1_1 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio1_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), - .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), - - .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio1_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), - .radio_time(radio1_radio_time), - .radio_rx_data(radio1_radio_rx_data), - .radio_rx_stb(radio1_radio_rx_stb), - .radio_rx_running(radio1_radio_rx_running), - .radio_tx_data(radio1_radio_tx_data), - .radio_tx_stb(radio1_radio_tx_stb), - .radio_tx_running(radio1_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // fifo0 - // ---------------------------------------------------- + //----------------------------------- + wire fifo0_mem_clk; wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; @@ -862,202 +928,201 @@ module rfnoc_image_core #( wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; - // axi_ram - wire [ 1-1:0] fifo0_axi_rst; - wire [ 4-1:0] fifo0_m_axi_awid; - wire [128-1:0] fifo0_m_axi_awaddr; - wire [ 32-1:0] fifo0_m_axi_awlen; - wire [ 12-1:0] fifo0_m_axi_awsize; - wire [ 8-1:0] fifo0_m_axi_awburst; - wire [ 4-1:0] fifo0_m_axi_awlock; - wire [ 16-1:0] fifo0_m_axi_awcache; - wire [ 12-1:0] fifo0_m_axi_awprot; - wire [ 16-1:0] fifo0_m_axi_awqos; - wire [ 16-1:0] fifo0_m_axi_awregion; - wire [ 4-1:0] fifo0_m_axi_awuser; - wire [ 4-1:0] fifo0_m_axi_awvalid; - wire [ 4-1:0] fifo0_m_axi_awready; - wire [256-1:0] fifo0_m_axi_wdata; - wire [ 32-1:0] fifo0_m_axi_wstrb; - wire [ 4-1:0] fifo0_m_axi_wlast; - wire [ 4-1:0] fifo0_m_axi_wuser; - wire [ 4-1:0] fifo0_m_axi_wvalid; - wire [ 4-1:0] fifo0_m_axi_wready; - wire [ 4-1:0] fifo0_m_axi_bid; - wire [ 8-1:0] fifo0_m_axi_bresp; - wire [ 4-1:0] fifo0_m_axi_buser; - wire [ 4-1:0] fifo0_m_axi_bvalid; - wire [ 4-1:0] fifo0_m_axi_bready; - wire [ 4-1:0] fifo0_m_axi_arid; - wire [128-1:0] fifo0_m_axi_araddr; - wire [ 32-1:0] fifo0_m_axi_arlen; - wire [ 12-1:0] fifo0_m_axi_arsize; - wire [ 8-1:0] fifo0_m_axi_arburst; - wire [ 4-1:0] fifo0_m_axi_arlock; - wire [ 16-1:0] fifo0_m_axi_arcache; - wire [ 12-1:0] fifo0_m_axi_arprot; - wire [ 16-1:0] fifo0_m_axi_arqos; - wire [ 16-1:0] fifo0_m_axi_arregion; - wire [ 4-1:0] fifo0_m_axi_aruser; - wire [ 4-1:0] fifo0_m_axi_arvalid; - wire [ 4-1:0] fifo0_m_axi_arready; - wire [ 4-1:0] fifo0_m_axi_rid; - wire [256-1:0] fifo0_m_axi_rdata; - wire [ 8-1:0] fifo0_m_axi_rresp; - wire [ 4-1:0] fifo0_m_axi_rlast; - wire [ 4-1:0] fifo0_m_axi_ruser; - wire [ 4-1:0] fifo0_m_axi_rvalid; - wire [ 4-1:0] fifo0_m_axi_rready; + // axi_ram + wire [ 0:0] fifo0_axi_rst; + wire [ 3:0] fifo0_m_axi_awid; + wire [ 127:0] fifo0_m_axi_awaddr; + wire [ 31:0] fifo0_m_axi_awlen; + wire [ 11:0] fifo0_m_axi_awsize; + wire [ 7:0] fifo0_m_axi_awburst; + wire [ 3:0] fifo0_m_axi_awlock; + wire [ 15:0] fifo0_m_axi_awcache; + wire [ 11:0] fifo0_m_axi_awprot; + wire [ 15:0] fifo0_m_axi_awqos; + wire [ 15:0] fifo0_m_axi_awregion; + wire [ 3:0] fifo0_m_axi_awuser; + wire [ 3:0] fifo0_m_axi_awvalid; + wire [ 3:0] fifo0_m_axi_awready; + wire [ 255:0] fifo0_m_axi_wdata; + wire [ 31:0] fifo0_m_axi_wstrb; + wire [ 3:0] fifo0_m_axi_wlast; + wire [ 3:0] fifo0_m_axi_wuser; + wire [ 3:0] fifo0_m_axi_wvalid; + wire [ 3:0] fifo0_m_axi_wready; + wire [ 3:0] fifo0_m_axi_bid; + wire [ 7:0] fifo0_m_axi_bresp; + wire [ 3:0] fifo0_m_axi_buser; + wire [ 3:0] fifo0_m_axi_bvalid; + wire [ 3:0] fifo0_m_axi_bready; + wire [ 3:0] fifo0_m_axi_arid; + wire [ 127:0] fifo0_m_axi_araddr; + wire [ 31:0] fifo0_m_axi_arlen; + wire [ 11:0] fifo0_m_axi_arsize; + wire [ 7:0] fifo0_m_axi_arburst; + wire [ 3:0] fifo0_m_axi_arlock; + wire [ 15:0] fifo0_m_axi_arcache; + wire [ 11:0] fifo0_m_axi_arprot; + wire [ 15:0] fifo0_m_axi_arqos; + wire [ 15:0] fifo0_m_axi_arregion; + wire [ 3:0] fifo0_m_axi_aruser; + wire [ 3:0] fifo0_m_axi_arvalid; + wire [ 3:0] fifo0_m_axi_arready; + wire [ 3:0] fifo0_m_axi_rid; + wire [ 255:0] fifo0_m_axi_rdata; + wire [ 7:0] fifo0_m_axi_rresp; + wire [ 3:0] fifo0_m_axi_rlast; + wire [ 3:0] fifo0_m_axi_ruser; + wire [ 3:0] fifo0_m_axi_rvalid; + wire [ 3:0] fifo0_m_axi_rready; rfnoc_block_axi_ram_fifo #( - .THIS_PORTID(4), - .CHDR_W(CHDR_W), - .NUM_PORTS(4), - .MEM_DATA_W(64), - .MEM_ADDR_W(31), - .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), - .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), - .MEM_CLK_RATE(303819444), - .MTU(MTU) + .THIS_PORTID (4), + .CHDR_W (CHDR_W), + .NUM_PORTS (4), + .MEM_DATA_W (64), + .MEM_ADDR_W (31), + .FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE (303819444), + .MTU (MTU) ) b_fifo0_2 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk(fifo0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), - .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), - - .axi_rst(fifo0_axi_rst), - .m_axi_awid(fifo0_m_axi_awid), - .m_axi_awaddr(fifo0_m_axi_awaddr), - .m_axi_awlen(fifo0_m_axi_awlen), - .m_axi_awsize(fifo0_m_axi_awsize), - .m_axi_awburst(fifo0_m_axi_awburst), - .m_axi_awlock(fifo0_m_axi_awlock), - .m_axi_awcache(fifo0_m_axi_awcache), - .m_axi_awprot(fifo0_m_axi_awprot), - .m_axi_awqos(fifo0_m_axi_awqos), - .m_axi_awregion(fifo0_m_axi_awregion), - .m_axi_awuser(fifo0_m_axi_awuser), - .m_axi_awvalid(fifo0_m_axi_awvalid), - .m_axi_awready(fifo0_m_axi_awready), - .m_axi_wdata(fifo0_m_axi_wdata), - .m_axi_wstrb(fifo0_m_axi_wstrb), - .m_axi_wlast(fifo0_m_axi_wlast), - .m_axi_wuser(fifo0_m_axi_wuser), - .m_axi_wvalid(fifo0_m_axi_wvalid), - .m_axi_wready(fifo0_m_axi_wready), - .m_axi_bid(fifo0_m_axi_bid), - .m_axi_bresp(fifo0_m_axi_bresp), - .m_axi_buser(fifo0_m_axi_buser), - .m_axi_bvalid(fifo0_m_axi_bvalid), - .m_axi_bready(fifo0_m_axi_bready), - .m_axi_arid(fifo0_m_axi_arid), - .m_axi_araddr(fifo0_m_axi_araddr), - .m_axi_arlen(fifo0_m_axi_arlen), - .m_axi_arsize(fifo0_m_axi_arsize), - .m_axi_arburst(fifo0_m_axi_arburst), - .m_axi_arlock(fifo0_m_axi_arlock), - .m_axi_arcache(fifo0_m_axi_arcache), - .m_axi_arprot(fifo0_m_axi_arprot), - .m_axi_arqos(fifo0_m_axi_arqos), - .m_axi_arregion(fifo0_m_axi_arregion), - .m_axi_aruser(fifo0_m_axi_aruser), - .m_axi_arvalid(fifo0_m_axi_arvalid), - .m_axi_arready(fifo0_m_axi_arready), - .m_axi_rid(fifo0_m_axi_rid), - .m_axi_rdata(fifo0_m_axi_rdata), - .m_axi_rresp(fifo0_m_axi_rresp), - .m_axi_rlast(fifo0_m_axi_rlast), - .m_axi_ruser(fifo0_m_axi_ruser), - .m_axi_rvalid(fifo0_m_axi_rvalid), - .m_axi_rready(fifo0_m_axi_rready), - - .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .axi_rst (fifo0_axi_rst), + .m_axi_awid (fifo0_m_axi_awid), + .m_axi_awaddr (fifo0_m_axi_awaddr), + .m_axi_awlen (fifo0_m_axi_awlen), + .m_axi_awsize (fifo0_m_axi_awsize), + .m_axi_awburst (fifo0_m_axi_awburst), + .m_axi_awlock (fifo0_m_axi_awlock), + .m_axi_awcache (fifo0_m_axi_awcache), + .m_axi_awprot (fifo0_m_axi_awprot), + .m_axi_awqos (fifo0_m_axi_awqos), + .m_axi_awregion (fifo0_m_axi_awregion), + .m_axi_awuser (fifo0_m_axi_awuser), + .m_axi_awvalid (fifo0_m_axi_awvalid), + .m_axi_awready (fifo0_m_axi_awready), + .m_axi_wdata (fifo0_m_axi_wdata), + .m_axi_wstrb (fifo0_m_axi_wstrb), + .m_axi_wlast (fifo0_m_axi_wlast), + .m_axi_wuser (fifo0_m_axi_wuser), + .m_axi_wvalid (fifo0_m_axi_wvalid), + .m_axi_wready (fifo0_m_axi_wready), + .m_axi_bid (fifo0_m_axi_bid), + .m_axi_bresp (fifo0_m_axi_bresp), + .m_axi_buser (fifo0_m_axi_buser), + .m_axi_bvalid (fifo0_m_axi_bvalid), + .m_axi_bready (fifo0_m_axi_bready), + .m_axi_arid (fifo0_m_axi_arid), + .m_axi_araddr (fifo0_m_axi_araddr), + .m_axi_arlen (fifo0_m_axi_arlen), + .m_axi_arsize (fifo0_m_axi_arsize), + .m_axi_arburst (fifo0_m_axi_arburst), + .m_axi_arlock (fifo0_m_axi_arlock), + .m_axi_arcache (fifo0_m_axi_arcache), + .m_axi_arprot (fifo0_m_axi_arprot), + .m_axi_arqos (fifo0_m_axi_arqos), + .m_axi_arregion (fifo0_m_axi_arregion), + .m_axi_aruser (fifo0_m_axi_aruser), + .m_axi_arvalid (fifo0_m_axi_arvalid), + .m_axi_arready (fifo0_m_axi_arready), + .m_axi_rid (fifo0_m_axi_rid), + .m_axi_rdata (fifo0_m_axi_rdata), + .m_axi_rresp (fifo0_m_axi_rresp), + .m_axi_rlast (fifo0_m_axi_rlast), + .m_axi_ruser (fifo0_m_axi_ruser), + .m_axi_rvalid (fifo0_m_axi_rvalid), + .m_axi_rready (fifo0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Static Router - // ---------------------------------------------------- - assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; - assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + //--------------------------------------------------------------------------- + + assign s_radio0_in_0_tdata = m_ep0_out0_tdata; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_radio0_in_0_tready; - assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; - assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tdata = m_radio0_out_0_tdata; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast; assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ep0_in0_tready; - assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; - assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tdata = m_ep1_out0_tdata; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast; assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; assign m_ep1_out0_tready = s_radio0_in_1_tready; - assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; - assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tdata = m_radio0_out_1_tdata; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast; assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; assign m_radio0_out_1_tready = s_ep1_in0_tready; - assign s_radio1_in_0_tdata = m_ep2_out0_tdata ; - assign s_radio1_in_0_tlast = m_ep2_out0_tlast ; + assign s_radio1_in_0_tdata = m_ep2_out0_tdata; + assign s_radio1_in_0_tlast = m_ep2_out0_tlast; assign s_radio1_in_0_tvalid = m_ep2_out0_tvalid; assign m_ep2_out0_tready = s_radio1_in_0_tready; - assign s_ep2_in0_tdata = m_radio1_out_0_tdata ; - assign s_ep2_in0_tlast = m_radio1_out_0_tlast ; + assign s_ep2_in0_tdata = m_radio1_out_0_tdata; + assign s_ep2_in0_tlast = m_radio1_out_0_tlast; assign s_ep2_in0_tvalid = m_radio1_out_0_tvalid; assign m_radio1_out_0_tready = s_ep2_in0_tready; - assign s_radio1_in_1_tdata = m_ep3_out0_tdata ; - assign s_radio1_in_1_tlast = m_ep3_out0_tlast ; + assign s_radio1_in_1_tdata = m_ep3_out0_tdata; + assign s_radio1_in_1_tlast = m_ep3_out0_tlast; assign s_radio1_in_1_tvalid = m_ep3_out0_tvalid; assign m_ep3_out0_tready = s_radio1_in_1_tready; - assign s_ep3_in0_tdata = m_radio1_out_1_tdata ; - assign s_ep3_in0_tlast = m_radio1_out_1_tlast ; + assign s_ep3_in0_tdata = m_radio1_out_1_tdata; + assign s_ep3_in0_tlast = m_radio1_out_1_tlast; assign s_ep3_in0_tvalid = m_radio1_out_1_tvalid; assign m_radio1_out_1_tready = s_ep3_in0_tready; - assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; - assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast; assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; assign m_ep4_out0_tready = s_fifo0_in_0_tready; - assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; - assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast; assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; assign m_fifo0_out_0_tready = s_ep4_in0_tready; - assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; - assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast; assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; assign m_ep5_out0_tready = s_fifo0_in_1_tready; - assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; - assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast; assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; assign m_fifo0_out_1_tready = s_ep5_in0_tready; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Unused Ports - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; assign s_fifo0_in_2_tlast = 1'b0; assign s_fifo0_in_2_tvalid = 1'b0; @@ -1067,17 +1132,20 @@ module rfnoc_image_core #( assign m_fifo0_out_2_tready = 1'b1; assign m_fifo0_out_3_tready = 1'b1; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Clock Domains - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign radio0_radio_clk = radio_clk; assign radio1_radio_clk = radio_clk; assign fifo0_mem_clk = dram_clk; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // IO Port Connection - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; @@ -1167,3 +1235,6 @@ module rfnoc_image_core #( assign radio1_radio_time = radio_time; endmodule + + +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v index 3ded945ac..63fdc6b70 100644 --- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v @@ -1,19 +1,32 @@ // -// Copyright 2020 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // - // Module: rfnoc_image_core (for n310) -// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) -// Re-running that tool will overwrite this file! -// File generated on: 2020-09-02T12:03:00.129190 -// Source: ./n310_rfnoc_image_core.yml -// Source SHA256: 39427a6d2533bc5342e99d75d7eaff9368e89ab8ff639821d333143af5ace45b +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:09.232810 +// Source: n310_rfnoc_image_core.yml +// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284 +// + +`default_nettype none + module rfnoc_image_core #( - parameter [15:0] PROTOVER = {8'd1, 8'd0} -)( + parameter CHDR_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( // Clocks input wire chdr_aclk, input wire ctrl_aclk, @@ -21,131 +34,136 @@ module rfnoc_image_core #( input wire radio_clk, input wire dram_clk, // Basic - input wire [15:0] device_id, -//// IO ports ////////////////////////////////// -// ctrlport_radio0 - output wire [ 1-1:0] m_ctrlport_radio0_req_wr, - output wire [ 1-1:0] m_ctrlport_radio0_req_rd, - output wire [ 20-1:0] m_ctrlport_radio0_req_addr, - output wire [ 32-1:0] m_ctrlport_radio0_req_data, - output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio0_req_time, - input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio0_resp_status, - input wire [ 32-1:0] m_ctrlport_radio0_resp_data, -// ctrlport_radio1 - output wire [ 1-1:0] m_ctrlport_radio1_req_wr, - output wire [ 1-1:0] m_ctrlport_radio1_req_rd, - output wire [ 20-1:0] m_ctrlport_radio1_req_addr, - output wire [ 32-1:0] m_ctrlport_radio1_req_data, - output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio1_req_time, - input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio1_resp_status, - input wire [ 32-1:0] m_ctrlport_radio1_resp_data, -// time_keeper - input wire [ 64-1:0] radio_time, -// x300_radio0 - input wire [ 64-1:0] radio_rx_data_radio0, - input wire [ 2-1:0] radio_rx_stb_radio0, - output wire [ 2-1:0] radio_rx_running_radio0, - output wire [ 64-1:0] radio_tx_data_radio0, - input wire [ 2-1:0] radio_tx_stb_radio0, - output wire [ 2-1:0] radio_tx_running_radio0, -// x300_radio1 - input wire [ 64-1:0] radio_rx_data_radio1, - input wire [ 2-1:0] radio_rx_stb_radio1, - output wire [ 2-1:0] radio_rx_running_radio1, - output wire [ 64-1:0] radio_tx_data_radio1, - input wire [ 2-1:0] radio_tx_stb_radio1, - output wire [ 2-1:0] radio_tx_running_radio1, -// dram - input wire [ 1-1:0] axi_rst, - output wire [ 4-1:0] m_axi_awid, - output wire [128-1:0] m_axi_awaddr, - output wire [ 32-1:0] m_axi_awlen, - output wire [ 12-1:0] m_axi_awsize, - output wire [ 8-1:0] m_axi_awburst, - output wire [ 4-1:0] m_axi_awlock, - output wire [ 16-1:0] m_axi_awcache, - output wire [ 12-1:0] m_axi_awprot, - output wire [ 16-1:0] m_axi_awqos, - output wire [ 16-1:0] m_axi_awregion, - output wire [ 4-1:0] m_axi_awuser, - output wire [ 4-1:0] m_axi_awvalid, - input wire [ 4-1:0] m_axi_awready, - output wire [256-1:0] m_axi_wdata, - output wire [ 32-1:0] m_axi_wstrb, - output wire [ 4-1:0] m_axi_wlast, - output wire [ 4-1:0] m_axi_wuser, - output wire [ 4-1:0] m_axi_wvalid, - input wire [ 4-1:0] m_axi_wready, - input wire [ 4-1:0] m_axi_bid, - input wire [ 8-1:0] m_axi_bresp, - input wire [ 4-1:0] m_axi_buser, - input wire [ 4-1:0] m_axi_bvalid, - output wire [ 4-1:0] m_axi_bready, - output wire [ 4-1:0] m_axi_arid, - output wire [128-1:0] m_axi_araddr, - output wire [ 32-1:0] m_axi_arlen, - output wire [ 12-1:0] m_axi_arsize, - output wire [ 8-1:0] m_axi_arburst, - output wire [ 4-1:0] m_axi_arlock, - output wire [ 16-1:0] m_axi_arcache, - output wire [ 12-1:0] m_axi_arprot, - output wire [ 16-1:0] m_axi_arqos, - output wire [ 16-1:0] m_axi_arregion, - output wire [ 4-1:0] m_axi_aruser, - output wire [ 4-1:0] m_axi_arvalid, - input wire [ 4-1:0] m_axi_arready, - input wire [ 4-1:0] m_axi_rid, - input wire [256-1:0] m_axi_rdata, - input wire [ 8-1:0] m_axi_rresp, - input wire [ 4-1:0] m_axi_rlast, - input wire [ 4-1:0] m_axi_ruser, - input wire [ 4-1:0] m_axi_rvalid, - output wire [ 4-1:0] m_axi_rready, - // Transport 0 (eth0 1G) - input wire [64-1:0] s_eth0_tdata, - input wire s_eth0_tlast, - input wire s_eth0_tvalid, - output wire s_eth0_tready, - output wire [64-1:0] m_eth0_tdata, - output wire m_eth0_tlast, - output wire m_eth0_tvalid, - input wire m_eth0_tready, - // Transport 1 (eth1 10G) - input wire [64-1:0] s_eth1_tdata, - input wire s_eth1_tlast, - input wire s_eth1_tvalid, - output wire s_eth1_tready, - output wire [64-1:0] m_eth1_tdata, - output wire m_eth1_tlast, - output wire m_eth1_tvalid, - input wire m_eth1_tready, - // Transport 2 (dma dma) - input wire [64-1:0] s_dma_tdata, - input wire s_dma_tlast, - input wire s_dma_tvalid, - output wire s_dma_tready, - output wire [64-1:0] m_dma_tdata, - output wire m_dma_tlast, - output wire m_dma_tvalid, - input wire m_dma_tready + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time_keeper + input wire [ 63:0] radio_time, + // x300_radio0 + input wire [ 63:0] radio_rx_data_radio0, + input wire [ 1:0] radio_rx_stb_radio0, + output wire [ 1:0] radio_rx_running_radio0, + output wire [ 63:0] radio_tx_data_radio0, + input wire [ 1:0] radio_tx_stb_radio0, + output wire [ 1:0] radio_tx_running_radio0, + // x300_radio1 + input wire [ 63:0] radio_rx_data_radio1, + input wire [ 1:0] radio_rx_stb_radio1, + output wire [ 1:0] radio_rx_running_radio1, + output wire [ 63:0] radio_tx_data_radio1, + input wire [ 1:0] radio_tx_stb_radio1, + output wire [ 1:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [CHDR_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [CHDR_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [CHDR_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [CHDR_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma) + input wire [CHDR_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [CHDR_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready ); - localparam CHDR_W = 64; - localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // CHDR Crossbar - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; @@ -226,12 +244,12 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep7_to_xb_tdata, ep6_to_xb_tdata, ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), - .s_axis_tlast ({ep7_to_xb_tlast, ep6_to_xb_tlast, ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tdata ({ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }), .s_axis_tvalid ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep7_tdata, xb_to_ep6_tdata, xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), - .m_axis_tlast ({xb_to_ep7_tlast, xb_to_ep6_tlast, xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tdata ({xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }), .m_axis_tvalid ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), @@ -240,9 +258,18 @@ module rfnoc_image_core #( .ext_rtcfg_ack () ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Stream Endpoints - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 32768; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; @@ -252,8 +279,8 @@ module rfnoc_image_core #( wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; - wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; - wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; @@ -266,23 +293,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep0_tdata ), - .s_axis_chdr_tlast (xb_to_ep0_tlast ), - .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), - .s_axis_chdr_tready (xb_to_ep0_tready ), - .m_axis_chdr_tdata (ep0_to_xb_tdata ), - .m_axis_chdr_tlast (ep0_to_xb_tlast ), - .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), - .m_axis_chdr_tready (ep0_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), @@ -291,20 +318,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), - .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), - .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 32768; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; @@ -313,8 +348,8 @@ module rfnoc_image_core #( wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; - wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; - wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; @@ -327,23 +362,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep1_tdata ), - .s_axis_chdr_tlast (xb_to_ep1_tlast ), - .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), - .s_axis_chdr_tready (xb_to_ep1_tready ), - .m_axis_chdr_tdata (ep1_to_xb_tdata ), - .m_axis_chdr_tlast (ep1_to_xb_tlast ), - .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), - .m_axis_chdr_tready (ep1_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), @@ -352,20 +387,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), - .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), - .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 32768; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + wire [CHDR_W-1:0] m_ep2_out0_tdata; wire m_ep2_out0_tlast; wire m_ep2_out0_tvalid; @@ -374,8 +417,8 @@ module rfnoc_image_core #( wire s_ep2_in0_tlast; wire s_ep2_in0_tvalid; wire s_ep2_in0_tready; - wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; - wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; @@ -388,23 +431,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep2_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep2_tdata ), - .s_axis_chdr_tlast (xb_to_ep2_tlast ), - .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), - .s_axis_chdr_tready (xb_to_ep2_tready ), - .m_axis_chdr_tdata (ep2_to_xb_tdata ), - .m_axis_chdr_tlast (ep2_to_xb_tlast ), - .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), - .m_axis_chdr_tready (ep2_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), .s_axis_data_tdata ({s_ep2_in0_tdata}), .s_axis_data_tlast ({s_ep2_in0_tlast}), .s_axis_data_tvalid ({s_ep2_in0_tvalid}), @@ -413,20 +456,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep2_out0_tlast}), .m_axis_data_tvalid ({m_ep2_out0_tvalid}), .m_axis_data_tready ({m_ep2_out0_tready}), - .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), .s_axis_ctrl_tready (s_ep2_ctrl_tready), - .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), .m_axis_ctrl_tready (m_ep2_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 32768; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + wire [CHDR_W-1:0] m_ep3_out0_tdata; wire m_ep3_out0_tlast; wire m_ep3_out0_tvalid; @@ -435,8 +486,8 @@ module rfnoc_image_core #( wire s_ep3_in0_tlast; wire s_ep3_in0_tvalid; wire s_ep3_in0_tready; - wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; - wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; @@ -449,23 +500,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep3_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep3_tdata ), - .s_axis_chdr_tlast (xb_to_ep3_tlast ), - .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), - .s_axis_chdr_tready (xb_to_ep3_tready ), - .m_axis_chdr_tdata (ep3_to_xb_tdata ), - .m_axis_chdr_tlast (ep3_to_xb_tlast ), - .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), - .m_axis_chdr_tready (ep3_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), .s_axis_data_tdata ({s_ep3_in0_tdata}), .s_axis_data_tlast ({s_ep3_in0_tlast}), .s_axis_data_tvalid ({s_ep3_in0_tvalid}), @@ -474,20 +525,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep3_out0_tlast}), .m_axis_data_tvalid ({m_ep3_out0_tvalid}), .m_axis_data_tready ({m_ep3_out0_tready}), - .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), .s_axis_ctrl_tready (s_ep3_ctrl_tready), - .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), .m_axis_ctrl_tready (m_ep3_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP4 = 4096; + localparam INGRESS_BUFF_SIZE_EP4 = + REQ_BUFF_SIZE_EP4 == 0 ? 5 : + REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP4); + wire [CHDR_W-1:0] m_ep4_out0_tdata; wire m_ep4_out0_tlast; wire m_ep4_out0_tvalid; @@ -496,8 +555,8 @@ module rfnoc_image_core #( wire s_ep4_in0_tlast; wire s_ep4_in0_tvalid; wire s_ep4_in0_tready; - wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; - wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; + wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; @@ -510,23 +569,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (4), .CTRL_XBAR_PORT (5), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep4_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep4_tdata ), - .s_axis_chdr_tlast (xb_to_ep4_tlast ), - .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), - .s_axis_chdr_tready (xb_to_ep4_tready ), - .m_axis_chdr_tdata (ep4_to_xb_tdata ), - .m_axis_chdr_tlast (ep4_to_xb_tlast ), - .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), - .m_axis_chdr_tready (ep4_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep4_tdata), + .s_axis_chdr_tlast (xb_to_ep4_tlast), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid), + .s_axis_chdr_tready (xb_to_ep4_tready), + .m_axis_chdr_tdata (ep4_to_xb_tdata), + .m_axis_chdr_tlast (ep4_to_xb_tlast), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid), + .m_axis_chdr_tready (ep4_to_xb_tready), .s_axis_data_tdata ({s_ep4_in0_tdata}), .s_axis_data_tlast ({s_ep4_in0_tlast}), .s_axis_data_tvalid ({s_ep4_in0_tvalid}), @@ -535,20 +594,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep4_out0_tlast}), .m_axis_data_tvalid ({m_ep4_out0_tvalid}), .m_axis_data_tready ({m_ep4_out0_tready}), - .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), .s_axis_ctrl_tready (s_ep4_ctrl_tready), - .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), .m_axis_ctrl_tready (m_ep4_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP5 = 4096; + localparam INGRESS_BUFF_SIZE_EP5 = + REQ_BUFF_SIZE_EP5 == 0 ? 5 : + REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP5); + wire [CHDR_W-1:0] m_ep5_out0_tdata; wire m_ep5_out0_tlast; wire m_ep5_out0_tvalid; @@ -557,8 +624,8 @@ module rfnoc_image_core #( wire s_ep5_in0_tlast; wire s_ep5_in0_tvalid; wire s_ep5_in0_tready; - wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; - wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; + wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; @@ -571,23 +638,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (5), .CTRL_XBAR_PORT (6), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep5_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep5_tdata ), - .s_axis_chdr_tlast (xb_to_ep5_tlast ), - .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), - .s_axis_chdr_tready (xb_to_ep5_tready ), - .m_axis_chdr_tdata (ep5_to_xb_tdata ), - .m_axis_chdr_tlast (ep5_to_xb_tlast ), - .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), - .m_axis_chdr_tready (ep5_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep5_tdata), + .s_axis_chdr_tlast (xb_to_ep5_tlast), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid), + .s_axis_chdr_tready (xb_to_ep5_tready), + .m_axis_chdr_tdata (ep5_to_xb_tdata), + .m_axis_chdr_tlast (ep5_to_xb_tlast), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid), + .m_axis_chdr_tready (ep5_to_xb_tready), .s_axis_data_tdata ({s_ep5_in0_tdata}), .s_axis_data_tlast ({s_ep5_in0_tlast}), .s_axis_data_tvalid ({s_ep5_in0_tvalid}), @@ -596,20 +663,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep5_out0_tlast}), .m_axis_data_tvalid ({m_ep5_out0_tvalid}), .m_axis_data_tready ({m_ep5_out0_tready}), - .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), .s_axis_ctrl_tready (s_ep5_ctrl_tready), - .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), .m_axis_ctrl_tready (m_ep5_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP6 = 4096; + localparam INGRESS_BUFF_SIZE_EP6 = + REQ_BUFF_SIZE_EP6 == 0 ? 5 : + REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP6); + wire [CHDR_W-1:0] m_ep6_out0_tdata; wire m_ep6_out0_tlast; wire m_ep6_out0_tvalid; @@ -618,8 +693,8 @@ module rfnoc_image_core #( wire s_ep6_in0_tlast; wire s_ep6_in0_tvalid; wire s_ep6_in0_tready; - wire [31:0] m_ep6_ctrl_tdata , s_ep6_ctrl_tdata ; - wire m_ep6_ctrl_tlast , s_ep6_ctrl_tlast ; + wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata; + wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast; wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid; wire m_ep6_ctrl_tready, s_ep6_ctrl_tready; @@ -632,23 +707,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (6), .CTRL_XBAR_PORT (7), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep6_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep6_tdata ), - .s_axis_chdr_tlast (xb_to_ep6_tlast ), - .s_axis_chdr_tvalid (xb_to_ep6_tvalid ), - .s_axis_chdr_tready (xb_to_ep6_tready ), - .m_axis_chdr_tdata (ep6_to_xb_tdata ), - .m_axis_chdr_tlast (ep6_to_xb_tlast ), - .m_axis_chdr_tvalid (ep6_to_xb_tvalid ), - .m_axis_chdr_tready (ep6_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep6_tdata), + .s_axis_chdr_tlast (xb_to_ep6_tlast), + .s_axis_chdr_tvalid (xb_to_ep6_tvalid), + .s_axis_chdr_tready (xb_to_ep6_tready), + .m_axis_chdr_tdata (ep6_to_xb_tdata), + .m_axis_chdr_tlast (ep6_to_xb_tlast), + .m_axis_chdr_tvalid (ep6_to_xb_tvalid), + .m_axis_chdr_tready (ep6_to_xb_tready), .s_axis_data_tdata ({s_ep6_in0_tdata}), .s_axis_data_tlast ({s_ep6_in0_tlast}), .s_axis_data_tvalid ({s_ep6_in0_tvalid}), @@ -657,20 +732,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep6_out0_tlast}), .m_axis_data_tvalid ({m_ep6_out0_tvalid}), .m_axis_data_tready ({m_ep6_out0_tready}), - .s_axis_ctrl_tdata (s_ep6_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep6_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep6_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep6_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep6_ctrl_tvalid), .s_axis_ctrl_tready (s_ep6_ctrl_tready), - .m_axis_ctrl_tdata (m_ep6_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep6_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep6_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep6_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep6_ctrl_tvalid), .m_axis_ctrl_tready (m_ep6_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP7 = 4096; + localparam INGRESS_BUFF_SIZE_EP7 = + REQ_BUFF_SIZE_EP7 == 0 ? 5 : + REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP7); + wire [CHDR_W-1:0] m_ep7_out0_tdata; wire m_ep7_out0_tlast; wire m_ep7_out0_tvalid; @@ -679,8 +762,8 @@ module rfnoc_image_core #( wire s_ep7_in0_tlast; wire s_ep7_in0_tvalid; wire s_ep7_in0_tready; - wire [31:0] m_ep7_ctrl_tdata , s_ep7_ctrl_tdata ; - wire m_ep7_ctrl_tlast , s_ep7_ctrl_tlast ; + wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata; + wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast; wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid; wire m_ep7_ctrl_tready, s_ep7_ctrl_tready; @@ -693,23 +776,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (7), .CTRL_XBAR_PORT (8), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep7_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep7_tdata ), - .s_axis_chdr_tlast (xb_to_ep7_tlast ), - .s_axis_chdr_tvalid (xb_to_ep7_tvalid ), - .s_axis_chdr_tready (xb_to_ep7_tready ), - .m_axis_chdr_tdata (ep7_to_xb_tdata ), - .m_axis_chdr_tlast (ep7_to_xb_tlast ), - .m_axis_chdr_tvalid (ep7_to_xb_tvalid ), - .m_axis_chdr_tready (ep7_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep7_tdata), + .s_axis_chdr_tlast (xb_to_ep7_tlast), + .s_axis_chdr_tvalid (xb_to_ep7_tvalid), + .s_axis_chdr_tready (xb_to_ep7_tready), + .m_axis_chdr_tdata (ep7_to_xb_tdata), + .m_axis_chdr_tlast (ep7_to_xb_tlast), + .m_axis_chdr_tvalid (ep7_to_xb_tvalid), + .m_axis_chdr_tready (ep7_to_xb_tready), .s_axis_data_tdata ({s_ep7_in0_tdata}), .s_axis_data_tlast ({s_ep7_in0_tlast}), .s_axis_data_tvalid ({s_ep7_in0_tvalid}), @@ -718,58 +801,57 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep7_out0_tlast}), .m_axis_data_tvalid ({m_ep7_out0_tvalid}), .m_axis_data_tready ({m_ep7_out0_tready}), - .s_axis_ctrl_tdata (s_ep7_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep7_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep7_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep7_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep7_ctrl_tvalid), .s_axis_ctrl_tready (s_ep7_ctrl_tready), - .m_axis_ctrl_tdata (m_ep7_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep7_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep7_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep7_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep7_ctrl_tvalid), .m_axis_ctrl_tready (m_ep7_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Control Crossbar - // ---------------------------------------------------- - - wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; - wire m_core_ctrl_tlast , s_core_ctrl_tlast ; - wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; - wire m_core_ctrl_tready, s_core_ctrl_tready; - wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; - wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; - wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; - wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; - wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; - wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; - wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; - wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; - wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; - wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; - wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; - wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; - wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; - wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; - wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; - wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; - wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; - wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; - wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; - wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; - wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; - wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; - wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; - wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; - wire [31:0] m_replay0_ctrl_tdata , s_replay0_ctrl_tdata ; - wire m_replay0_ctrl_tlast , s_replay0_ctrl_tlast ; - wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; - wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata, s_duc0_ctrl_tdata; + wire m_duc0_ctrl_tlast, s_duc0_ctrl_tlast; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata, s_ddc0_ctrl_tdata; + wire m_ddc0_ctrl_tlast, s_ddc0_ctrl_tlast; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata, s_duc1_ctrl_tdata; + wire m_duc1_ctrl_tlast, s_duc1_ctrl_tlast; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata, s_ddc1_ctrl_tdata; + wire m_ddc1_ctrl_tlast, s_ddc1_ctrl_tlast; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_replay0_ctrl_tdata, s_replay0_ctrl_tdata; + wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast; + wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; + wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), @@ -793,9 +875,11 @@ module rfnoc_image_core #( .deadlock_detected() ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // RFNoC Core Kernel - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( @@ -820,12 +904,12 @@ module rfnoc_image_core #( .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), - .s_axis_ctrl_tdata (s_core_ctrl_tdata ), - .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), - .m_axis_ctrl_tdata (m_core_ctrl_tdata ), - .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), @@ -833,13 +917,15 @@ module rfnoc_image_core #( .rfnoc_core_status (rfnoc_core_status) ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Blocks - // ---------------------------------------------------- + //--------------------------------------------------------------------------- - // ---------------------------------------------------- + //----------------------------------- // duc0 - // ---------------------------------------------------- + //----------------------------------- + wire duc0_ce_clk; wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; @@ -850,44 +936,41 @@ module rfnoc_image_core #( wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tready, m_duc0_out_0_tready; - rfnoc_block_duc #( - .THIS_PORTID(2), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .NUM_HB(3), - .CIC_MAX_INTERP(255), - .MTU(MTU) + .THIS_PORTID (2), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (MTU) ) b_duc0_0 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(duc0_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), - .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), - - - .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // ddc0 - // ---------------------------------------------------- + //----------------------------------- + wire ddc0_ce_clk; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; @@ -898,44 +981,41 @@ module rfnoc_image_core #( wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; - rfnoc_block_ddc #( - .THIS_PORTID(3), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .NUM_HB(3), - .CIC_MAX_DECIM(255), - .MTU(MTU) + .THIS_PORTID (3), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (MTU) ) b_ddc0_1 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(ddc0_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), - .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), - - - .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio0 - // ---------------------------------------------------- + //----------------------------------- + wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; @@ -946,79 +1026,77 @@ module rfnoc_image_core #( wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tready, m_radio0_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio0_m_ctrlport_req_wr; - wire [ 1-1:0] radio0_m_ctrlport_req_rd; - wire [ 20-1:0] radio0_m_ctrlport_req_addr; - wire [ 32-1:0] radio0_m_ctrlport_req_data; - wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio0_m_ctrlport_req_has_time; - wire [ 64-1:0] radio0_m_ctrlport_req_time; - wire [ 1-1:0] radio0_m_ctrlport_resp_ack; - wire [ 2-1:0] radio0_m_ctrlport_resp_status; - wire [ 32-1:0] radio0_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio0_radio_time; - // x300_radio - wire [ 64-1:0] radio0_radio_rx_data; - wire [ 2-1:0] radio0_radio_rx_stb; - wire [ 2-1:0] radio0_radio_rx_running; - wire [ 64-1:0] radio0_radio_tx_data; - wire [ 2-1:0] radio0_radio_tx_stb; - wire [ 2-1:0] radio0_radio_tx_running; + // ctrl_port + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio0_radio_time; + // x300_radio + wire [ 63:0] radio0_radio_rx_data; + wire [ 1:0] radio0_radio_rx_stb; + wire [ 1:0] radio0_radio_rx_running; + wire [ 63:0] radio0_radio_tx_data; + wire [ 1:0] radio0_radio_tx_stb; + wire [ 1:0] radio0_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(4), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MTU(MTU) + .THIS_PORTID (4), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MTU (MTU) ) b_radio0_2 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio0_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), - .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), - - .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio0_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), - .radio_time(radio0_radio_time), - .radio_rx_data(radio0_radio_rx_data), - .radio_rx_stb(radio0_radio_rx_stb), - .radio_rx_running(radio0_radio_rx_running), - .radio_tx_data(radio0_radio_tx_data), - .radio_tx_stb(radio0_radio_tx_stb), - .radio_tx_running(radio0_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // duc1 - // ---------------------------------------------------- + //----------------------------------- + wire duc1_ce_clk; wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ; wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ; @@ -1029,44 +1107,41 @@ module rfnoc_image_core #( wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; wire m_duc1_out_1_tready, m_duc1_out_0_tready; - rfnoc_block_duc #( - .THIS_PORTID(5), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .NUM_HB(3), - .CIC_MAX_INTERP(255), - .MTU(MTU) + .THIS_PORTID (5), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (MTU) ) b_duc1_3 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(duc1_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), - .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), - - - .s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_duc1_in_1_tready, s_duc1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_duc1_out_1_tdata , m_duc1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_duc1_out_1_tready, m_duc1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + .s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc1_in_1_tready, s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_1_tdata , m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc1_out_1_tready, m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // ddc1 - // ---------------------------------------------------- + //----------------------------------- + wire ddc1_ce_clk; wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; @@ -1077,44 +1152,41 @@ module rfnoc_image_core #( wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; - rfnoc_block_ddc #( - .THIS_PORTID(6), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .NUM_HB(3), - .CIC_MAX_DECIM(255), - .MTU(MTU) + .THIS_PORTID (6), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (MTU) ) b_ddc1_4 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(ddc1_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), - .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), - - - .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_ddc1_in_1_tready, s_ddc1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_ddc1_out_1_tready, m_ddc1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc1_in_1_tready, s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc1_out_1_tready, m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio1 - // ---------------------------------------------------- + //----------------------------------- + wire radio1_radio_clk; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; @@ -1125,79 +1197,77 @@ module rfnoc_image_core #( wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; wire m_radio1_out_1_tready, m_radio1_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio1_m_ctrlport_req_wr; - wire [ 1-1:0] radio1_m_ctrlport_req_rd; - wire [ 20-1:0] radio1_m_ctrlport_req_addr; - wire [ 32-1:0] radio1_m_ctrlport_req_data; - wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio1_m_ctrlport_req_has_time; - wire [ 64-1:0] radio1_m_ctrlport_req_time; - wire [ 1-1:0] radio1_m_ctrlport_resp_ack; - wire [ 2-1:0] radio1_m_ctrlport_resp_status; - wire [ 32-1:0] radio1_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio1_radio_time; - // x300_radio - wire [ 64-1:0] radio1_radio_rx_data; - wire [ 2-1:0] radio1_radio_rx_stb; - wire [ 2-1:0] radio1_radio_rx_running; - wire [ 64-1:0] radio1_radio_tx_data; - wire [ 2-1:0] radio1_radio_tx_stb; - wire [ 2-1:0] radio1_radio_tx_running; + // ctrl_port + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio1_radio_time; + // x300_radio + wire [ 63:0] radio1_radio_rx_data; + wire [ 1:0] radio1_radio_rx_stb; + wire [ 1:0] radio1_radio_rx_running; + wire [ 63:0] radio1_radio_tx_data; + wire [ 1:0] radio1_radio_tx_stb; + wire [ 1:0] radio1_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(7), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MTU(MTU) + .THIS_PORTID (7), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MTU (MTU) ) b_radio1_5 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio1_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), - .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), - - .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio1_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), - .radio_time(radio1_radio_time), - .radio_rx_data(radio1_radio_rx_data), - .radio_rx_stb(radio1_radio_rx_stb), - .radio_rx_running(radio1_radio_rx_running), - .radio_tx_data(radio1_radio_tx_data), - .radio_tx_stb(radio1_radio_tx_stb), - .radio_tx_running(radio1_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // replay0 - // ---------------------------------------------------- + //----------------------------------- + wire replay0_mem_clk; wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; @@ -1208,263 +1278,264 @@ module rfnoc_image_core #( wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; - // axi_ram - wire [ 1-1:0] replay0_axi_rst; - wire [ 4-1:0] replay0_m_axi_awid; - wire [128-1:0] replay0_m_axi_awaddr; - wire [ 32-1:0] replay0_m_axi_awlen; - wire [ 12-1:0] replay0_m_axi_awsize; - wire [ 8-1:0] replay0_m_axi_awburst; - wire [ 4-1:0] replay0_m_axi_awlock; - wire [ 16-1:0] replay0_m_axi_awcache; - wire [ 12-1:0] replay0_m_axi_awprot; - wire [ 16-1:0] replay0_m_axi_awqos; - wire [ 16-1:0] replay0_m_axi_awregion; - wire [ 4-1:0] replay0_m_axi_awuser; - wire [ 4-1:0] replay0_m_axi_awvalid; - wire [ 4-1:0] replay0_m_axi_awready; - wire [256-1:0] replay0_m_axi_wdata; - wire [ 32-1:0] replay0_m_axi_wstrb; - wire [ 4-1:0] replay0_m_axi_wlast; - wire [ 4-1:0] replay0_m_axi_wuser; - wire [ 4-1:0] replay0_m_axi_wvalid; - wire [ 4-1:0] replay0_m_axi_wready; - wire [ 4-1:0] replay0_m_axi_bid; - wire [ 8-1:0] replay0_m_axi_bresp; - wire [ 4-1:0] replay0_m_axi_buser; - wire [ 4-1:0] replay0_m_axi_bvalid; - wire [ 4-1:0] replay0_m_axi_bready; - wire [ 4-1:0] replay0_m_axi_arid; - wire [128-1:0] replay0_m_axi_araddr; - wire [ 32-1:0] replay0_m_axi_arlen; - wire [ 12-1:0] replay0_m_axi_arsize; - wire [ 8-1:0] replay0_m_axi_arburst; - wire [ 4-1:0] replay0_m_axi_arlock; - wire [ 16-1:0] replay0_m_axi_arcache; - wire [ 12-1:0] replay0_m_axi_arprot; - wire [ 16-1:0] replay0_m_axi_arqos; - wire [ 16-1:0] replay0_m_axi_arregion; - wire [ 4-1:0] replay0_m_axi_aruser; - wire [ 4-1:0] replay0_m_axi_arvalid; - wire [ 4-1:0] replay0_m_axi_arready; - wire [ 4-1:0] replay0_m_axi_rid; - wire [256-1:0] replay0_m_axi_rdata; - wire [ 8-1:0] replay0_m_axi_rresp; - wire [ 4-1:0] replay0_m_axi_rlast; - wire [ 4-1:0] replay0_m_axi_ruser; - wire [ 4-1:0] replay0_m_axi_rvalid; - wire [ 4-1:0] replay0_m_axi_rready; + // axi_ram + wire [ 0:0] replay0_axi_rst; + wire [ 3:0] replay0_m_axi_awid; + wire [ 127:0] replay0_m_axi_awaddr; + wire [ 31:0] replay0_m_axi_awlen; + wire [ 11:0] replay0_m_axi_awsize; + wire [ 7:0] replay0_m_axi_awburst; + wire [ 3:0] replay0_m_axi_awlock; + wire [ 15:0] replay0_m_axi_awcache; + wire [ 11:0] replay0_m_axi_awprot; + wire [ 15:0] replay0_m_axi_awqos; + wire [ 15:0] replay0_m_axi_awregion; + wire [ 3:0] replay0_m_axi_awuser; + wire [ 3:0] replay0_m_axi_awvalid; + wire [ 3:0] replay0_m_axi_awready; + wire [ 255:0] replay0_m_axi_wdata; + wire [ 31:0] replay0_m_axi_wstrb; + wire [ 3:0] replay0_m_axi_wlast; + wire [ 3:0] replay0_m_axi_wuser; + wire [ 3:0] replay0_m_axi_wvalid; + wire [ 3:0] replay0_m_axi_wready; + wire [ 3:0] replay0_m_axi_bid; + wire [ 7:0] replay0_m_axi_bresp; + wire [ 3:0] replay0_m_axi_buser; + wire [ 3:0] replay0_m_axi_bvalid; + wire [ 3:0] replay0_m_axi_bready; + wire [ 3:0] replay0_m_axi_arid; + wire [ 127:0] replay0_m_axi_araddr; + wire [ 31:0] replay0_m_axi_arlen; + wire [ 11:0] replay0_m_axi_arsize; + wire [ 7:0] replay0_m_axi_arburst; + wire [ 3:0] replay0_m_axi_arlock; + wire [ 15:0] replay0_m_axi_arcache; + wire [ 11:0] replay0_m_axi_arprot; + wire [ 15:0] replay0_m_axi_arqos; + wire [ 15:0] replay0_m_axi_arregion; + wire [ 3:0] replay0_m_axi_aruser; + wire [ 3:0] replay0_m_axi_arvalid; + wire [ 3:0] replay0_m_axi_arready; + wire [ 3:0] replay0_m_axi_rid; + wire [ 255:0] replay0_m_axi_rdata; + wire [ 7:0] replay0_m_axi_rresp; + wire [ 3:0] replay0_m_axi_rlast; + wire [ 3:0] replay0_m_axi_ruser; + wire [ 3:0] replay0_m_axi_rvalid; + wire [ 3:0] replay0_m_axi_rready; rfnoc_block_replay #( - .THIS_PORTID(8), - .CHDR_W(CHDR_W), - .NUM_PORTS(4), - .MEM_ADDR_W(31), - .MEM_DATA_W(64), - .MTU(MTU) + .THIS_PORTID (8), + .CHDR_W (CHDR_W), + .NUM_PORTS (4), + .MEM_ADDR_W (31), + .MEM_DATA_W (64), + .MTU (MTU) ) b_replay0_6 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk(replay0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), - .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), - - .axi_rst(replay0_axi_rst), - .m_axi_awid(replay0_m_axi_awid), - .m_axi_awaddr(replay0_m_axi_awaddr), - .m_axi_awlen(replay0_m_axi_awlen), - .m_axi_awsize(replay0_m_axi_awsize), - .m_axi_awburst(replay0_m_axi_awburst), - .m_axi_awlock(replay0_m_axi_awlock), - .m_axi_awcache(replay0_m_axi_awcache), - .m_axi_awprot(replay0_m_axi_awprot), - .m_axi_awqos(replay0_m_axi_awqos), - .m_axi_awregion(replay0_m_axi_awregion), - .m_axi_awuser(replay0_m_axi_awuser), - .m_axi_awvalid(replay0_m_axi_awvalid), - .m_axi_awready(replay0_m_axi_awready), - .m_axi_wdata(replay0_m_axi_wdata), - .m_axi_wstrb(replay0_m_axi_wstrb), - .m_axi_wlast(replay0_m_axi_wlast), - .m_axi_wuser(replay0_m_axi_wuser), - .m_axi_wvalid(replay0_m_axi_wvalid), - .m_axi_wready(replay0_m_axi_wready), - .m_axi_bid(replay0_m_axi_bid), - .m_axi_bresp(replay0_m_axi_bresp), - .m_axi_buser(replay0_m_axi_buser), - .m_axi_bvalid(replay0_m_axi_bvalid), - .m_axi_bready(replay0_m_axi_bready), - .m_axi_arid(replay0_m_axi_arid), - .m_axi_araddr(replay0_m_axi_araddr), - .m_axi_arlen(replay0_m_axi_arlen), - .m_axi_arsize(replay0_m_axi_arsize), - .m_axi_arburst(replay0_m_axi_arburst), - .m_axi_arlock(replay0_m_axi_arlock), - .m_axi_arcache(replay0_m_axi_arcache), - .m_axi_arprot(replay0_m_axi_arprot), - .m_axi_arqos(replay0_m_axi_arqos), - .m_axi_arregion(replay0_m_axi_arregion), - .m_axi_aruser(replay0_m_axi_aruser), - .m_axi_arvalid(replay0_m_axi_arvalid), - .m_axi_arready(replay0_m_axi_arready), - .m_axi_rid(replay0_m_axi_rid), - .m_axi_rdata(replay0_m_axi_rdata), - .m_axi_rresp(replay0_m_axi_rresp), - .m_axi_rlast(replay0_m_axi_rlast), - .m_axi_ruser(replay0_m_axi_ruser), - .m_axi_rvalid(replay0_m_axi_rvalid), - .m_axi_rready(replay0_m_axi_rready), - - .s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (replay0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), + .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), + .axi_rst (replay0_axi_rst), + .m_axi_awid (replay0_m_axi_awid), + .m_axi_awaddr (replay0_m_axi_awaddr), + .m_axi_awlen (replay0_m_axi_awlen), + .m_axi_awsize (replay0_m_axi_awsize), + .m_axi_awburst (replay0_m_axi_awburst), + .m_axi_awlock (replay0_m_axi_awlock), + .m_axi_awcache (replay0_m_axi_awcache), + .m_axi_awprot (replay0_m_axi_awprot), + .m_axi_awqos (replay0_m_axi_awqos), + .m_axi_awregion (replay0_m_axi_awregion), + .m_axi_awuser (replay0_m_axi_awuser), + .m_axi_awvalid (replay0_m_axi_awvalid), + .m_axi_awready (replay0_m_axi_awready), + .m_axi_wdata (replay0_m_axi_wdata), + .m_axi_wstrb (replay0_m_axi_wstrb), + .m_axi_wlast (replay0_m_axi_wlast), + .m_axi_wuser (replay0_m_axi_wuser), + .m_axi_wvalid (replay0_m_axi_wvalid), + .m_axi_wready (replay0_m_axi_wready), + .m_axi_bid (replay0_m_axi_bid), + .m_axi_bresp (replay0_m_axi_bresp), + .m_axi_buser (replay0_m_axi_buser), + .m_axi_bvalid (replay0_m_axi_bvalid), + .m_axi_bready (replay0_m_axi_bready), + .m_axi_arid (replay0_m_axi_arid), + .m_axi_araddr (replay0_m_axi_araddr), + .m_axi_arlen (replay0_m_axi_arlen), + .m_axi_arsize (replay0_m_axi_arsize), + .m_axi_arburst (replay0_m_axi_arburst), + .m_axi_arlock (replay0_m_axi_arlock), + .m_axi_arcache (replay0_m_axi_arcache), + .m_axi_arprot (replay0_m_axi_arprot), + .m_axi_arqos (replay0_m_axi_arqos), + .m_axi_arregion (replay0_m_axi_arregion), + .m_axi_aruser (replay0_m_axi_aruser), + .m_axi_arvalid (replay0_m_axi_arvalid), + .m_axi_arready (replay0_m_axi_arready), + .m_axi_rid (replay0_m_axi_rid), + .m_axi_rdata (replay0_m_axi_rdata), + .m_axi_rresp (replay0_m_axi_rresp), + .m_axi_rlast (replay0_m_axi_rlast), + .m_axi_ruser (replay0_m_axi_ruser), + .m_axi_rvalid (replay0_m_axi_rvalid), + .m_axi_rready (replay0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Static Router - // ---------------------------------------------------- - assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; - assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + //--------------------------------------------------------------------------- + + assign s_duc0_in_0_tdata = m_ep0_out0_tdata; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_duc0_in_0_tready; - assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; - assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast; assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; assign m_duc0_out_0_tready = s_radio0_in_0_tready; - assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; - assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast; assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ddc0_in_0_tready; - assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; - assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast; assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; assign m_ddc0_out_0_tready = s_ep0_in0_tready; - assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; - assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tdata = m_ep1_out0_tdata; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast; assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; assign m_ep1_out0_tready = s_duc0_in_1_tready; - assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; - assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast; assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; assign m_duc0_out_1_tready = s_radio0_in_1_tready; - assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; - assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast; assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; assign m_radio0_out_1_tready = s_ddc0_in_1_tready; - assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; - assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast; assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; assign m_ddc0_out_1_tready = s_ep1_in0_tready; - assign s_duc1_in_0_tdata = m_ep2_out0_tdata ; - assign s_duc1_in_0_tlast = m_ep2_out0_tlast ; + assign s_duc1_in_0_tdata = m_ep2_out0_tdata; + assign s_duc1_in_0_tlast = m_ep2_out0_tlast; assign s_duc1_in_0_tvalid = m_ep2_out0_tvalid; assign m_ep2_out0_tready = s_duc1_in_0_tready; - assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; - assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast; assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; assign m_duc1_out_0_tready = s_radio1_in_0_tready; - assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; - assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast; assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; assign m_radio1_out_0_tready = s_ddc1_in_0_tready; - assign s_ep2_in0_tdata = m_ddc1_out_0_tdata ; - assign s_ep2_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep2_in0_tdata = m_ddc1_out_0_tdata; + assign s_ep2_in0_tlast = m_ddc1_out_0_tlast; assign s_ep2_in0_tvalid = m_ddc1_out_0_tvalid; assign m_ddc1_out_0_tready = s_ep2_in0_tready; - assign s_duc1_in_1_tdata = m_ep3_out0_tdata ; - assign s_duc1_in_1_tlast = m_ep3_out0_tlast ; + assign s_duc1_in_1_tdata = m_ep3_out0_tdata; + assign s_duc1_in_1_tlast = m_ep3_out0_tlast; assign s_duc1_in_1_tvalid = m_ep3_out0_tvalid; assign m_ep3_out0_tready = s_duc1_in_1_tready; - assign s_radio1_in_1_tdata = m_duc1_out_1_tdata ; - assign s_radio1_in_1_tlast = m_duc1_out_1_tlast ; + assign s_radio1_in_1_tdata = m_duc1_out_1_tdata; + assign s_radio1_in_1_tlast = m_duc1_out_1_tlast; assign s_radio1_in_1_tvalid = m_duc1_out_1_tvalid; assign m_duc1_out_1_tready = s_radio1_in_1_tready; - assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata ; - assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast ; + assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata; + assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast; assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid; assign m_radio1_out_1_tready = s_ddc1_in_1_tready; - assign s_ep3_in0_tdata = m_ddc1_out_1_tdata ; - assign s_ep3_in0_tlast = m_ddc1_out_1_tlast ; + assign s_ep3_in0_tdata = m_ddc1_out_1_tdata; + assign s_ep3_in0_tlast = m_ddc1_out_1_tlast; assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid; assign m_ddc1_out_1_tready = s_ep3_in0_tready; - assign s_replay0_in_0_tdata = m_ep4_out0_tdata ; - assign s_replay0_in_0_tlast = m_ep4_out0_tlast ; + assign s_replay0_in_0_tdata = m_ep4_out0_tdata; + assign s_replay0_in_0_tlast = m_ep4_out0_tlast; assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid; assign m_ep4_out0_tready = s_replay0_in_0_tready; - assign s_ep4_in0_tdata = m_replay0_out_0_tdata ; - assign s_ep4_in0_tlast = m_replay0_out_0_tlast ; + assign s_ep4_in0_tdata = m_replay0_out_0_tdata; + assign s_ep4_in0_tlast = m_replay0_out_0_tlast; assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid; assign m_replay0_out_0_tready = s_ep4_in0_tready; - assign s_replay0_in_1_tdata = m_ep5_out0_tdata ; - assign s_replay0_in_1_tlast = m_ep5_out0_tlast ; + assign s_replay0_in_1_tdata = m_ep5_out0_tdata; + assign s_replay0_in_1_tlast = m_ep5_out0_tlast; assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid; assign m_ep5_out0_tready = s_replay0_in_1_tready; - assign s_ep5_in0_tdata = m_replay0_out_1_tdata ; - assign s_ep5_in0_tlast = m_replay0_out_1_tlast ; + assign s_ep5_in0_tdata = m_replay0_out_1_tdata; + assign s_ep5_in0_tlast = m_replay0_out_1_tlast; assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid; assign m_replay0_out_1_tready = s_ep5_in0_tready; - assign s_replay0_in_2_tdata = m_ep6_out0_tdata ; - assign s_replay0_in_2_tlast = m_ep6_out0_tlast ; + assign s_replay0_in_2_tdata = m_ep6_out0_tdata; + assign s_replay0_in_2_tlast = m_ep6_out0_tlast; assign s_replay0_in_2_tvalid = m_ep6_out0_tvalid; assign m_ep6_out0_tready = s_replay0_in_2_tready; - assign s_ep6_in0_tdata = m_replay0_out_2_tdata ; - assign s_ep6_in0_tlast = m_replay0_out_2_tlast ; + assign s_ep6_in0_tdata = m_replay0_out_2_tdata; + assign s_ep6_in0_tlast = m_replay0_out_2_tlast; assign s_ep6_in0_tvalid = m_replay0_out_2_tvalid; assign m_replay0_out_2_tready = s_ep6_in0_tready; - assign s_replay0_in_3_tdata = m_ep7_out0_tdata ; - assign s_replay0_in_3_tlast = m_ep7_out0_tlast ; + assign s_replay0_in_3_tdata = m_ep7_out0_tdata; + assign s_replay0_in_3_tlast = m_ep7_out0_tlast; assign s_replay0_in_3_tvalid = m_ep7_out0_tvalid; assign m_ep7_out0_tready = s_replay0_in_3_tready; - assign s_ep7_in0_tdata = m_replay0_out_3_tdata ; - assign s_ep7_in0_tlast = m_replay0_out_3_tlast ; + assign s_ep7_in0_tdata = m_replay0_out_3_tdata; + assign s_ep7_in0_tlast = m_replay0_out_3_tlast; assign s_ep7_in0_tvalid = m_replay0_out_3_tvalid; assign m_replay0_out_3_tready = s_ep7_in0_tready; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Unused Ports - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Clock Domains - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign radio0_radio_clk = radio_clk; assign ddc0_ce_clk = rfnoc_chdr_clk; assign duc0_ce_clk = rfnoc_chdr_clk; @@ -1474,9 +1545,10 @@ module rfnoc_image_core #( assign replay0_mem_clk = dram_clk; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // IO Port Connection - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; @@ -1566,3 +1638,6 @@ module rfnoc_image_core #( assign radio1_radio_time = radio_time; endmodule + + +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh new file mode 100644 index 000000000..9ea3cafc5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh @@ -0,0 +1,21 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for n310) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:09.279594 +// Source: n310_rfnoc_image_core.yml +// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284 +// + +`define CHDR_WIDTH 64 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.v b/fpga/usrp3/top/n3xx/n320_bist_image_core.v index 4a080f2a8..142f46a09 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_image_core.v +++ b/fpga/usrp3/top/n3xx/n320_bist_image_core.v @@ -1,19 +1,32 @@ // -// Copyright 2020 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // - // Module: rfnoc_image_core (for n320) -// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) -// Re-running that tool will overwrite this file! -// File generated on: 2020-07-27T12:39:13.318449 +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:06.226381 // Source: n320_bist_image_core.yml -// Source SHA256: b5d9a0fb5302f7bfadf36c9d6cdcc70814aa1062f82396378a2976faba6ba010 +// Source SHA256: d384cf18372dd4b674466793e7cf30abeb4f3ef658d466be7007a9b7b8af7241 +// + +`default_nettype none + module rfnoc_image_core #( - parameter [15:0] PROTOVER = {8'd1, 8'd0} -)( + parameter CHDR_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( // Clocks input wire chdr_aclk, input wire ctrl_aclk, @@ -21,131 +34,136 @@ module rfnoc_image_core #( input wire radio_clk, input wire dram_clk, // Basic - input wire [15:0] device_id, -//// IO ports ////////////////////////////////// -// ctrlport_radio0 - output wire [ 1-1:0] m_ctrlport_radio0_req_wr, - output wire [ 1-1:0] m_ctrlport_radio0_req_rd, - output wire [ 20-1:0] m_ctrlport_radio0_req_addr, - output wire [ 32-1:0] m_ctrlport_radio0_req_data, - output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio0_req_time, - input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio0_resp_status, - input wire [ 32-1:0] m_ctrlport_radio0_resp_data, -// ctrlport_radio1 - output wire [ 1-1:0] m_ctrlport_radio1_req_wr, - output wire [ 1-1:0] m_ctrlport_radio1_req_rd, - output wire [ 20-1:0] m_ctrlport_radio1_req_addr, - output wire [ 32-1:0] m_ctrlport_radio1_req_data, - output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio1_req_time, - input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio1_resp_status, - input wire [ 32-1:0] m_ctrlport_radio1_resp_data, -// time_keeper - input wire [ 64-1:0] radio_time, -// radio_ch0 - input wire [ 32-1:0] radio_rx_data_radio0, - input wire [ 1-1:0] radio_rx_stb_radio0, - output wire [ 1-1:0] radio_rx_running_radio0, - output wire [ 32-1:0] radio_tx_data_radio0, - input wire [ 1-1:0] radio_tx_stb_radio0, - output wire [ 1-1:0] radio_tx_running_radio0, -// radio_ch1 - input wire [ 32-1:0] radio_rx_data_radio1, - input wire [ 1-1:0] radio_rx_stb_radio1, - output wire [ 1-1:0] radio_rx_running_radio1, - output wire [ 32-1:0] radio_tx_data_radio1, - input wire [ 1-1:0] radio_tx_stb_radio1, - output wire [ 1-1:0] radio_tx_running_radio1, -// dram - input wire [ 1-1:0] axi_rst, - output wire [ 4-1:0] m_axi_awid, - output wire [128-1:0] m_axi_awaddr, - output wire [ 32-1:0] m_axi_awlen, - output wire [ 12-1:0] m_axi_awsize, - output wire [ 8-1:0] m_axi_awburst, - output wire [ 4-1:0] m_axi_awlock, - output wire [ 16-1:0] m_axi_awcache, - output wire [ 12-1:0] m_axi_awprot, - output wire [ 16-1:0] m_axi_awqos, - output wire [ 16-1:0] m_axi_awregion, - output wire [ 4-1:0] m_axi_awuser, - output wire [ 4-1:0] m_axi_awvalid, - input wire [ 4-1:0] m_axi_awready, - output wire [256-1:0] m_axi_wdata, - output wire [ 32-1:0] m_axi_wstrb, - output wire [ 4-1:0] m_axi_wlast, - output wire [ 4-1:0] m_axi_wuser, - output wire [ 4-1:0] m_axi_wvalid, - input wire [ 4-1:0] m_axi_wready, - input wire [ 4-1:0] m_axi_bid, - input wire [ 8-1:0] m_axi_bresp, - input wire [ 4-1:0] m_axi_buser, - input wire [ 4-1:0] m_axi_bvalid, - output wire [ 4-1:0] m_axi_bready, - output wire [ 4-1:0] m_axi_arid, - output wire [128-1:0] m_axi_araddr, - output wire [ 32-1:0] m_axi_arlen, - output wire [ 12-1:0] m_axi_arsize, - output wire [ 8-1:0] m_axi_arburst, - output wire [ 4-1:0] m_axi_arlock, - output wire [ 16-1:0] m_axi_arcache, - output wire [ 12-1:0] m_axi_arprot, - output wire [ 16-1:0] m_axi_arqos, - output wire [ 16-1:0] m_axi_arregion, - output wire [ 4-1:0] m_axi_aruser, - output wire [ 4-1:0] m_axi_arvalid, - input wire [ 4-1:0] m_axi_arready, - input wire [ 4-1:0] m_axi_rid, - input wire [256-1:0] m_axi_rdata, - input wire [ 8-1:0] m_axi_rresp, - input wire [ 4-1:0] m_axi_rlast, - input wire [ 4-1:0] m_axi_ruser, - input wire [ 4-1:0] m_axi_rvalid, - output wire [ 4-1:0] m_axi_rready, - // Transport 0 (eth0 1G) - input wire [64-1:0] s_eth0_tdata, - input wire s_eth0_tlast, - input wire s_eth0_tvalid, - output wire s_eth0_tready, - output wire [64-1:0] m_eth0_tdata, - output wire m_eth0_tlast, - output wire m_eth0_tvalid, - input wire m_eth0_tready, - // Transport 1 (eth1 10G) - input wire [64-1:0] s_eth1_tdata, - input wire s_eth1_tlast, - input wire s_eth1_tvalid, - output wire s_eth1_tready, - output wire [64-1:0] m_eth1_tdata, - output wire m_eth1_tlast, - output wire m_eth1_tvalid, - input wire m_eth1_tready, - // Transport 2 (dma dma) - input wire [64-1:0] s_dma_tdata, - input wire s_dma_tlast, - input wire s_dma_tvalid, - output wire s_dma_tready, - output wire [64-1:0] m_dma_tdata, - output wire m_dma_tlast, - output wire m_dma_tvalid, - input wire m_dma_tready + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time_keeper + input wire [ 63:0] radio_time, + // radio_ch0 + input wire [ 31:0] radio_rx_data_radio0, + input wire [ 0:0] radio_rx_stb_radio0, + output wire [ 0:0] radio_rx_running_radio0, + output wire [ 31:0] radio_tx_data_radio0, + input wire [ 0:0] radio_tx_stb_radio0, + output wire [ 0:0] radio_tx_running_radio0, + // radio_ch1 + input wire [ 31:0] radio_rx_data_radio1, + input wire [ 0:0] radio_rx_stb_radio1, + output wire [ 0:0] radio_rx_running_radio1, + output wire [ 31:0] radio_tx_data_radio1, + input wire [ 0:0] radio_tx_stb_radio1, + output wire [ 0:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [CHDR_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [CHDR_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [CHDR_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [CHDR_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma) + input wire [CHDR_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [CHDR_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready ); - localparam CHDR_W = 64; - localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // CHDR Crossbar - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; @@ -194,12 +212,12 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), - .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tdata ({ep5_to_xb_tdata , ep4_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep5_to_xb_tlast , ep4_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }), .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), - .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tdata ({xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }), .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), @@ -208,9 +226,18 @@ module rfnoc_image_core #( .ext_rtcfg_ack () ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Stream Endpoints - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 32768; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; @@ -220,8 +247,8 @@ module rfnoc_image_core #( wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; - wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; - wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; @@ -234,23 +261,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep0_tdata ), - .s_axis_chdr_tlast (xb_to_ep0_tlast ), - .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), - .s_axis_chdr_tready (xb_to_ep0_tready ), - .m_axis_chdr_tdata (ep0_to_xb_tdata ), - .m_axis_chdr_tlast (ep0_to_xb_tlast ), - .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), - .m_axis_chdr_tready (ep0_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), @@ -259,20 +286,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), - .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), - .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 32768; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; @@ -281,8 +316,8 @@ module rfnoc_image_core #( wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; - wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; - wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; @@ -295,23 +330,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep1_tdata ), - .s_axis_chdr_tlast (xb_to_ep1_tlast ), - .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), - .s_axis_chdr_tready (xb_to_ep1_tready ), - .m_axis_chdr_tdata (ep1_to_xb_tdata ), - .m_axis_chdr_tlast (ep1_to_xb_tlast ), - .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), - .m_axis_chdr_tready (ep1_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), @@ -320,20 +355,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), - .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), - .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP4 = 32768; + localparam INGRESS_BUFF_SIZE_EP4 = + REQ_BUFF_SIZE_EP4 == 0 ? 5 : + REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP4); + wire [CHDR_W-1:0] m_ep4_out0_tdata; wire m_ep4_out0_tlast; wire m_ep4_out0_tvalid; @@ -342,8 +385,8 @@ module rfnoc_image_core #( wire s_ep4_in0_tlast; wire s_ep4_in0_tvalid; wire s_ep4_in0_tready; - wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; - wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; + wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; @@ -356,23 +399,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep4_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep4_tdata ), - .s_axis_chdr_tlast (xb_to_ep4_tlast ), - .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), - .s_axis_chdr_tready (xb_to_ep4_tready ), - .m_axis_chdr_tdata (ep4_to_xb_tdata ), - .m_axis_chdr_tlast (ep4_to_xb_tlast ), - .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), - .m_axis_chdr_tready (ep4_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep4_tdata), + .s_axis_chdr_tlast (xb_to_ep4_tlast), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid), + .s_axis_chdr_tready (xb_to_ep4_tready), + .m_axis_chdr_tdata (ep4_to_xb_tdata), + .m_axis_chdr_tlast (ep4_to_xb_tlast), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid), + .m_axis_chdr_tready (ep4_to_xb_tready), .s_axis_data_tdata ({s_ep4_in0_tdata}), .s_axis_data_tlast ({s_ep4_in0_tlast}), .s_axis_data_tvalid ({s_ep4_in0_tvalid}), @@ -381,20 +424,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep4_out0_tlast}), .m_axis_data_tvalid ({m_ep4_out0_tvalid}), .m_axis_data_tready ({m_ep4_out0_tready}), - .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), .s_axis_ctrl_tready (s_ep4_ctrl_tready), - .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), .m_axis_ctrl_tready (m_ep4_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP5 = 32768; + localparam INGRESS_BUFF_SIZE_EP5 = + REQ_BUFF_SIZE_EP5 == 0 ? 5 : + REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP5); + wire [CHDR_W-1:0] m_ep5_out0_tdata; wire m_ep5_out0_tlast; wire m_ep5_out0_tvalid; @@ -403,8 +454,8 @@ module rfnoc_image_core #( wire s_ep5_in0_tlast; wire s_ep5_in0_tvalid; wire s_ep5_in0_tready; - wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; - wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; + wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; @@ -417,23 +468,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), - .INGRESS_BUFF_SIZE (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep5_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep5_tdata ), - .s_axis_chdr_tlast (xb_to_ep5_tlast ), - .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), - .s_axis_chdr_tready (xb_to_ep5_tready ), - .m_axis_chdr_tdata (ep5_to_xb_tdata ), - .m_axis_chdr_tlast (ep5_to_xb_tlast ), - .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), - .m_axis_chdr_tready (ep5_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep5_tdata), + .s_axis_chdr_tlast (xb_to_ep5_tlast), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid), + .s_axis_chdr_tready (xb_to_ep5_tready), + .m_axis_chdr_tdata (ep5_to_xb_tdata), + .m_axis_chdr_tlast (ep5_to_xb_tlast), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid), + .m_axis_chdr_tready (ep5_to_xb_tready), .s_axis_data_tdata ({s_ep5_in0_tdata}), .s_axis_data_tlast ({s_ep5_in0_tlast}), .s_axis_data_tvalid ({s_ep5_in0_tvalid}), @@ -442,42 +493,41 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep5_out0_tlast}), .m_axis_data_tvalid ({m_ep5_out0_tvalid}), .m_axis_data_tready ({m_ep5_out0_tready}), - .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), .s_axis_ctrl_tready (s_ep5_ctrl_tready), - .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), .m_axis_ctrl_tready (m_ep5_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Control Crossbar - // ---------------------------------------------------- - - wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; - wire m_core_ctrl_tlast , s_core_ctrl_tlast ; - wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; - wire m_core_ctrl_tready, s_core_ctrl_tready; - wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; - wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; - wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; - wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; - wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; - wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; - wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; - wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; - wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; - wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; - wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; - wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata, s_fifo0_ctrl_tdata; + wire m_fifo0_ctrl_tlast, s_fifo0_ctrl_tlast; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), @@ -501,9 +551,11 @@ module rfnoc_image_core #( .deadlock_detected() ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // RFNoC Core Kernel - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( @@ -528,12 +580,12 @@ module rfnoc_image_core #( .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), - .s_axis_ctrl_tdata (s_core_ctrl_tdata ), - .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), - .m_axis_ctrl_tdata (m_core_ctrl_tdata ), - .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), @@ -541,13 +593,15 @@ module rfnoc_image_core #( .rfnoc_core_status (rfnoc_core_status) ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Blocks - // ---------------------------------------------------- + //--------------------------------------------------------------------------- - // ---------------------------------------------------- + //----------------------------------- // radio0 - // ---------------------------------------------------- + //----------------------------------- + wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_0_tdata ; wire s_radio0_in_0_tlast ; @@ -558,79 +612,77 @@ module rfnoc_image_core #( wire m_radio0_out_0_tvalid; wire m_radio0_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio0_m_ctrlport_req_wr; - wire [ 1-1:0] radio0_m_ctrlport_req_rd; - wire [ 20-1:0] radio0_m_ctrlport_req_addr; - wire [ 32-1:0] radio0_m_ctrlport_req_data; - wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio0_m_ctrlport_req_has_time; - wire [ 64-1:0] radio0_m_ctrlport_req_time; - wire [ 1-1:0] radio0_m_ctrlport_resp_ack; - wire [ 2-1:0] radio0_m_ctrlport_resp_status; - wire [ 32-1:0] radio0_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio0_radio_time; - // radio_iface - wire [ 32-1:0] radio0_radio_rx_data; - wire [ 1-1:0] radio0_radio_rx_stb; - wire [ 1-1:0] radio0_radio_rx_running; - wire [ 32-1:0] radio0_radio_tx_data; - wire [ 1-1:0] radio0_radio_tx_stb; - wire [ 1-1:0] radio0_radio_tx_running; + // ctrl_port + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio0_radio_time; + // radio_iface + wire [ 31:0] radio0_radio_rx_data; + wire [ 0:0] radio0_radio_rx_stb; + wire [ 0:0] radio0_radio_rx_running; + wire [ 31:0] radio0_radio_tx_data; + wire [ 0:0] radio0_radio_tx_stb; + wire [ 0:0] radio0_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(2), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .MTU(MTU) + .THIS_PORTID (2), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .MTU (MTU) ) b_radio0_0 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio0_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), - .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), - - .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio0_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), - .radio_time(radio0_radio_time), - .radio_rx_data(radio0_radio_rx_data), - .radio_rx_stb(radio0_radio_rx_stb), - .radio_rx_running(radio0_radio_rx_running), - .radio_tx_data(radio0_radio_tx_data), - .radio_tx_stb(radio0_radio_tx_stb), - .radio_tx_running(radio0_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio1 - // ---------------------------------------------------- + //----------------------------------- + wire radio1_radio_clk; wire [CHDR_W-1:0] s_radio1_in_0_tdata ; wire s_radio1_in_0_tlast ; @@ -641,79 +693,77 @@ module rfnoc_image_core #( wire m_radio1_out_0_tvalid; wire m_radio1_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio1_m_ctrlport_req_wr; - wire [ 1-1:0] radio1_m_ctrlport_req_rd; - wire [ 20-1:0] radio1_m_ctrlport_req_addr; - wire [ 32-1:0] radio1_m_ctrlport_req_data; - wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio1_m_ctrlport_req_has_time; - wire [ 64-1:0] radio1_m_ctrlport_req_time; - wire [ 1-1:0] radio1_m_ctrlport_resp_ack; - wire [ 2-1:0] radio1_m_ctrlport_resp_status; - wire [ 32-1:0] radio1_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio1_radio_time; - // radio_iface - wire [ 32-1:0] radio1_radio_rx_data; - wire [ 1-1:0] radio1_radio_rx_stb; - wire [ 1-1:0] radio1_radio_rx_running; - wire [ 32-1:0] radio1_radio_tx_data; - wire [ 1-1:0] radio1_radio_tx_stb; - wire [ 1-1:0] radio1_radio_tx_running; + // ctrl_port + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio1_radio_time; + // radio_iface + wire [ 31:0] radio1_radio_rx_data; + wire [ 0:0] radio1_radio_rx_stb; + wire [ 0:0] radio1_radio_rx_running; + wire [ 31:0] radio1_radio_tx_data; + wire [ 0:0] radio1_radio_tx_stb; + wire [ 0:0] radio1_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(3), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .MTU(MTU) + .THIS_PORTID (3), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .MTU (MTU) ) b_radio1_1 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio1_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), - .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), - - .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio1_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), - .radio_time(radio1_radio_time), - .radio_rx_data(radio1_radio_rx_data), - .radio_rx_stb(radio1_radio_rx_stb), - .radio_rx_running(radio1_radio_rx_running), - .radio_tx_data(radio1_radio_tx_data), - .radio_tx_stb(radio1_radio_tx_stb), - .radio_tx_running(radio1_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // fifo0 - // ---------------------------------------------------- + //----------------------------------- + wire fifo0_mem_clk; wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; @@ -724,182 +774,181 @@ module rfnoc_image_core #( wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; - // axi_ram - wire [ 1-1:0] fifo0_axi_rst; - wire [ 4-1:0] fifo0_m_axi_awid; - wire [128-1:0] fifo0_m_axi_awaddr; - wire [ 32-1:0] fifo0_m_axi_awlen; - wire [ 12-1:0] fifo0_m_axi_awsize; - wire [ 8-1:0] fifo0_m_axi_awburst; - wire [ 4-1:0] fifo0_m_axi_awlock; - wire [ 16-1:0] fifo0_m_axi_awcache; - wire [ 12-1:0] fifo0_m_axi_awprot; - wire [ 16-1:0] fifo0_m_axi_awqos; - wire [ 16-1:0] fifo0_m_axi_awregion; - wire [ 4-1:0] fifo0_m_axi_awuser; - wire [ 4-1:0] fifo0_m_axi_awvalid; - wire [ 4-1:0] fifo0_m_axi_awready; - wire [256-1:0] fifo0_m_axi_wdata; - wire [ 32-1:0] fifo0_m_axi_wstrb; - wire [ 4-1:0] fifo0_m_axi_wlast; - wire [ 4-1:0] fifo0_m_axi_wuser; - wire [ 4-1:0] fifo0_m_axi_wvalid; - wire [ 4-1:0] fifo0_m_axi_wready; - wire [ 4-1:0] fifo0_m_axi_bid; - wire [ 8-1:0] fifo0_m_axi_bresp; - wire [ 4-1:0] fifo0_m_axi_buser; - wire [ 4-1:0] fifo0_m_axi_bvalid; - wire [ 4-1:0] fifo0_m_axi_bready; - wire [ 4-1:0] fifo0_m_axi_arid; - wire [128-1:0] fifo0_m_axi_araddr; - wire [ 32-1:0] fifo0_m_axi_arlen; - wire [ 12-1:0] fifo0_m_axi_arsize; - wire [ 8-1:0] fifo0_m_axi_arburst; - wire [ 4-1:0] fifo0_m_axi_arlock; - wire [ 16-1:0] fifo0_m_axi_arcache; - wire [ 12-1:0] fifo0_m_axi_arprot; - wire [ 16-1:0] fifo0_m_axi_arqos; - wire [ 16-1:0] fifo0_m_axi_arregion; - wire [ 4-1:0] fifo0_m_axi_aruser; - wire [ 4-1:0] fifo0_m_axi_arvalid; - wire [ 4-1:0] fifo0_m_axi_arready; - wire [ 4-1:0] fifo0_m_axi_rid; - wire [256-1:0] fifo0_m_axi_rdata; - wire [ 8-1:0] fifo0_m_axi_rresp; - wire [ 4-1:0] fifo0_m_axi_rlast; - wire [ 4-1:0] fifo0_m_axi_ruser; - wire [ 4-1:0] fifo0_m_axi_rvalid; - wire [ 4-1:0] fifo0_m_axi_rready; + // axi_ram + wire [ 0:0] fifo0_axi_rst; + wire [ 3:0] fifo0_m_axi_awid; + wire [ 127:0] fifo0_m_axi_awaddr; + wire [ 31:0] fifo0_m_axi_awlen; + wire [ 11:0] fifo0_m_axi_awsize; + wire [ 7:0] fifo0_m_axi_awburst; + wire [ 3:0] fifo0_m_axi_awlock; + wire [ 15:0] fifo0_m_axi_awcache; + wire [ 11:0] fifo0_m_axi_awprot; + wire [ 15:0] fifo0_m_axi_awqos; + wire [ 15:0] fifo0_m_axi_awregion; + wire [ 3:0] fifo0_m_axi_awuser; + wire [ 3:0] fifo0_m_axi_awvalid; + wire [ 3:0] fifo0_m_axi_awready; + wire [ 255:0] fifo0_m_axi_wdata; + wire [ 31:0] fifo0_m_axi_wstrb; + wire [ 3:0] fifo0_m_axi_wlast; + wire [ 3:0] fifo0_m_axi_wuser; + wire [ 3:0] fifo0_m_axi_wvalid; + wire [ 3:0] fifo0_m_axi_wready; + wire [ 3:0] fifo0_m_axi_bid; + wire [ 7:0] fifo0_m_axi_bresp; + wire [ 3:0] fifo0_m_axi_buser; + wire [ 3:0] fifo0_m_axi_bvalid; + wire [ 3:0] fifo0_m_axi_bready; + wire [ 3:0] fifo0_m_axi_arid; + wire [ 127:0] fifo0_m_axi_araddr; + wire [ 31:0] fifo0_m_axi_arlen; + wire [ 11:0] fifo0_m_axi_arsize; + wire [ 7:0] fifo0_m_axi_arburst; + wire [ 3:0] fifo0_m_axi_arlock; + wire [ 15:0] fifo0_m_axi_arcache; + wire [ 11:0] fifo0_m_axi_arprot; + wire [ 15:0] fifo0_m_axi_arqos; + wire [ 15:0] fifo0_m_axi_arregion; + wire [ 3:0] fifo0_m_axi_aruser; + wire [ 3:0] fifo0_m_axi_arvalid; + wire [ 3:0] fifo0_m_axi_arready; + wire [ 3:0] fifo0_m_axi_rid; + wire [ 255:0] fifo0_m_axi_rdata; + wire [ 7:0] fifo0_m_axi_rresp; + wire [ 3:0] fifo0_m_axi_rlast; + wire [ 3:0] fifo0_m_axi_ruser; + wire [ 3:0] fifo0_m_axi_rvalid; + wire [ 3:0] fifo0_m_axi_rready; rfnoc_block_axi_ram_fifo #( - .THIS_PORTID(4), - .CHDR_W(CHDR_W), - .NUM_PORTS(4), - .MEM_DATA_W(64), - .MEM_ADDR_W(31), - .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), - .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), - .MEM_CLK_RATE(303819444), - .MTU(MTU) + .THIS_PORTID (4), + .CHDR_W (CHDR_W), + .NUM_PORTS (4), + .MEM_DATA_W (64), + .MEM_ADDR_W (31), + .FIFO_ADDR_BASE ({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK ({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE (303819444), + .MTU (MTU) ) b_fifo0_2 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk(fifo0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), - .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), - - .axi_rst(fifo0_axi_rst), - .m_axi_awid(fifo0_m_axi_awid), - .m_axi_awaddr(fifo0_m_axi_awaddr), - .m_axi_awlen(fifo0_m_axi_awlen), - .m_axi_awsize(fifo0_m_axi_awsize), - .m_axi_awburst(fifo0_m_axi_awburst), - .m_axi_awlock(fifo0_m_axi_awlock), - .m_axi_awcache(fifo0_m_axi_awcache), - .m_axi_awprot(fifo0_m_axi_awprot), - .m_axi_awqos(fifo0_m_axi_awqos), - .m_axi_awregion(fifo0_m_axi_awregion), - .m_axi_awuser(fifo0_m_axi_awuser), - .m_axi_awvalid(fifo0_m_axi_awvalid), - .m_axi_awready(fifo0_m_axi_awready), - .m_axi_wdata(fifo0_m_axi_wdata), - .m_axi_wstrb(fifo0_m_axi_wstrb), - .m_axi_wlast(fifo0_m_axi_wlast), - .m_axi_wuser(fifo0_m_axi_wuser), - .m_axi_wvalid(fifo0_m_axi_wvalid), - .m_axi_wready(fifo0_m_axi_wready), - .m_axi_bid(fifo0_m_axi_bid), - .m_axi_bresp(fifo0_m_axi_bresp), - .m_axi_buser(fifo0_m_axi_buser), - .m_axi_bvalid(fifo0_m_axi_bvalid), - .m_axi_bready(fifo0_m_axi_bready), - .m_axi_arid(fifo0_m_axi_arid), - .m_axi_araddr(fifo0_m_axi_araddr), - .m_axi_arlen(fifo0_m_axi_arlen), - .m_axi_arsize(fifo0_m_axi_arsize), - .m_axi_arburst(fifo0_m_axi_arburst), - .m_axi_arlock(fifo0_m_axi_arlock), - .m_axi_arcache(fifo0_m_axi_arcache), - .m_axi_arprot(fifo0_m_axi_arprot), - .m_axi_arqos(fifo0_m_axi_arqos), - .m_axi_arregion(fifo0_m_axi_arregion), - .m_axi_aruser(fifo0_m_axi_aruser), - .m_axi_arvalid(fifo0_m_axi_arvalid), - .m_axi_arready(fifo0_m_axi_arready), - .m_axi_rid(fifo0_m_axi_rid), - .m_axi_rdata(fifo0_m_axi_rdata), - .m_axi_rresp(fifo0_m_axi_rresp), - .m_axi_rlast(fifo0_m_axi_rlast), - .m_axi_ruser(fifo0_m_axi_ruser), - .m_axi_rvalid(fifo0_m_axi_rvalid), - .m_axi_rready(fifo0_m_axi_rready), - - .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .axi_rst (fifo0_axi_rst), + .m_axi_awid (fifo0_m_axi_awid), + .m_axi_awaddr (fifo0_m_axi_awaddr), + .m_axi_awlen (fifo0_m_axi_awlen), + .m_axi_awsize (fifo0_m_axi_awsize), + .m_axi_awburst (fifo0_m_axi_awburst), + .m_axi_awlock (fifo0_m_axi_awlock), + .m_axi_awcache (fifo0_m_axi_awcache), + .m_axi_awprot (fifo0_m_axi_awprot), + .m_axi_awqos (fifo0_m_axi_awqos), + .m_axi_awregion (fifo0_m_axi_awregion), + .m_axi_awuser (fifo0_m_axi_awuser), + .m_axi_awvalid (fifo0_m_axi_awvalid), + .m_axi_awready (fifo0_m_axi_awready), + .m_axi_wdata (fifo0_m_axi_wdata), + .m_axi_wstrb (fifo0_m_axi_wstrb), + .m_axi_wlast (fifo0_m_axi_wlast), + .m_axi_wuser (fifo0_m_axi_wuser), + .m_axi_wvalid (fifo0_m_axi_wvalid), + .m_axi_wready (fifo0_m_axi_wready), + .m_axi_bid (fifo0_m_axi_bid), + .m_axi_bresp (fifo0_m_axi_bresp), + .m_axi_buser (fifo0_m_axi_buser), + .m_axi_bvalid (fifo0_m_axi_bvalid), + .m_axi_bready (fifo0_m_axi_bready), + .m_axi_arid (fifo0_m_axi_arid), + .m_axi_araddr (fifo0_m_axi_araddr), + .m_axi_arlen (fifo0_m_axi_arlen), + .m_axi_arsize (fifo0_m_axi_arsize), + .m_axi_arburst (fifo0_m_axi_arburst), + .m_axi_arlock (fifo0_m_axi_arlock), + .m_axi_arcache (fifo0_m_axi_arcache), + .m_axi_arprot (fifo0_m_axi_arprot), + .m_axi_arqos (fifo0_m_axi_arqos), + .m_axi_arregion (fifo0_m_axi_arregion), + .m_axi_aruser (fifo0_m_axi_aruser), + .m_axi_arvalid (fifo0_m_axi_arvalid), + .m_axi_arready (fifo0_m_axi_arready), + .m_axi_rid (fifo0_m_axi_rid), + .m_axi_rdata (fifo0_m_axi_rdata), + .m_axi_rresp (fifo0_m_axi_rresp), + .m_axi_rlast (fifo0_m_axi_rlast), + .m_axi_ruser (fifo0_m_axi_ruser), + .m_axi_rvalid (fifo0_m_axi_rvalid), + .m_axi_rready (fifo0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Static Router - // ---------------------------------------------------- - assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; - assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + //--------------------------------------------------------------------------- + + assign s_radio0_in_0_tdata = m_ep0_out0_tdata; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_radio0_in_0_tready; - assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; - assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tdata = m_radio0_out_0_tdata; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast; assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ep0_in0_tready; - assign s_radio1_in_0_tdata = m_ep1_out0_tdata ; - assign s_radio1_in_0_tlast = m_ep1_out0_tlast ; + assign s_radio1_in_0_tdata = m_ep1_out0_tdata; + assign s_radio1_in_0_tlast = m_ep1_out0_tlast; assign s_radio1_in_0_tvalid = m_ep1_out0_tvalid; assign m_ep1_out0_tready = s_radio1_in_0_tready; - assign s_ep1_in0_tdata = m_radio1_out_0_tdata ; - assign s_ep1_in0_tlast = m_radio1_out_0_tlast ; + assign s_ep1_in0_tdata = m_radio1_out_0_tdata; + assign s_ep1_in0_tlast = m_radio1_out_0_tlast; assign s_ep1_in0_tvalid = m_radio1_out_0_tvalid; assign m_radio1_out_0_tready = s_ep1_in0_tready; - assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; - assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast; assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; assign m_ep4_out0_tready = s_fifo0_in_0_tready; - assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; - assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast; assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; assign m_fifo0_out_0_tready = s_ep4_in0_tready; - assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; - assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast; assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; assign m_ep5_out0_tready = s_fifo0_in_1_tready; - assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; - assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast; assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; assign m_fifo0_out_1_tready = s_ep5_in0_tready; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Unused Ports - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; assign s_fifo0_in_2_tlast = 1'b0; assign s_fifo0_in_2_tvalid = 1'b0; @@ -909,17 +958,20 @@ module rfnoc_image_core #( assign m_fifo0_out_2_tready = 1'b1; assign m_fifo0_out_3_tready = 1'b1; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Clock Domains - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign radio0_radio_clk = radio_clk; assign radio1_radio_clk = radio_clk; assign fifo0_mem_clk = dram_clk; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // IO Port Connection - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; @@ -1009,3 +1061,6 @@ module rfnoc_image_core #( assign radio1_radio_time = radio_time; endmodule + + +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v index 6196836eb..0ea15f6c3 100644 --- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v @@ -1,19 +1,32 @@ // -// Copyright 2020 Ettus Research, A National Instruments Brand +// Copyright 2021 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // - // Module: rfnoc_image_core (for n320) -// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) -// Re-running that tool will overwrite this file! -// File generated on: 2020-09-02T12:03:04.264797 -// Source: ./n320_rfnoc_image_core.yml -// Source SHA256: a059eb9043ce1c034abc0a0db7daad88a5e584207994c53030a98b3bea1bce39 +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:09.950905 +// Source: n320_rfnoc_image_core.yml +// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f +// + +`default_nettype none + module rfnoc_image_core #( - parameter [15:0] PROTOVER = {8'd1, 8'd0} -)( + parameter CHDR_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( // Clocks input wire chdr_aclk, input wire ctrl_aclk, @@ -21,131 +34,136 @@ module rfnoc_image_core #( input wire radio_clk, input wire dram_clk, // Basic - input wire [15:0] device_id, -//// IO ports ////////////////////////////////// -// ctrlport_radio0 - output wire [ 1-1:0] m_ctrlport_radio0_req_wr, - output wire [ 1-1:0] m_ctrlport_radio0_req_rd, - output wire [ 20-1:0] m_ctrlport_radio0_req_addr, - output wire [ 32-1:0] m_ctrlport_radio0_req_data, - output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio0_req_time, - input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio0_resp_status, - input wire [ 32-1:0] m_ctrlport_radio0_resp_data, -// ctrlport_radio1 - output wire [ 1-1:0] m_ctrlport_radio1_req_wr, - output wire [ 1-1:0] m_ctrlport_radio1_req_rd, - output wire [ 20-1:0] m_ctrlport_radio1_req_addr, - output wire [ 32-1:0] m_ctrlport_radio1_req_data, - output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, - output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, - output wire [ 64-1:0] m_ctrlport_radio1_req_time, - input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, - input wire [ 2-1:0] m_ctrlport_radio1_resp_status, - input wire [ 32-1:0] m_ctrlport_radio1_resp_data, -// time_keeper - input wire [ 64-1:0] radio_time, -// radio_ch0 - input wire [ 32-1:0] radio_rx_data_radio0, - input wire [ 1-1:0] radio_rx_stb_radio0, - output wire [ 1-1:0] radio_rx_running_radio0, - output wire [ 32-1:0] radio_tx_data_radio0, - input wire [ 1-1:0] radio_tx_stb_radio0, - output wire [ 1-1:0] radio_tx_running_radio0, -// radio_ch1 - input wire [ 32-1:0] radio_rx_data_radio1, - input wire [ 1-1:0] radio_rx_stb_radio1, - output wire [ 1-1:0] radio_rx_running_radio1, - output wire [ 32-1:0] radio_tx_data_radio1, - input wire [ 1-1:0] radio_tx_stb_radio1, - output wire [ 1-1:0] radio_tx_running_radio1, -// dram - input wire [ 1-1:0] axi_rst, - output wire [ 4-1:0] m_axi_awid, - output wire [128-1:0] m_axi_awaddr, - output wire [ 32-1:0] m_axi_awlen, - output wire [ 12-1:0] m_axi_awsize, - output wire [ 8-1:0] m_axi_awburst, - output wire [ 4-1:0] m_axi_awlock, - output wire [ 16-1:0] m_axi_awcache, - output wire [ 12-1:0] m_axi_awprot, - output wire [ 16-1:0] m_axi_awqos, - output wire [ 16-1:0] m_axi_awregion, - output wire [ 4-1:0] m_axi_awuser, - output wire [ 4-1:0] m_axi_awvalid, - input wire [ 4-1:0] m_axi_awready, - output wire [256-1:0] m_axi_wdata, - output wire [ 32-1:0] m_axi_wstrb, - output wire [ 4-1:0] m_axi_wlast, - output wire [ 4-1:0] m_axi_wuser, - output wire [ 4-1:0] m_axi_wvalid, - input wire [ 4-1:0] m_axi_wready, - input wire [ 4-1:0] m_axi_bid, - input wire [ 8-1:0] m_axi_bresp, - input wire [ 4-1:0] m_axi_buser, - input wire [ 4-1:0] m_axi_bvalid, - output wire [ 4-1:0] m_axi_bready, - output wire [ 4-1:0] m_axi_arid, - output wire [128-1:0] m_axi_araddr, - output wire [ 32-1:0] m_axi_arlen, - output wire [ 12-1:0] m_axi_arsize, - output wire [ 8-1:0] m_axi_arburst, - output wire [ 4-1:0] m_axi_arlock, - output wire [ 16-1:0] m_axi_arcache, - output wire [ 12-1:0] m_axi_arprot, - output wire [ 16-1:0] m_axi_arqos, - output wire [ 16-1:0] m_axi_arregion, - output wire [ 4-1:0] m_axi_aruser, - output wire [ 4-1:0] m_axi_arvalid, - input wire [ 4-1:0] m_axi_arready, - input wire [ 4-1:0] m_axi_rid, - input wire [256-1:0] m_axi_rdata, - input wire [ 8-1:0] m_axi_rresp, - input wire [ 4-1:0] m_axi_rlast, - input wire [ 4-1:0] m_axi_ruser, - input wire [ 4-1:0] m_axi_rvalid, - output wire [ 4-1:0] m_axi_rready, - // Transport 0 (eth0 1G) - input wire [64-1:0] s_eth0_tdata, - input wire s_eth0_tlast, - input wire s_eth0_tvalid, - output wire s_eth0_tready, - output wire [64-1:0] m_eth0_tdata, - output wire m_eth0_tlast, - output wire m_eth0_tvalid, - input wire m_eth0_tready, - // Transport 1 (eth1 10G) - input wire [64-1:0] s_eth1_tdata, - input wire s_eth1_tlast, - input wire s_eth1_tvalid, - output wire s_eth1_tready, - output wire [64-1:0] m_eth1_tdata, - output wire m_eth1_tlast, - output wire m_eth1_tvalid, - input wire m_eth1_tready, - // Transport 2 (dma dma) - input wire [64-1:0] s_dma_tdata, - input wire s_dma_tlast, - input wire s_dma_tvalid, - output wire s_dma_tready, - output wire [64-1:0] m_dma_tdata, - output wire m_dma_tlast, - output wire m_dma_tvalid, - input wire m_dma_tready + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time_keeper + input wire [ 63:0] radio_time, + // radio_ch0 + input wire [ 31:0] radio_rx_data_radio0, + input wire [ 0:0] radio_rx_stb_radio0, + output wire [ 0:0] radio_rx_running_radio0, + output wire [ 31:0] radio_tx_data_radio0, + input wire [ 0:0] radio_tx_stb_radio0, + output wire [ 0:0] radio_tx_running_radio0, + // radio_ch1 + input wire [ 31:0] radio_rx_data_radio1, + input wire [ 0:0] radio_rx_stb_radio1, + output wire [ 0:0] radio_rx_running_radio1, + output wire [ 31:0] radio_tx_data_radio1, + input wire [ 0:0] radio_tx_stb_radio1, + output wire [ 0:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 3:0] m_axi_awid, + output wire [ 127:0] m_axi_awaddr, + output wire [ 31:0] m_axi_awlen, + output wire [ 11:0] m_axi_awsize, + output wire [ 7:0] m_axi_awburst, + output wire [ 3:0] m_axi_awlock, + output wire [ 15:0] m_axi_awcache, + output wire [ 11:0] m_axi_awprot, + output wire [ 15:0] m_axi_awqos, + output wire [ 15:0] m_axi_awregion, + output wire [ 3:0] m_axi_awuser, + output wire [ 3:0] m_axi_awvalid, + input wire [ 3:0] m_axi_awready, + output wire [ 255:0] m_axi_wdata, + output wire [ 31:0] m_axi_wstrb, + output wire [ 3:0] m_axi_wlast, + output wire [ 3:0] m_axi_wuser, + output wire [ 3:0] m_axi_wvalid, + input wire [ 3:0] m_axi_wready, + input wire [ 3:0] m_axi_bid, + input wire [ 7:0] m_axi_bresp, + input wire [ 3:0] m_axi_buser, + input wire [ 3:0] m_axi_bvalid, + output wire [ 3:0] m_axi_bready, + output wire [ 3:0] m_axi_arid, + output wire [ 127:0] m_axi_araddr, + output wire [ 31:0] m_axi_arlen, + output wire [ 11:0] m_axi_arsize, + output wire [ 7:0] m_axi_arburst, + output wire [ 3:0] m_axi_arlock, + output wire [ 15:0] m_axi_arcache, + output wire [ 11:0] m_axi_arprot, + output wire [ 15:0] m_axi_arqos, + output wire [ 15:0] m_axi_arregion, + output wire [ 3:0] m_axi_aruser, + output wire [ 3:0] m_axi_arvalid, + input wire [ 3:0] m_axi_arready, + input wire [ 3:0] m_axi_rid, + input wire [ 255:0] m_axi_rdata, + input wire [ 7:0] m_axi_rresp, + input wire [ 3:0] m_axi_rlast, + input wire [ 3:0] m_axi_ruser, + input wire [ 3:0] m_axi_rvalid, + output wire [ 3:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [CHDR_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [CHDR_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [CHDR_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [CHDR_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma) + input wire [CHDR_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [CHDR_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready ); - localparam CHDR_W = 64; - localparam MTU = 10; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // CHDR Crossbar - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire xb_to_ep0_tlast ; wire xb_to_ep0_tvalid; @@ -194,12 +212,12 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), - .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tdata ({ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }), .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), - .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tdata ({xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }), .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), .ext_rtcfg_stb (1'h0), @@ -208,9 +226,18 @@ module rfnoc_image_core #( .ext_rtcfg_ack () ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Stream Endpoints - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 65536; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); wire [CHDR_W-1:0] m_ep0_out0_tdata; wire m_ep0_out0_tlast; @@ -220,8 +247,8 @@ module rfnoc_image_core #( wire s_ep0_in0_tlast; wire s_ep0_in0_tvalid; wire s_ep0_in0_tready; - wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; - wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; @@ -234,23 +261,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (0), .CTRL_XBAR_PORT (1), - .INGRESS_BUFF_SIZE (16), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep0_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep0_tdata ), - .s_axis_chdr_tlast (xb_to_ep0_tlast ), - .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), - .s_axis_chdr_tready (xb_to_ep0_tready ), - .m_axis_chdr_tdata (ep0_to_xb_tdata ), - .m_axis_chdr_tlast (ep0_to_xb_tlast ), - .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), - .m_axis_chdr_tready (ep0_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), .s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}), @@ -259,20 +286,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tready ({m_ep0_out0_tready}), - .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tready (s_ep0_ctrl_tready), - .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tready (m_ep0_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 65536; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + wire [CHDR_W-1:0] m_ep1_out0_tdata; wire m_ep1_out0_tlast; wire m_ep1_out0_tvalid; @@ -281,8 +316,8 @@ module rfnoc_image_core #( wire s_ep1_in0_tlast; wire s_ep1_in0_tvalid; wire s_ep1_in0_tready; - wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; - wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; @@ -295,23 +330,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (1), .CTRL_XBAR_PORT (2), - .INGRESS_BUFF_SIZE (16), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep1_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep1_tdata ), - .s_axis_chdr_tlast (xb_to_ep1_tlast ), - .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), - .s_axis_chdr_tready (xb_to_ep1_tready ), - .m_axis_chdr_tdata (ep1_to_xb_tdata ), - .m_axis_chdr_tlast (ep1_to_xb_tlast ), - .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), - .m_axis_chdr_tready (ep1_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), .s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}), @@ -320,20 +355,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tready ({m_ep1_out0_tready}), - .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tready (s_ep1_ctrl_tready), - .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tready (m_ep1_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 4096; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + wire [CHDR_W-1:0] m_ep2_out0_tdata; wire m_ep2_out0_tlast; wire m_ep2_out0_tvalid; @@ -342,8 +385,8 @@ module rfnoc_image_core #( wire s_ep2_in0_tlast; wire s_ep2_in0_tvalid; wire s_ep2_in0_tready; - wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; - wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; @@ -356,23 +399,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (2), .CTRL_XBAR_PORT (3), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep2_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep2_tdata ), - .s_axis_chdr_tlast (xb_to_ep2_tlast ), - .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), - .s_axis_chdr_tready (xb_to_ep2_tready ), - .m_axis_chdr_tdata (ep2_to_xb_tdata ), - .m_axis_chdr_tlast (ep2_to_xb_tlast ), - .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), - .m_axis_chdr_tready (ep2_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), .s_axis_data_tdata ({s_ep2_in0_tdata}), .s_axis_data_tlast ({s_ep2_in0_tlast}), .s_axis_data_tvalid ({s_ep2_in0_tvalid}), @@ -381,20 +424,28 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep2_out0_tlast}), .m_axis_data_tvalid ({m_ep2_out0_tvalid}), .m_axis_data_tready ({m_ep2_out0_tready}), - .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), .s_axis_ctrl_tready (s_ep2_ctrl_tready), - .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), .m_axis_ctrl_tready (m_ep2_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 4096; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + wire [CHDR_W-1:0] m_ep3_out0_tdata; wire m_ep3_out0_tlast; wire m_ep3_out0_tvalid; @@ -403,8 +454,8 @@ module rfnoc_image_core #( wire s_ep3_in0_tlast; wire s_ep3_in0_tvalid; wire s_ep3_in0_tready; - wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; - wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; @@ -417,23 +468,23 @@ module rfnoc_image_core #( .NUM_DATA_O (1), .INST_NUM (3), .CTRL_XBAR_PORT (4), - .INGRESS_BUFF_SIZE (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), .MTU (MTU), .REPORT_STRM_ERRS (1) ) ep3_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk ), - .rfnoc_chdr_rst (rfnoc_chdr_rst ), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .device_id (device_id ), - .s_axis_chdr_tdata (xb_to_ep3_tdata ), - .s_axis_chdr_tlast (xb_to_ep3_tlast ), - .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), - .s_axis_chdr_tready (xb_to_ep3_tready ), - .m_axis_chdr_tdata (ep3_to_xb_tdata ), - .m_axis_chdr_tlast (ep3_to_xb_tlast ), - .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), - .m_axis_chdr_tready (ep3_to_xb_tready ), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), .s_axis_data_tdata ({s_ep3_in0_tdata}), .s_axis_data_tlast ({s_ep3_in0_tlast}), .s_axis_data_tvalid ({s_ep3_in0_tvalid}), @@ -442,58 +493,57 @@ module rfnoc_image_core #( .m_axis_data_tlast ({m_ep3_out0_tlast}), .m_axis_data_tvalid ({m_ep3_out0_tvalid}), .m_axis_data_tready ({m_ep3_out0_tready}), - .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), - .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), .s_axis_ctrl_tready (s_ep3_ctrl_tready), - .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), - .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), .m_axis_ctrl_tready (m_ep3_ctrl_tready), - .strm_seq_err_stb ( ), - .strm_data_err_stb ( ), - .strm_route_err_stb ( ), - .signal_data_err (1'b0 ) + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Control Crossbar - // ---------------------------------------------------- - - wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; - wire m_core_ctrl_tlast , s_core_ctrl_tlast ; - wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; - wire m_core_ctrl_tready, s_core_ctrl_tready; - wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; - wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; - wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; - wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; - wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; - wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; - wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; - wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; - wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; - wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; - wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; - wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; - wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; - wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; - wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; - wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; - wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; - wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; - wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; - wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; - wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; - wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; - wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; - wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; - wire [31:0] m_replay0_ctrl_tdata , s_replay0_ctrl_tdata ; - wire m_replay0_ctrl_tlast , s_replay0_ctrl_tlast ; - wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; - wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata, s_duc0_ctrl_tdata; + wire m_duc0_ctrl_tlast, s_duc0_ctrl_tlast; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata, s_ddc0_ctrl_tdata; + wire m_ddc0_ctrl_tlast, s_ddc0_ctrl_tlast; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata, s_duc1_ctrl_tdata; + wire m_duc1_ctrl_tlast, s_duc1_ctrl_tlast; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata, s_ddc1_ctrl_tdata; + wire m_ddc1_ctrl_tlast, s_ddc1_ctrl_tlast; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_replay0_ctrl_tdata, s_replay0_ctrl_tdata; + wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast; + wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; + wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), @@ -517,9 +567,11 @@ module rfnoc_image_core #( .deadlock_detected() ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // RFNoC Core Kernel - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( @@ -544,12 +596,12 @@ module rfnoc_image_core #( .core_chdr_rst (rfnoc_chdr_rst), .core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_rst (rfnoc_ctrl_rst), - .s_axis_ctrl_tdata (s_core_ctrl_tdata ), - .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tready (s_core_ctrl_tready), - .m_axis_ctrl_tdata (m_core_ctrl_tdata ), - .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tready (m_core_ctrl_tready), .device_id (device_id), @@ -557,13 +609,15 @@ module rfnoc_image_core #( .rfnoc_core_status (rfnoc_core_status) ); - // ---------------------------------------------------- + + //--------------------------------------------------------------------------- // Blocks - // ---------------------------------------------------- + //--------------------------------------------------------------------------- - // ---------------------------------------------------- + //----------------------------------- // duc0 - // ---------------------------------------------------- + //----------------------------------- + wire duc0_ce_clk; wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire s_duc0_in_0_tlast ; @@ -574,44 +628,41 @@ module rfnoc_image_core #( wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tready; - rfnoc_block_duc #( - .THIS_PORTID(2), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .NUM_HB(3), - .CIC_MAX_INTERP(255), - .MTU(MTU) + .THIS_PORTID (2), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (MTU) ) b_duc0_0 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(duc0_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), - .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), - - - .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_duc0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_duc0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_duc0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_duc0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_duc0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // ddc0 - // ---------------------------------------------------- + //----------------------------------- + wire ddc0_ce_clk; wire [CHDR_W-1:0] s_ddc0_in_0_tdata ; wire s_ddc0_in_0_tlast ; @@ -622,44 +673,41 @@ module rfnoc_image_core #( wire m_ddc0_out_0_tvalid; wire m_ddc0_out_0_tready; - rfnoc_block_ddc #( - .THIS_PORTID(3), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .NUM_HB(3), - .CIC_MAX_DECIM(255), - .MTU(MTU) + .THIS_PORTID (3), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (MTU) ) b_ddc0_1 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(ddc0_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), - .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), - - - .s_rfnoc_chdr_tdata ({s_ddc0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_ddc0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_ddc0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_ddc0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_ddc0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_ddc0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_ddc0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_ddc0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .s_rfnoc_chdr_tdata ({s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio0 - // ---------------------------------------------------- + //----------------------------------- + wire radio0_radio_clk; wire [CHDR_W-1:0] s_radio0_in_0_tdata ; wire s_radio0_in_0_tlast ; @@ -670,79 +718,77 @@ module rfnoc_image_core #( wire m_radio0_out_0_tvalid; wire m_radio0_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio0_m_ctrlport_req_wr; - wire [ 1-1:0] radio0_m_ctrlport_req_rd; - wire [ 20-1:0] radio0_m_ctrlport_req_addr; - wire [ 32-1:0] radio0_m_ctrlport_req_data; - wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio0_m_ctrlport_req_has_time; - wire [ 64-1:0] radio0_m_ctrlport_req_time; - wire [ 1-1:0] radio0_m_ctrlport_resp_ack; - wire [ 2-1:0] radio0_m_ctrlport_resp_status; - wire [ 32-1:0] radio0_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio0_radio_time; - // radio_iface - wire [ 32-1:0] radio0_radio_rx_data; - wire [ 1-1:0] radio0_radio_rx_stb; - wire [ 1-1:0] radio0_radio_rx_running; - wire [ 32-1:0] radio0_radio_tx_data; - wire [ 1-1:0] radio0_radio_tx_stb; - wire [ 1-1:0] radio0_radio_tx_running; + // ctrl_port + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio0_radio_time; + // radio_iface + wire [ 31:0] radio0_radio_rx_data; + wire [ 0:0] radio0_radio_rx_stb; + wire [ 0:0] radio0_radio_rx_running; + wire [ 31:0] radio0_radio_tx_data; + wire [ 0:0] radio0_radio_tx_stb; + wire [ 0:0] radio0_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(4), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .MTU(MTU) + .THIS_PORTID (4), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .MTU (MTU) ) b_radio0_2 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio0_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), - .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), - - .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio0_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), - .radio_time(radio0_radio_time), - .radio_rx_data(radio0_radio_rx_data), - .radio_rx_stb(radio0_radio_rx_stb), - .radio_rx_running(radio0_radio_rx_running), - .radio_tx_data(radio0_radio_tx_data), - .radio_tx_stb(radio0_radio_tx_stb), - .radio_tx_running(radio0_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // duc1 - // ---------------------------------------------------- + //----------------------------------- + wire duc1_ce_clk; wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire s_duc1_in_0_tlast ; @@ -753,44 +799,41 @@ module rfnoc_image_core #( wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tready; - rfnoc_block_duc #( - .THIS_PORTID(5), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .NUM_HB(3), - .CIC_MAX_INTERP(255), - .MTU(MTU) + .THIS_PORTID (5), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (MTU) ) b_duc1_3 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(duc1_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), - .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), - - - .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_duc1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_duc1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_duc1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_duc1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_duc1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // ddc1 - // ---------------------------------------------------- + //----------------------------------- + wire ddc1_ce_clk; wire [CHDR_W-1:0] s_ddc1_in_0_tdata ; wire s_ddc1_in_0_tlast ; @@ -801,44 +844,41 @@ module rfnoc_image_core #( wire m_ddc1_out_0_tvalid; wire m_ddc1_out_0_tready; - rfnoc_block_ddc #( - .THIS_PORTID(6), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .NUM_HB(3), - .CIC_MAX_DECIM(255), - .MTU(MTU) + .THIS_PORTID (6), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (MTU) ) b_ddc1_4 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .ce_clk(ddc1_ce_clk), - .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), - .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), - - - .s_rfnoc_chdr_tdata ({s_ddc1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_ddc1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_ddc1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_ddc1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_ddc1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_ddc1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_ddc1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_ddc1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + .s_rfnoc_chdr_tdata ({s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // radio1 - // ---------------------------------------------------- + //----------------------------------- + wire radio1_radio_clk; wire [CHDR_W-1:0] s_radio1_in_0_tdata ; wire s_radio1_in_0_tlast ; @@ -849,79 +889,77 @@ module rfnoc_image_core #( wire m_radio1_out_0_tvalid; wire m_radio1_out_0_tready; - // ctrl_port - wire [ 1-1:0] radio1_m_ctrlport_req_wr; - wire [ 1-1:0] radio1_m_ctrlport_req_rd; - wire [ 20-1:0] radio1_m_ctrlport_req_addr; - wire [ 32-1:0] radio1_m_ctrlport_req_data; - wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; - wire [ 1-1:0] radio1_m_ctrlport_req_has_time; - wire [ 64-1:0] radio1_m_ctrlport_req_time; - wire [ 1-1:0] radio1_m_ctrlport_resp_ack; - wire [ 2-1:0] radio1_m_ctrlport_resp_status; - wire [ 32-1:0] radio1_m_ctrlport_resp_data; - // time_keeper - wire [ 64-1:0] radio1_radio_time; - // radio_iface - wire [ 32-1:0] radio1_radio_rx_data; - wire [ 1-1:0] radio1_radio_rx_stb; - wire [ 1-1:0] radio1_radio_rx_running; - wire [ 32-1:0] radio1_radio_tx_data; - wire [ 1-1:0] radio1_radio_tx_stb; - wire [ 1-1:0] radio1_radio_tx_running; + // ctrl_port + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 63:0] radio1_radio_time; + // radio_iface + wire [ 31:0] radio1_radio_rx_data; + wire [ 0:0] radio1_radio_rx_stb; + wire [ 0:0] radio1_radio_rx_running; + wire [ 31:0] radio1_radio_tx_data; + wire [ 0:0] radio1_radio_tx_stb; + wire [ 0:0] radio1_radio_tx_running; rfnoc_block_radio #( - .THIS_PORTID(7), - .CHDR_W(CHDR_W), - .NUM_PORTS(1), - .MTU(MTU) + .THIS_PORTID (7), + .CHDR_W (CHDR_W), + .NUM_PORTS (1), + .MTU (MTU) ) b_radio1_5 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .radio_clk(radio1_radio_clk), - .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), - .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), - - .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), - .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), - .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), - .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), - .m_ctrlport_req_time(radio1_m_ctrlport_req_time), - .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), - .radio_time(radio1_radio_time), - .radio_rx_data(radio1_radio_rx_data), - .radio_rx_stb(radio1_radio_rx_stb), - .radio_rx_running(radio1_radio_rx_running), - .radio_tx_data(radio1_radio_tx_data), - .radio_tx_stb(radio1_radio_tx_stb), - .radio_tx_running(radio1_radio_tx_running), - - .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_radio1_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_radio1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_radio1_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_radio1_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) ); - - // ---------------------------------------------------- + //----------------------------------- // replay0 - // ---------------------------------------------------- + //----------------------------------- + wire replay0_mem_clk; wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; @@ -932,203 +970,204 @@ module rfnoc_image_core #( wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; wire m_replay0_out_1_tready, m_replay0_out_0_tready; - // axi_ram - wire [ 1-1:0] replay0_axi_rst; - wire [ 4-1:0] replay0_m_axi_awid; - wire [128-1:0] replay0_m_axi_awaddr; - wire [ 32-1:0] replay0_m_axi_awlen; - wire [ 12-1:0] replay0_m_axi_awsize; - wire [ 8-1:0] replay0_m_axi_awburst; - wire [ 4-1:0] replay0_m_axi_awlock; - wire [ 16-1:0] replay0_m_axi_awcache; - wire [ 12-1:0] replay0_m_axi_awprot; - wire [ 16-1:0] replay0_m_axi_awqos; - wire [ 16-1:0] replay0_m_axi_awregion; - wire [ 4-1:0] replay0_m_axi_awuser; - wire [ 4-1:0] replay0_m_axi_awvalid; - wire [ 4-1:0] replay0_m_axi_awready; - wire [256-1:0] replay0_m_axi_wdata; - wire [ 32-1:0] replay0_m_axi_wstrb; - wire [ 4-1:0] replay0_m_axi_wlast; - wire [ 4-1:0] replay0_m_axi_wuser; - wire [ 4-1:0] replay0_m_axi_wvalid; - wire [ 4-1:0] replay0_m_axi_wready; - wire [ 4-1:0] replay0_m_axi_bid; - wire [ 8-1:0] replay0_m_axi_bresp; - wire [ 4-1:0] replay0_m_axi_buser; - wire [ 4-1:0] replay0_m_axi_bvalid; - wire [ 4-1:0] replay0_m_axi_bready; - wire [ 4-1:0] replay0_m_axi_arid; - wire [128-1:0] replay0_m_axi_araddr; - wire [ 32-1:0] replay0_m_axi_arlen; - wire [ 12-1:0] replay0_m_axi_arsize; - wire [ 8-1:0] replay0_m_axi_arburst; - wire [ 4-1:0] replay0_m_axi_arlock; - wire [ 16-1:0] replay0_m_axi_arcache; - wire [ 12-1:0] replay0_m_axi_arprot; - wire [ 16-1:0] replay0_m_axi_arqos; - wire [ 16-1:0] replay0_m_axi_arregion; - wire [ 4-1:0] replay0_m_axi_aruser; - wire [ 4-1:0] replay0_m_axi_arvalid; - wire [ 4-1:0] replay0_m_axi_arready; - wire [ 4-1:0] replay0_m_axi_rid; - wire [256-1:0] replay0_m_axi_rdata; - wire [ 8-1:0] replay0_m_axi_rresp; - wire [ 4-1:0] replay0_m_axi_rlast; - wire [ 4-1:0] replay0_m_axi_ruser; - wire [ 4-1:0] replay0_m_axi_rvalid; - wire [ 4-1:0] replay0_m_axi_rready; + // axi_ram + wire [ 0:0] replay0_axi_rst; + wire [ 3:0] replay0_m_axi_awid; + wire [ 127:0] replay0_m_axi_awaddr; + wire [ 31:0] replay0_m_axi_awlen; + wire [ 11:0] replay0_m_axi_awsize; + wire [ 7:0] replay0_m_axi_awburst; + wire [ 3:0] replay0_m_axi_awlock; + wire [ 15:0] replay0_m_axi_awcache; + wire [ 11:0] replay0_m_axi_awprot; + wire [ 15:0] replay0_m_axi_awqos; + wire [ 15:0] replay0_m_axi_awregion; + wire [ 3:0] replay0_m_axi_awuser; + wire [ 3:0] replay0_m_axi_awvalid; + wire [ 3:0] replay0_m_axi_awready; + wire [ 255:0] replay0_m_axi_wdata; + wire [ 31:0] replay0_m_axi_wstrb; + wire [ 3:0] replay0_m_axi_wlast; + wire [ 3:0] replay0_m_axi_wuser; + wire [ 3:0] replay0_m_axi_wvalid; + wire [ 3:0] replay0_m_axi_wready; + wire [ 3:0] replay0_m_axi_bid; + wire [ 7:0] replay0_m_axi_bresp; + wire [ 3:0] replay0_m_axi_buser; + wire [ 3:0] replay0_m_axi_bvalid; + wire [ 3:0] replay0_m_axi_bready; + wire [ 3:0] replay0_m_axi_arid; + wire [ 127:0] replay0_m_axi_araddr; + wire [ 31:0] replay0_m_axi_arlen; + wire [ 11:0] replay0_m_axi_arsize; + wire [ 7:0] replay0_m_axi_arburst; + wire [ 3:0] replay0_m_axi_arlock; + wire [ 15:0] replay0_m_axi_arcache; + wire [ 11:0] replay0_m_axi_arprot; + wire [ 15:0] replay0_m_axi_arqos; + wire [ 15:0] replay0_m_axi_arregion; + wire [ 3:0] replay0_m_axi_aruser; + wire [ 3:0] replay0_m_axi_arvalid; + wire [ 3:0] replay0_m_axi_arready; + wire [ 3:0] replay0_m_axi_rid; + wire [ 255:0] replay0_m_axi_rdata; + wire [ 7:0] replay0_m_axi_rresp; + wire [ 3:0] replay0_m_axi_rlast; + wire [ 3:0] replay0_m_axi_ruser; + wire [ 3:0] replay0_m_axi_rvalid; + wire [ 3:0] replay0_m_axi_rready; rfnoc_block_replay #( - .THIS_PORTID(8), - .CHDR_W(CHDR_W), - .NUM_PORTS(2), - .MEM_ADDR_W(31), - .MEM_DATA_W(64), - .MTU(MTU) + .THIS_PORTID (8), + .CHDR_W (CHDR_W), + .NUM_PORTS (2), + .MEM_ADDR_W (31), + .MEM_DATA_W (64), + .MTU (MTU) ) b_replay0_6 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk(replay0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), - .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), - - .axi_rst(replay0_axi_rst), - .m_axi_awid(replay0_m_axi_awid), - .m_axi_awaddr(replay0_m_axi_awaddr), - .m_axi_awlen(replay0_m_axi_awlen), - .m_axi_awsize(replay0_m_axi_awsize), - .m_axi_awburst(replay0_m_axi_awburst), - .m_axi_awlock(replay0_m_axi_awlock), - .m_axi_awcache(replay0_m_axi_awcache), - .m_axi_awprot(replay0_m_axi_awprot), - .m_axi_awqos(replay0_m_axi_awqos), - .m_axi_awregion(replay0_m_axi_awregion), - .m_axi_awuser(replay0_m_axi_awuser), - .m_axi_awvalid(replay0_m_axi_awvalid), - .m_axi_awready(replay0_m_axi_awready), - .m_axi_wdata(replay0_m_axi_wdata), - .m_axi_wstrb(replay0_m_axi_wstrb), - .m_axi_wlast(replay0_m_axi_wlast), - .m_axi_wuser(replay0_m_axi_wuser), - .m_axi_wvalid(replay0_m_axi_wvalid), - .m_axi_wready(replay0_m_axi_wready), - .m_axi_bid(replay0_m_axi_bid), - .m_axi_bresp(replay0_m_axi_bresp), - .m_axi_buser(replay0_m_axi_buser), - .m_axi_bvalid(replay0_m_axi_bvalid), - .m_axi_bready(replay0_m_axi_bready), - .m_axi_arid(replay0_m_axi_arid), - .m_axi_araddr(replay0_m_axi_araddr), - .m_axi_arlen(replay0_m_axi_arlen), - .m_axi_arsize(replay0_m_axi_arsize), - .m_axi_arburst(replay0_m_axi_arburst), - .m_axi_arlock(replay0_m_axi_arlock), - .m_axi_arcache(replay0_m_axi_arcache), - .m_axi_arprot(replay0_m_axi_arprot), - .m_axi_arqos(replay0_m_axi_arqos), - .m_axi_arregion(replay0_m_axi_arregion), - .m_axi_aruser(replay0_m_axi_aruser), - .m_axi_arvalid(replay0_m_axi_arvalid), - .m_axi_arready(replay0_m_axi_arready), - .m_axi_rid(replay0_m_axi_rid), - .m_axi_rdata(replay0_m_axi_rdata), - .m_axi_rresp(replay0_m_axi_rresp), - .m_axi_rlast(replay0_m_axi_rlast), - .m_axi_ruser(replay0_m_axi_ruser), - .m_axi_rvalid(replay0_m_axi_rvalid), - .m_axi_rready(replay0_m_axi_rready), - - .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), - .s_rfnoc_chdr_tvalid({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), - .s_rfnoc_chdr_tready({s_replay0_in_1_tready, s_replay0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }), - .m_rfnoc_chdr_tvalid({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), - .m_rfnoc_chdr_tready({m_replay0_out_1_tready, m_replay0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid(s_replay0_ctrl_tvalid), - .s_rfnoc_ctrl_tready(s_replay0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid(m_replay0_ctrl_tvalid), - .m_rfnoc_ctrl_tready(m_replay0_ctrl_tready) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (replay0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), + .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), + .axi_rst (replay0_axi_rst), + .m_axi_awid (replay0_m_axi_awid), + .m_axi_awaddr (replay0_m_axi_awaddr), + .m_axi_awlen (replay0_m_axi_awlen), + .m_axi_awsize (replay0_m_axi_awsize), + .m_axi_awburst (replay0_m_axi_awburst), + .m_axi_awlock (replay0_m_axi_awlock), + .m_axi_awcache (replay0_m_axi_awcache), + .m_axi_awprot (replay0_m_axi_awprot), + .m_axi_awqos (replay0_m_axi_awqos), + .m_axi_awregion (replay0_m_axi_awregion), + .m_axi_awuser (replay0_m_axi_awuser), + .m_axi_awvalid (replay0_m_axi_awvalid), + .m_axi_awready (replay0_m_axi_awready), + .m_axi_wdata (replay0_m_axi_wdata), + .m_axi_wstrb (replay0_m_axi_wstrb), + .m_axi_wlast (replay0_m_axi_wlast), + .m_axi_wuser (replay0_m_axi_wuser), + .m_axi_wvalid (replay0_m_axi_wvalid), + .m_axi_wready (replay0_m_axi_wready), + .m_axi_bid (replay0_m_axi_bid), + .m_axi_bresp (replay0_m_axi_bresp), + .m_axi_buser (replay0_m_axi_buser), + .m_axi_bvalid (replay0_m_axi_bvalid), + .m_axi_bready (replay0_m_axi_bready), + .m_axi_arid (replay0_m_axi_arid), + .m_axi_araddr (replay0_m_axi_araddr), + .m_axi_arlen (replay0_m_axi_arlen), + .m_axi_arsize (replay0_m_axi_arsize), + .m_axi_arburst (replay0_m_axi_arburst), + .m_axi_arlock (replay0_m_axi_arlock), + .m_axi_arcache (replay0_m_axi_arcache), + .m_axi_arprot (replay0_m_axi_arprot), + .m_axi_arqos (replay0_m_axi_arqos), + .m_axi_arregion (replay0_m_axi_arregion), + .m_axi_aruser (replay0_m_axi_aruser), + .m_axi_arvalid (replay0_m_axi_arvalid), + .m_axi_arready (replay0_m_axi_arready), + .m_axi_rid (replay0_m_axi_rid), + .m_axi_rdata (replay0_m_axi_rdata), + .m_axi_rresp (replay0_m_axi_rresp), + .m_axi_rlast (replay0_m_axi_rlast), + .m_axi_ruser (replay0_m_axi_ruser), + .m_axi_rvalid (replay0_m_axi_rvalid), + .m_axi_rready (replay0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_replay0_in_1_tready, s_replay0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) ); - - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Static Router - // ---------------------------------------------------- - assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; - assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + //--------------------------------------------------------------------------- + + assign s_duc0_in_0_tdata = m_ep0_out0_tdata; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign m_ep0_out0_tready = s_duc0_in_0_tready; - assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; - assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast; assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; assign m_duc0_out_0_tready = s_radio0_in_0_tready; - assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; - assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast; assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; assign m_radio0_out_0_tready = s_ddc0_in_0_tready; - assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; - assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast; assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; assign m_ddc0_out_0_tready = s_ep0_in0_tready; - assign s_duc1_in_0_tdata = m_ep1_out0_tdata ; - assign s_duc1_in_0_tlast = m_ep1_out0_tlast ; + assign s_duc1_in_0_tdata = m_ep1_out0_tdata; + assign s_duc1_in_0_tlast = m_ep1_out0_tlast; assign s_duc1_in_0_tvalid = m_ep1_out0_tvalid; assign m_ep1_out0_tready = s_duc1_in_0_tready; - assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; - assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast; assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; assign m_duc1_out_0_tready = s_radio1_in_0_tready; - assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; - assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast; assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; assign m_radio1_out_0_tready = s_ddc1_in_0_tready; - assign s_ep1_in0_tdata = m_ddc1_out_0_tdata ; - assign s_ep1_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep1_in0_tdata = m_ddc1_out_0_tdata; + assign s_ep1_in0_tlast = m_ddc1_out_0_tlast; assign s_ep1_in0_tvalid = m_ddc1_out_0_tvalid; assign m_ddc1_out_0_tready = s_ep1_in0_tready; - assign s_replay0_in_0_tdata = m_ep2_out0_tdata ; - assign s_replay0_in_0_tlast = m_ep2_out0_tlast ; + assign s_replay0_in_0_tdata = m_ep2_out0_tdata; + assign s_replay0_in_0_tlast = m_ep2_out0_tlast; assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid; assign m_ep2_out0_tready = s_replay0_in_0_tready; - assign s_ep2_in0_tdata = m_replay0_out_0_tdata ; - assign s_ep2_in0_tlast = m_replay0_out_0_tlast ; + assign s_ep2_in0_tdata = m_replay0_out_0_tdata; + assign s_ep2_in0_tlast = m_replay0_out_0_tlast; assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid; assign m_replay0_out_0_tready = s_ep2_in0_tready; - assign s_replay0_in_1_tdata = m_ep3_out0_tdata ; - assign s_replay0_in_1_tlast = m_ep3_out0_tlast ; + assign s_replay0_in_1_tdata = m_ep3_out0_tdata; + assign s_replay0_in_1_tlast = m_ep3_out0_tlast; assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid; assign m_ep3_out0_tready = s_replay0_in_1_tready; - assign s_ep3_in0_tdata = m_replay0_out_1_tdata ; - assign s_ep3_in0_tlast = m_replay0_out_1_tlast ; + assign s_ep3_in0_tdata = m_replay0_out_1_tdata; + assign s_ep3_in0_tlast = m_replay0_out_1_tlast; assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid; assign m_replay0_out_1_tready = s_ep3_in0_tready; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Unused Ports - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + + - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // Clock Domains - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + assign radio0_radio_clk = radio_clk; assign ddc0_ce_clk = radio_clk; assign duc0_ce_clk = radio_clk; @@ -1138,9 +1177,10 @@ module rfnoc_image_core #( assign replay0_mem_clk = dram_clk; - // ---------------------------------------------------- + //--------------------------------------------------------------------------- // IO Port Connection - // ---------------------------------------------------- + //--------------------------------------------------------------------------- + // Master/Slave Connections: assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; @@ -1230,3 +1270,6 @@ module rfnoc_image_core #( assign radio1_radio_time = radio_time; endmodule + + +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh new file mode 100644 index 000000000..82cf70236 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh @@ -0,0 +1,21 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for n320) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// File generated on: 2021-05-03T08:51:09.997079 +// Source: n320_rfnoc_image_core.yml +// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f +// + +`define CHDR_WIDTH 64 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } |