diff options
Diffstat (limited to 'fpga/usrp3/top/n3xx/ip')
64 files changed, 20832 insertions, 0 deletions
diff --git a/fpga/usrp3/top/n3xx/ip/Makefile.inc b/fpga/usrp3/top/n3xx/ip/Makefile.inc new file mode 100644 index 000000000..98021fcc7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/Makefile.inc @@ -0,0 +1,90 @@ +# +# Copyright 2017-2018 Ettus Research, a National Instruments Company +# + +#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +include $(IP_DIR)/hb47_1to2/Makefile.inc +include $(IP_DIR)/hb47_2to1/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_256_bd/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +#include $(IP_DIR)/input_sample_fifo/Makefile.inc +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/misc_clock_gen/Makefile.inc +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc +include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc +include $(IP_DIR)/axi_eth_dma/Makefile.inc +include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc +include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc +include $(IP_DIR)/n310_ps_bd/Makefile.inc + +BD_SRCS = \ +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_N310_PS_BD_SRCS) + +IP_XCI_SRCS = \ +$(IP_HB47_1TO2_SRCS) \ +$(IP_HB47_2TO1_SRCS) \ +$(IP_AXI4_BRAM_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \ +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \ +$(IP_MISC_CLOCK_GEN_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI_ETH_DMA_SRCS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_SRCS) \ + +IP_CODEGEN_SRCS = \ +$(ONE_GIGE_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) + +IP_SYNTH_OUTPUTS = \ +$(IP_HB47_1TO2_OUTS) \ +$(IP_HB47_2TO1_OUTS) \ +$(IP_AXI4_BRAM_OUTS) \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \ +$(IP_AXI_INTERCONNECT_OUTS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \ +$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AXI_ETH_DMA_OUTS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AURORA_64B66B_PCS_PMA_OUTS) + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_2X64_256_BD_OUTS) \ +$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \ +$(IP_N310_PS_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc new file mode 100644 index 000000000..270f4e92e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +AURORA_PHY_SRCS = \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \ +$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) + +IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \ +imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \ +imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \ +imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \ +) + +IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + +IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ +aurora_64b66b_pcs_pma.xci.out \ +) + +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci new file mode 100644 index 000000000..aaba9d9c1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci @@ -0,0 +1,1780 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>aurora_64b66b_pcs_pma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="aurora_64b66b" spirit:version="12.0"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue 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spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE0.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE1.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE10.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE11.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE12.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE13.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE14.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE15.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue 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spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE5.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE6.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue 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spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE8.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_LANE9.RX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PB.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE0.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE1.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE10.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE11.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE12.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE13.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE14.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE15.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE2.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE3.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE4.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE5.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE6.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE7.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE8.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.CHNL_NUMBER">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.GT_DIRECTION">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.MASTERCLK_SRC">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_LANE9.TX_SETTINGS">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PB.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_M_AXIS_RX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXIS_TX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_1.FREQ_HZ">156.25</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_1.PARENT_ID">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_2.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TREADY">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXIS_RX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TREADY">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.HAS_TSTRB">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.LAYERED_METADATA">undef</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_S_AXIS_TX.TUSER_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TKEEP">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_K_M_AXIS_RX.HAS_TLAST">0</spirit:configurableElementValue> + <spirit:configurableElementValue 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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TransceiverControl" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.crc_mode" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.drp_mode" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.flow_mode" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.interface_mode" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..39ed52f8c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v new file mode 100644 index 000000000..9e98990c1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output init_clk +); + + wire init_clk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (init_clk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (init_clk_buf), + .O (init_clk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v new file mode 100644 index 000000000..c2107f8b1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v @@ -0,0 +1,108 @@ +// +// Copyright 2017 Ettus Research LLC +// + +module aurora_phy_mmcm +( + input aurora_tx_clk_unbuf, + input mmcm_reset, + output user_clk, + output sync_clk, + output mmcm_locked +); + + wire mmcm_fb_clk; + wire user_clk_i; + wire sync_clk_i; + wire aurora_tx_clk; + + BUFG txout_clock_net_i ( + .I(aurora_tx_clk_unbuf), + .O(aurora_tx_clk) + ); + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (aurora_tx_clk), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..6b768bfcf --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,258 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input user_clk, + input sync_clk, + input init_clk, + input qpllclk, + input qpllrefclk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err, + input qplllock, + input qpllrefclklost, + output qpllreset, + output tx_out_clk, + input mmcm_locked, + output gt_pll_lock +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock_iclk, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_qpllclk_quad2_i; + wire gt_qpllrefclk_quad2_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + assign gt_qpllclk_quad1_i = qpllclk; + assign gt_qpllrefclk_quad1_i = qpllrefclk; + assign gt_qpllclk_quad2_i = qpllclk; + assign gt_qpllrefclk_quad2_i = qpllrefclk; + assign gt_qplllock_i = qplllock; + assign gt_qpllrefclklost_i = qpllrefclklost; + assign qpllreset = gt_to_common_qpllreset_i; + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; +aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc new file mode 100644 index 000000000..34dacff4f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS = $(IP_BUILD_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS = $(addprefix $(IP_BUILD_DIR)/axi3_to_axi4lite_protocol_converter/, \ +axi3_to_axi4lite_protocol_converter.xci.out \ +synth/axi3_to_axi4lite_protocol_converter.v \ +) + +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) $(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) : $(IP_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci + $(call BUILD_VIVADO_IP,axi3_to_axi4lite_protocol_converter,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci new file mode 100644 index 000000000..344851bf8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci @@ -0,0 +1,152 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" 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+IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_32/, \ +axi4_to_axi3_protocol_converter_32.xci.out \ +synth/axi4_to_axi3_protocol_converter_32.v \ +) + +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci + $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_32,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci new file mode 100644 index 000000000..2fa5f4cac --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci @@ -0,0 +1,149 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" 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</spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc new file mode 100644 index 000000000..0c68b7a3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS = $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_64/, \ +axi4_to_axi3_protocol_converter_64.xci.out \ +synth/axi4_to_axi3_protocol_converter_64.v \ +) + +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) : 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+ </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..26d706087 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi64_4k_2clk_fifo</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue 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b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..2f6ec0d88 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi64_8k_2clk_fifo</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + 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spirit:referenceId="PARAM_VALUE.Enable_TLAST">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Independent_Clocks_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Independent_Clocks_Distributed_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">15</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">AXI_STREAM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" 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xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc new file mode 100644 index 000000000..658891469 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_ETH_DMA_SRCS = $(IP_BUILD_DIR)/axi_eth_dma/axi_eth_dma.xci + +IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ +axi_eth_dma.xci.out \ +) + +$(IP_AXI_ETH_DMA_SRCS) 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xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_S2MM.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.HAS_TSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TDEST_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_STS.TUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_mm2s_dre" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_include_s2mm_dre" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axi_mm2s_data_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axi_s2mm_data_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_m_axis_mm2s_tdata_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_mm2s_burst_size" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s2mm_burst_size" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_s_axis_s2mm_tdata_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_include_stscntrl_strm" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_length_width" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.c_sg_use_stsapp_length" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc new file mode 100644 index 000000000..02b27ee68 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_2X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v + +BD_AXI_INTERCON_2X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \ +axi_intercon_2x64_256_bd.bd.out \ +axi_intercon_2x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(IP_AXI_INTERCON_2X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_2x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd new file mode 100644 index 000000000..121829558 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd @@ -0,0 +1,715 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:synthFlowMode="None" bd:tool_version="2015.4" bd:top="axi_intercon_2x64_256_bd" bd:version="1.00.a"> + + <spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>BlockDiagram</spirit:library> + <spirit:name>axi_intercon_2x64_256_bd</spirit:name> + <spirit:version>1.00.a</spirit:version> + <spirit:parameters> + <spirit:parameter> + <spirit:name>isTop</spirit:name> + <spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>M00_AXI</spirit:name> + <spirit:master/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>256</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>200000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_2x64_128_bd_M00_ACLK</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S00_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S01_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.M00_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>M00_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_2x64_128_bd_M00_ACLK</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>M00_AXI_ARESETN</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.M00_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>M00_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters/> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.S00_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S00_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>1000000000</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_2x64_128_bd_S00_ACLK</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>S00_AXI_ARESETN</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.S00_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S00_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters/> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.S01_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S01_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_2x64_128_bd_S01_ACLK</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value>S01_AXI_ARESETN</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>RST.S01_AXI_ARESETN</spirit:name> + <spirit:displayName>Reset</spirit:displayName> + <spirit:description>Reset</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>S01_AXI_ARESETN</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters/> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:model> + <spirit:views> + <spirit:view> + <spirit:name>BlockDiagram</spirit:name> + <spirit:envIdentifier>:vivado.xilinx.com:</spirit:envIdentifier> + <spirit:hierarchyRef spirit:library="BlockDiagram" spirit:name="axi_intercon_2x64_256_bd_imp" spirit:vendor="xilinx.com" spirit:version="1.00.a"/> + </spirit:view> + </spirit:views> + <spirit:ports> + <spirit:port> + <spirit:name>M00_AXI_ACLK</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>M00_AXI_ARESETN</spirit:name> + <spirit:wire> + <spirit:direction>in</spirit:direction> + </spirit:wire> + </spirit:port> + <spirit:port> + <spirit:name>S00_AXI_ACLK</spirit:name> + <spirit:wire> + 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spirit:referenceId="REG_AW">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_AR">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_R">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_W">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="REG_B">1</spirit:configurableElementValue> + </spirit:configurableElementValues> + </spirit:componentInstance> + </spirit:componentInstances> + <spirit:interconnections> + <spirit:interconnection> + <spirit:name>s00_rs_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s00_rs"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_width_conv"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s01_rs_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_rs"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_width_conv"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>xbar_M00_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="m00_rs"/> + <spirit:activeInterface spirit:busRef="M00_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s00_rs_256_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s00_rs_256"/> + <spirit:activeInterface spirit:busRef="S00_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s01_rs_256_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_rs_256"/> + <spirit:activeInterface spirit:busRef="S01_AXI" spirit:componentRef="xbar"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s00_width_conv_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s00_width_conv"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_rs_256"/> + </spirit:interconnection> + <spirit:interconnection> + <spirit:name>s01_width_conv_M_AXI</spirit:name> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="s01_width_conv"/> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_rs_256"/> + </spirit:interconnection> + </spirit:interconnections> + <spirit:adHocConnections> + <spirit:adHocConnection> + <spirit:name>M00_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="M00_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="xbar" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="m00_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s00_rs_256" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s01_rs_256" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="m_axi_aclk"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="m_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>M00_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="M00_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="xbar" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="m00_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s00_rs_256" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s01_rs_256" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="m_axi_aresetn"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="m_axi_aresetn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S00_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S00_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="s00_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="s_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S00_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S00_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="s00_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s00_width_conv" spirit:portRef="s_axi_aresetn"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S01_AXI_ACLK_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S01_AXI_ACLK"/> + <spirit:internalPortReference spirit:componentRef="s01_rs" spirit:portRef="aclk"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="s_axi_aclk"/> + </spirit:adHocConnection> + <spirit:adHocConnection> + <spirit:name>S01_AXI_ARESETN_1</spirit:name> + <spirit:externalPortReference spirit:portRef="S01_AXI_ARESETN"/> + <spirit:internalPortReference spirit:componentRef="s01_rs" spirit:portRef="aresetn"/> + <spirit:internalPortReference spirit:componentRef="s01_width_conv" spirit:portRef="s_axi_aresetn"/> + </spirit:adHocConnection> + </spirit:adHocConnections> + <spirit:hierConnections> + <spirit:hierConnection spirit:interfaceRef="M00_AXI/m00_rs_M_AXI"> + <spirit:activeInterface spirit:busRef="M_AXI" spirit:componentRef="m00_rs"/> + </spirit:hierConnection> + <spirit:hierConnection spirit:interfaceRef="S00_AXI/S00_AXI_1"> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s00_rs"/> + </spirit:hierConnection> + <spirit:hierConnection spirit:interfaceRef="S01_AXI/S01_AXI_1"> + <spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="s01_rs"/> + </spirit:hierConnection> + </spirit:hierConnections> + </spirit:design> + +</bd:repository> diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml new file mode 100644 index 000000000..5e3a0c83e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml @@ -0,0 +1,89 @@ +<?xml version="1.0" encoding="UTF-8"?> +<Root MajorVersion="0" MinorVersion="33"> + <CompositeFile CompositeFileTopName="axi_intercon_2x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true"> + <Description>Composite Fileset</Description> + <Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/> + <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/> + <Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/> + <FileCollection Name="SOURCES" Type="SOURCES"> + <File Name="ip/axi_intercon_2x64_256_bd_s00_cc_0/axi_intercon_2x64_256_bd_s00_cc_0.xci" Type="IP"> + <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_m00_rs_0/axi_intercon_2x64_256_bd_m00_rs_0.xci" Type="IP"> + <Instance HierarchyPath="m00_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s00_rs_0/axi_intercon_2x64_256_bd_s00_rs_0.xci" Type="IP"> + <Instance HierarchyPath="s00_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s00_width_conv_0/axi_intercon_2x64_256_bd_s00_width_conv_0.xci" Type="IP"> + <Instance HierarchyPath="s00_width_conv"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s01_rs_0/axi_intercon_2x64_256_bd_s01_rs_0.xci" Type="IP"> + <Instance HierarchyPath="s01_rs"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s01_width_conv_0/axi_intercon_2x64_256_bd_s01_width_conv_0.xci" Type="IP"> + <Instance HierarchyPath="s01_width_conv"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_xbar_0/axi_intercon_2x64_256_bd_xbar_0.xci" Type="IP"> + <Instance HierarchyPath="xbar"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s01_rs_256_0/axi_intercon_2x64_256_bd_s01_rs_256_0.xci" Type="IP"> + <Instance HierarchyPath="s01_rs_256"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s00_rs_256_0/axi_intercon_2x64_256_bd_s00_rs_256_0.xci" Type="IP"> + <Instance HierarchyPath="s00_rs_256"/> + <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + <File Name="ip/axi_intercon_2x64_256_bd_s01_cc_0/axi_intercon_2x64_256_bd_s01_cc_0.xci" Type="IP"> + <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/> + <Library Name="xil_defaultlib"/> + <UsedIn Val="SYNTHESIS"/> + <UsedIn Val="IMPLEMENTATION"/> + <UsedIn Val="SIMULATION"/> + </File> + </FileCollection> + </CompositeFile> +</Root> diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v new file mode 100644 index 000000000..06a471d59 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v @@ -0,0 +1,500 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_2x64_256_bd_wrapper + (M00_AXI_ACLK, + M00_AXI_ARESETN, + M00_AXI_ARADDR, + M00_AXI_ARBURST, + M00_AXI_ARCACHE, + M00_AXI_ARID, + M00_AXI_ARLEN, + M00_AXI_ARLOCK, + M00_AXI_ARPROT, + M00_AXI_ARQOS, + M00_AXI_ARREADY, + M00_AXI_ARREGION, + M00_AXI_ARSIZE, + M00_AXI_ARVALID, + M00_AXI_AWADDR, + M00_AXI_AWBURST, + M00_AXI_AWCACHE, + M00_AXI_AWID, + M00_AXI_AWLEN, + M00_AXI_AWLOCK, + M00_AXI_AWPROT, + M00_AXI_AWQOS, + M00_AXI_AWREADY, + M00_AXI_AWREGION, + M00_AXI_AWSIZE, + M00_AXI_AWVALID, + M00_AXI_BID, + M00_AXI_BREADY, + M00_AXI_BRESP, + M00_AXI_BVALID, + M00_AXI_RDATA, + M00_AXI_RID, + M00_AXI_RLAST, + M00_AXI_RREADY, + M00_AXI_RRESP, + M00_AXI_RVALID, + M00_AXI_WDATA, + M00_AXI_WLAST, + M00_AXI_WREADY, + M00_AXI_WSTRB, + M00_AXI_WVALID, + S00_AXI_ACLK, + S00_AXI_ARESETN, + S00_AXI_ARADDR, + S00_AXI_ARBURST, + S00_AXI_ARCACHE, + S00_AXI_ARID, + S00_AXI_ARLEN, + S00_AXI_ARLOCK, + S00_AXI_ARPROT, + S00_AXI_ARQOS, + S00_AXI_ARREADY, + S00_AXI_ARREGION, + S00_AXI_ARSIZE, + S00_AXI_ARVALID, + S00_AXI_AWADDR, + S00_AXI_AWBURST, + S00_AXI_AWCACHE, + S00_AXI_AWID, + S00_AXI_AWLEN, + S00_AXI_AWLOCK, + S00_AXI_AWPROT, + S00_AXI_AWQOS, + S00_AXI_AWREADY, + S00_AXI_AWREGION, + S00_AXI_AWSIZE, + S00_AXI_AWVALID, + S00_AXI_BID, + S00_AXI_BREADY, + S00_AXI_BRESP, + S00_AXI_BVALID, + S00_AXI_RDATA, + S00_AXI_RID, + S00_AXI_RLAST, + S00_AXI_RREADY, + S00_AXI_RRESP, + S00_AXI_RVALID, + S00_AXI_WDATA, + S00_AXI_WLAST, + S00_AXI_WREADY, + S00_AXI_WSTRB, + S00_AXI_WVALID, + S01_AXI_ACLK, + S01_AXI_ARESETN, + S01_AXI_ARADDR, + S01_AXI_ARBURST, + S01_AXI_ARCACHE, + S01_AXI_ARID, + S01_AXI_ARLEN, + S01_AXI_ARLOCK, + S01_AXI_ARPROT, + S01_AXI_ARQOS, + S01_AXI_ARREADY, + S01_AXI_ARREGION, + S01_AXI_ARSIZE, + S01_AXI_ARVALID, + S01_AXI_AWADDR, + S01_AXI_AWBURST, + S01_AXI_AWCACHE, + S01_AXI_AWID, + S01_AXI_AWLEN, + S01_AXI_AWLOCK, + S01_AXI_AWPROT, + S01_AXI_AWQOS, + S01_AXI_AWREADY, + S01_AXI_AWREGION, + S01_AXI_AWSIZE, + S01_AXI_AWVALID, + S01_AXI_BID, + S01_AXI_BREADY, + S01_AXI_BRESP, + S01_AXI_BVALID, + S01_AXI_RDATA, + S01_AXI_RID, + S01_AXI_RLAST, + S01_AXI_RREADY, + S01_AXI_RRESP, + S01_AXI_RVALID, + S01_AXI_WDATA, + S01_AXI_WLAST, + S01_AXI_WREADY, + S01_AXI_WSTRB, + S01_AXI_WVALID); + input M00_AXI_ACLK; + input M00_AXI_ARESETN; + output [31:0]M00_AXI_ARADDR; + output [1:0]M00_AXI_ARBURST; + output [3:0]M00_AXI_ARCACHE; + output [0:0]M00_AXI_ARID; + output [7:0]M00_AXI_ARLEN; + output [0:0]M00_AXI_ARLOCK; + output [2:0]M00_AXI_ARPROT; + output [3:0]M00_AXI_ARQOS; + input M00_AXI_ARREADY; + output [3:0]M00_AXI_ARREGION; + output [2:0]M00_AXI_ARSIZE; + output M00_AXI_ARVALID; + output [31:0]M00_AXI_AWADDR; + output [1:0]M00_AXI_AWBURST; + output [3:0]M00_AXI_AWCACHE; + output [0:0]M00_AXI_AWID; + output [7:0]M00_AXI_AWLEN; + output [0:0]M00_AXI_AWLOCK; + output [2:0]M00_AXI_AWPROT; + output [3:0]M00_AXI_AWQOS; + input M00_AXI_AWREADY; + output [3:0]M00_AXI_AWREGION; + output [2:0]M00_AXI_AWSIZE; + output M00_AXI_AWVALID; + input [0:0]M00_AXI_BID; + output M00_AXI_BREADY; + input [1:0]M00_AXI_BRESP; + input M00_AXI_BVALID; + input [255:0]M00_AXI_RDATA; + input [0:0]M00_AXI_RID; + input M00_AXI_RLAST; + output M00_AXI_RREADY; + input [1:0]M00_AXI_RRESP; + input M00_AXI_RVALID; + output [255:0]M00_AXI_WDATA; + output M00_AXI_WLAST; + input M00_AXI_WREADY; + output [31:0]M00_AXI_WSTRB; + output M00_AXI_WVALID; + input S00_AXI_ACLK; + input S00_AXI_ARESETN; + input [31:0]S00_AXI_ARADDR; + input [1:0]S00_AXI_ARBURST; + input [3:0]S00_AXI_ARCACHE; + input [0:0]S00_AXI_ARID; + input [7:0]S00_AXI_ARLEN; + input [0:0]S00_AXI_ARLOCK; + input [2:0]S00_AXI_ARPROT; + input [3:0]S00_AXI_ARQOS; + output S00_AXI_ARREADY; + input [3:0]S00_AXI_ARREGION; + input [2:0]S00_AXI_ARSIZE; + input S00_AXI_ARVALID; + input [31:0]S00_AXI_AWADDR; + input [1:0]S00_AXI_AWBURST; + input [3:0]S00_AXI_AWCACHE; + input [0:0]S00_AXI_AWID; + input [7:0]S00_AXI_AWLEN; + input [0:0]S00_AXI_AWLOCK; + input [2:0]S00_AXI_AWPROT; + input [3:0]S00_AXI_AWQOS; + output S00_AXI_AWREADY; + input [3:0]S00_AXI_AWREGION; + input [2:0]S00_AXI_AWSIZE; + input S00_AXI_AWVALID; + output [0:0]S00_AXI_BID; + input S00_AXI_BREADY; + output [1:0]S00_AXI_BRESP; + output S00_AXI_BVALID; + output [63:0]S00_AXI_RDATA; + output [0:0]S00_AXI_RID; + output S00_AXI_RLAST; + input S00_AXI_RREADY; + output [1:0]S00_AXI_RRESP; + output S00_AXI_RVALID; + input [63:0]S00_AXI_WDATA; + input S00_AXI_WLAST; + output S00_AXI_WREADY; + input [7:0]S00_AXI_WSTRB; + input S00_AXI_WVALID; + input S01_AXI_ACLK; + input S01_AXI_ARESETN; + input [31:0]S01_AXI_ARADDR; + input [1:0]S01_AXI_ARBURST; + input [3:0]S01_AXI_ARCACHE; + input [0:0]S01_AXI_ARID; + input [7:0]S01_AXI_ARLEN; + input [0:0]S01_AXI_ARLOCK; + input [2:0]S01_AXI_ARPROT; + input [3:0]S01_AXI_ARQOS; + output S01_AXI_ARREADY; + input [3:0]S01_AXI_ARREGION; + input [2:0]S01_AXI_ARSIZE; + input S01_AXI_ARVALID; + input [31:0]S01_AXI_AWADDR; + input [1:0]S01_AXI_AWBURST; + input [3:0]S01_AXI_AWCACHE; + input [0:0]S01_AXI_AWID; + input [7:0]S01_AXI_AWLEN; + input [0:0]S01_AXI_AWLOCK; + input [2:0]S01_AXI_AWPROT; + input [3:0]S01_AXI_AWQOS; + output S01_AXI_AWREADY; + input [3:0]S01_AXI_AWREGION; + input [2:0]S01_AXI_AWSIZE; + input S01_AXI_AWVALID; + output [0:0]S01_AXI_BID; + input S01_AXI_BREADY; + output [1:0]S01_AXI_BRESP; + output S01_AXI_BVALID; + output [63:0]S01_AXI_RDATA; + output [0:0]S01_AXI_RID; + output S01_AXI_RLAST; + input S01_AXI_RREADY; + output [1:0]S01_AXI_RRESP; + output S01_AXI_RVALID; + input [63:0]S01_AXI_WDATA; + input S01_AXI_WLAST; + output S01_AXI_WREADY; + input [7:0]S01_AXI_WSTRB; + input S01_AXI_WVALID; + + wire M00_AXI_ACLK; + wire M00_AXI_ARESETN; + wire [31:0]M00_AXI_ARADDR; + wire [1:0]M00_AXI_ARBURST; + wire [3:0]M00_AXI_ARCACHE; + wire [0:0]M00_AXI_ARID; + wire [7:0]M00_AXI_ARLEN; + wire [0:0]M00_AXI_ARLOCK; + wire [2:0]M00_AXI_ARPROT; + wire [3:0]M00_AXI_ARQOS; + wire M00_AXI_ARREADY; + wire [3:0]M00_AXI_ARREGION; + wire [2:0]M00_AXI_ARSIZE; + wire M00_AXI_ARVALID; + wire [31:0]M00_AXI_AWADDR; + wire [1:0]M00_AXI_AWBURST; + wire [3:0]M00_AXI_AWCACHE; + wire [0:0]M00_AXI_AWID; + wire [7:0]M00_AXI_AWLEN; + wire [0:0]M00_AXI_AWLOCK; + wire [2:0]M00_AXI_AWPROT; + wire [3:0]M00_AXI_AWQOS; + wire M00_AXI_AWREADY; + wire [3:0]M00_AXI_AWREGION; + wire [2:0]M00_AXI_AWSIZE; + wire M00_AXI_AWVALID; + wire [0:0]M00_AXI_BID; + wire M00_AXI_BREADY; + wire [1:0]M00_AXI_BRESP; + wire M00_AXI_BVALID; + wire [255:0]M00_AXI_RDATA; + wire [0:0]M00_AXI_RID; + wire M00_AXI_RLAST; + wire M00_AXI_RREADY; + wire [1:0]M00_AXI_RRESP; + wire M00_AXI_RVALID; + wire [255:0]M00_AXI_WDATA; + wire M00_AXI_WLAST; + wire M00_AXI_WREADY; + wire [31:0]M00_AXI_WSTRB; + wire M00_AXI_WVALID; + wire S00_AXI_ACLK; + wire S00_AXI_ARESETN; + wire [31:0]S00_AXI_ARADDR; + wire [1:0]S00_AXI_ARBURST; + wire [3:0]S00_AXI_ARCACHE; + wire [0:0]S00_AXI_ARID; + wire [7:0]S00_AXI_ARLEN; + wire [0:0]S00_AXI_ARLOCK; + wire [2:0]S00_AXI_ARPROT; + wire [3:0]S00_AXI_ARQOS; + wire S00_AXI_ARREADY; + wire [3:0]S00_AXI_ARREGION; + wire [2:0]S00_AXI_ARSIZE; + wire S00_AXI_ARVALID; + wire [31:0]S00_AXI_AWADDR; + wire [1:0]S00_AXI_AWBURST; + wire [3:0]S00_AXI_AWCACHE; + wire [0:0]S00_AXI_AWID; + wire [7:0]S00_AXI_AWLEN; + wire [0:0]S00_AXI_AWLOCK; + wire [2:0]S00_AXI_AWPROT; + wire [3:0]S00_AXI_AWQOS; + wire S00_AXI_AWREADY; + wire [3:0]S00_AXI_AWREGION; + wire [2:0]S00_AXI_AWSIZE; + wire S00_AXI_AWVALID; + wire [0:0]S00_AXI_BID; + wire S00_AXI_BREADY; + wire [1:0]S00_AXI_BRESP; + wire S00_AXI_BVALID; + wire [63:0]S00_AXI_RDATA; + wire [0:0]S00_AXI_RID; + wire S00_AXI_RLAST; + wire S00_AXI_RREADY; + wire [1:0]S00_AXI_RRESP; + wire S00_AXI_RVALID; + wire [63:0]S00_AXI_WDATA; + wire S00_AXI_WLAST; + wire S00_AXI_WREADY; + wire [7:0]S00_AXI_WSTRB; + wire S00_AXI_WVALID; + wire S01_AXI_ACLK; + wire S01_AXI_ARESETN; + wire [31:0]S01_AXI_ARADDR; + wire [1:0]S01_AXI_ARBURST; + wire [3:0]S01_AXI_ARCACHE; + wire [0:0]S01_AXI_ARID; + wire [7:0]S01_AXI_ARLEN; + wire [0:0]S01_AXI_ARLOCK; + wire [2:0]S01_AXI_ARPROT; + wire [3:0]S01_AXI_ARQOS; + wire S01_AXI_ARREADY; + wire [3:0]S01_AXI_ARREGION; + wire [2:0]S01_AXI_ARSIZE; + wire S01_AXI_ARVALID; + wire [31:0]S01_AXI_AWADDR; + wire [1:0]S01_AXI_AWBURST; + wire [3:0]S01_AXI_AWCACHE; + wire [0:0]S01_AXI_AWID; + wire [7:0]S01_AXI_AWLEN; + wire [0:0]S01_AXI_AWLOCK; + wire [2:0]S01_AXI_AWPROT; + wire [3:0]S01_AXI_AWQOS; + wire S01_AXI_AWREADY; + wire [3:0]S01_AXI_AWREGION; + wire [2:0]S01_AXI_AWSIZE; + wire S01_AXI_AWVALID; + wire [0:0]S01_AXI_BID; + wire S01_AXI_BREADY; + wire [1:0]S01_AXI_BRESP; + wire S01_AXI_BVALID; + wire [63:0]S01_AXI_RDATA; + wire [0:0]S01_AXI_RID; + wire S01_AXI_RLAST; + wire S01_AXI_RREADY; + wire [1:0]S01_AXI_RRESP; + wire S01_AXI_RVALID; + wire [63:0]S01_AXI_WDATA; + wire S01_AXI_WLAST; + wire S01_AXI_WREADY; + wire [7:0]S01_AXI_WSTRB; + wire S01_AXI_WVALID; + + axi_intercon_2x64_256_bd axi_intercon_2x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID)); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc new file mode 100644 index 000000000..2f5ba57c6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_4X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v + +BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \ +axi_intercon_4x64_256_bd.bd.out \ +axi_intercon_4x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd new file mode 100644 index 000000000..eb6c30100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd @@ -0,0 +1,2191 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:isValidated="true" bd:synthFlowMode="None" bd:tool_version="2015.4" bd:top="axi_intercon_4x64_256_bd" bd:version="1.00.a"> + + <spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>BlockDiagram</spirit:library> + <spirit:name>axi_intercon_4x64_256_bd</spirit:name> + <spirit:version>1.00.a</spirit:version> + <spirit:parameters> + <spirit:parameter> + <spirit:name>isTop</spirit:name> + <spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value> + </spirit:parameter> + </spirit:parameters> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>M00_AXI</spirit:name> + <spirit:master/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>200000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user_prop"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="ip_prop"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="ip_prop"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_M00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S00_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S01_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S01_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S02_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S03_AXI</spirit:name> + <spirit:slave/> + <spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:parameters> + <spirit:parameter> + <spirit:name>DATA_WIDTH</spirit:name> + <spirit:value>64</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PROTOCOL</spirit:name> + <spirit:value>AXI4</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>350000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ID_WIDTH</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ADDR_WIDTH</spirit:name> + <spirit:value>32</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>AWUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ARUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>WUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>RUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>BUSER_WIDTH</spirit:name> + <spirit:value>0</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>READ_WRITE_MODE</spirit:name> + <spirit:value>READ_WRITE</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_LOCK</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_PROT</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_CACHE</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_QOS</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_REGION</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_WSTRB</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_BRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>HAS_RRESP</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>SUPPORTS_NARROW_BURST</spirit:name> + <spirit:value>1</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_READ_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name> + <spirit:value>2</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>MAX_BURST_LENGTH</spirit:name> + <spirit:value>256</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>PHASE</spirit:name> + <spirit:value>0.000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="default"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + <spirit:parameter> + <spirit:name>CLK_DOMAIN</spirit:name> + <spirit:value>axi_intercon_4x64_128_bd_S00_ACLK</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>CLK.M00_AXI_ACLK</spirit:name> + <spirit:displayName>Clk</spirit:displayName> + <spirit:description>Clock</spirit:description> + <spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>M00_AXI_ACLK</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>FREQ_HZ</spirit:name> + <spirit:value>200000000</spirit:value> + <spirit:vendorExtensions> + <bd:configElementInfos> + <bd:configElementInfo bd:valueSource="user"/> + </bd:configElementInfos> + </spirit:vendorExtensions> + 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b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v new file mode 100644 index 000000000..71e446f92 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v @@ -0,0 +1,419 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_4x64_256_bd_wrapper ( + input M00_AXI_ACLK, + input M00_AXI_ARESETN, + output [31:0]M00_AXI_ARADDR, + output [1:0]M00_AXI_ARBURST, + output [3:0]M00_AXI_ARCACHE, + output [3:0]M00_AXI_ARID, + output [7:0]M00_AXI_ARLEN, + output [0:0]M00_AXI_ARLOCK, + output [2:0]M00_AXI_ARPROT, + output [3:0]M00_AXI_ARQOS, + input M00_AXI_ARREADY, + output [3:0]M00_AXI_ARREGION, + output [2:0]M00_AXI_ARSIZE, + output M00_AXI_ARVALID, + output [31:0]M00_AXI_AWADDR, + output [1:0]M00_AXI_AWBURST, + output [3:0]M00_AXI_AWCACHE, + output [3:0]M00_AXI_AWID, + output [7:0]M00_AXI_AWLEN, + output [0:0]M00_AXI_AWLOCK, + output [2:0]M00_AXI_AWPROT, + output [3:0]M00_AXI_AWQOS, + input M00_AXI_AWREADY, + output [3:0]M00_AXI_AWREGION, + output [2:0]M00_AXI_AWSIZE, + output M00_AXI_AWVALID, + input [3:0]M00_AXI_BID, + output M00_AXI_BREADY, + input [1:0]M00_AXI_BRESP, + input M00_AXI_BVALID, + input [255:0]M00_AXI_RDATA, + input [3:0]M00_AXI_RID, + input M00_AXI_RLAST, + output M00_AXI_RREADY, + input [1:0]M00_AXI_RRESP, + input M00_AXI_RVALID, + output [255:0]M00_AXI_WDATA, + output M00_AXI_WLAST, + input M00_AXI_WREADY, + output [31:0]M00_AXI_WSTRB, + output M00_AXI_WVALID, + input S00_AXI_ACLK, + input S00_AXI_ARESETN, + input [31:0]S00_AXI_ARADDR, + input [1:0]S00_AXI_ARBURST, + input [3:0]S00_AXI_ARCACHE, + input [0:0]S00_AXI_ARID, + input [7:0]S00_AXI_ARLEN, + input [0:0]S00_AXI_ARLOCK, + input [2:0]S00_AXI_ARPROT, + input [3:0]S00_AXI_ARQOS, + output S00_AXI_ARREADY, + input [3:0]S00_AXI_ARREGION, + input [2:0]S00_AXI_ARSIZE, + input S00_AXI_ARVALID, + input [31:0]S00_AXI_AWADDR, + input [1:0]S00_AXI_AWBURST, + input [3:0]S00_AXI_AWCACHE, + input [0:0]S00_AXI_AWID, + input [7:0]S00_AXI_AWLEN, + input [0:0]S00_AXI_AWLOCK, + input [2:0]S00_AXI_AWPROT, + input [3:0]S00_AXI_AWQOS, + output S00_AXI_AWREADY, + input [3:0]S00_AXI_AWREGION, + input [2:0]S00_AXI_AWSIZE, + input S00_AXI_AWVALID, + output [0:0]S00_AXI_BID, + input S00_AXI_BREADY, + output [1:0]S00_AXI_BRESP, + output S00_AXI_BVALID, + output [63:0]S00_AXI_RDATA, + output [0:0]S00_AXI_RID, + output S00_AXI_RLAST, + input S00_AXI_RREADY, + output [1:0]S00_AXI_RRESP, + output S00_AXI_RVALID, + input [63:0]S00_AXI_WDATA, + input S00_AXI_WLAST, + output S00_AXI_WREADY, + input [7:0]S00_AXI_WSTRB, + input S00_AXI_WVALID, + input S01_AXI_ACLK, + input S01_AXI_ARESETN, + input [31:0]S01_AXI_ARADDR, + input [1:0]S01_AXI_ARBURST, + input [3:0]S01_AXI_ARCACHE, + input [0:0]S01_AXI_ARID, + input [7:0]S01_AXI_ARLEN, + input [0:0]S01_AXI_ARLOCK, + input [2:0]S01_AXI_ARPROT, + input [3:0]S01_AXI_ARQOS, + output S01_AXI_ARREADY, + input [3:0]S01_AXI_ARREGION, + input [2:0]S01_AXI_ARSIZE, + input S01_AXI_ARVALID, + input [31:0]S01_AXI_AWADDR, + input [1:0]S01_AXI_AWBURST, + input [3:0]S01_AXI_AWCACHE, + input [0:0]S01_AXI_AWID, + input [7:0]S01_AXI_AWLEN, + input [0:0]S01_AXI_AWLOCK, + input [2:0]S01_AXI_AWPROT, + input [3:0]S01_AXI_AWQOS, + output S01_AXI_AWREADY, + input [3:0]S01_AXI_AWREGION, + input [2:0]S01_AXI_AWSIZE, + input S01_AXI_AWVALID, + output [0:0]S01_AXI_BID, + input S01_AXI_BREADY, + output [1:0]S01_AXI_BRESP, + output S01_AXI_BVALID, + output [63:0]S01_AXI_RDATA, + output [0:0]S01_AXI_RID, + output S01_AXI_RLAST, + input S01_AXI_RREADY, + output [1:0]S01_AXI_RRESP, + output S01_AXI_RVALID, + input [63:0]S01_AXI_WDATA, + input S01_AXI_WLAST, + output S01_AXI_WREADY, + input [7:0]S01_AXI_WSTRB, + input S01_AXI_WVALID, + input S02_AXI_ACLK, + input S02_AXI_ARESETN, + input [31:0]S02_AXI_ARADDR, + input [1:0]S02_AXI_ARBURST, + input [3:0]S02_AXI_ARCACHE, + input [0:0]S02_AXI_ARID, + input [7:0]S02_AXI_ARLEN, + input [0:0]S02_AXI_ARLOCK, + input [2:0]S02_AXI_ARPROT, + input [3:0]S02_AXI_ARQOS, + output S02_AXI_ARREADY, + input [3:0]S02_AXI_ARREGION, + input [2:0]S02_AXI_ARSIZE, + input S02_AXI_ARVALID, + input [31:0]S02_AXI_AWADDR, + input [1:0]S02_AXI_AWBURST, + input [3:0]S02_AXI_AWCACHE, + input [0:0]S02_AXI_AWID, + input [7:0]S02_AXI_AWLEN, + input [0:0]S02_AXI_AWLOCK, + input [2:0]S02_AXI_AWPROT, + input [3:0]S02_AXI_AWQOS, + output S02_AXI_AWREADY, + input [3:0]S02_AXI_AWREGION, + input [2:0]S02_AXI_AWSIZE, + input S02_AXI_AWVALID, + output [0:0]S02_AXI_BID, + input S02_AXI_BREADY, + output [1:0]S02_AXI_BRESP, + output S02_AXI_BVALID, + output [63:0]S02_AXI_RDATA, + output [0:0]S02_AXI_RID, + output S02_AXI_RLAST, + input S02_AXI_RREADY, + output [1:0]S02_AXI_RRESP, + output S02_AXI_RVALID, + input [63:0]S02_AXI_WDATA, + input S02_AXI_WLAST, + output S02_AXI_WREADY, + input [7:0]S02_AXI_WSTRB, + input S02_AXI_WVALID, + input S03_AXI_ACLK, + input S03_AXI_ARESETN, + input [31:0]S03_AXI_ARADDR, + input [1:0]S03_AXI_ARBURST, + input [3:0]S03_AXI_ARCACHE, + input [0:0]S03_AXI_ARID, + input [7:0]S03_AXI_ARLEN, + input [0:0]S03_AXI_ARLOCK, + input [2:0]S03_AXI_ARPROT, + input [3:0]S03_AXI_ARQOS, + output S03_AXI_ARREADY, + input [3:0]S03_AXI_ARREGION, + input [2:0]S03_AXI_ARSIZE, + input S03_AXI_ARVALID, + input [31:0]S03_AXI_AWADDR, + input [1:0]S03_AXI_AWBURST, + input [3:0]S03_AXI_AWCACHE, + input [0:0]S03_AXI_AWID, + input [7:0]S03_AXI_AWLEN, + input [0:0]S03_AXI_AWLOCK, + input [2:0]S03_AXI_AWPROT, + input [3:0]S03_AXI_AWQOS, + output S03_AXI_AWREADY, + input [3:0]S03_AXI_AWREGION, + input [2:0]S03_AXI_AWSIZE, + input S03_AXI_AWVALID, + output [0:0]S03_AXI_BID, + input S03_AXI_BREADY, + output [1:0]S03_AXI_BRESP, + output S03_AXI_BVALID, + output [63:0]S03_AXI_RDATA, + output [0:0]S03_AXI_RID, + output S03_AXI_RLAST, + input S03_AXI_RREADY, + output [1:0]S03_AXI_RRESP, + output S03_AXI_RVALID, + input [63:0]S03_AXI_WDATA, + input S03_AXI_WLAST, + output S03_AXI_WREADY, + input [7:0]S03_AXI_WSTRB, + input S03_AXI_WVALID +); + + axi_intercon_4x64_256_bd axi_intercon_4x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID), + .S02_AXI_ACLK(S02_AXI_ACLK), + .S02_AXI_ARESETN(S02_AXI_ARESETN), + .S02_AXI_araddr(S02_AXI_ARADDR), + .S02_AXI_arburst(S02_AXI_ARBURST), + .S02_AXI_arcache(S02_AXI_ARCACHE), + .S02_AXI_arid(S02_AXI_ARID), + .S02_AXI_arlen(S02_AXI_ARLEN), + .S02_AXI_arlock(S02_AXI_ARLOCK), + .S02_AXI_arprot(S02_AXI_ARPROT), + .S02_AXI_arqos(S02_AXI_ARQOS), + .S02_AXI_arready(S02_AXI_ARREADY), + .S02_AXI_arregion(S02_AXI_ARREGION), + .S02_AXI_arsize(S02_AXI_ARSIZE), + .S02_AXI_arvalid(S02_AXI_ARVALID), + .S02_AXI_awaddr(S02_AXI_AWADDR), + .S02_AXI_awburst(S02_AXI_AWBURST), + .S02_AXI_awcache(S02_AXI_AWCACHE), + .S02_AXI_awid(S02_AXI_AWID), + .S02_AXI_awlen(S02_AXI_AWLEN), + .S02_AXI_awlock(S02_AXI_AWLOCK), + .S02_AXI_awprot(S02_AXI_AWPROT), + .S02_AXI_awqos(S02_AXI_AWQOS), + .S02_AXI_awready(S02_AXI_AWREADY), + .S02_AXI_awregion(S02_AXI_AWREGION), + .S02_AXI_awsize(S02_AXI_AWSIZE), + .S02_AXI_awvalid(S02_AXI_AWVALID), + .S02_AXI_bid(S02_AXI_BID), + .S02_AXI_bready(S02_AXI_BREADY), + .S02_AXI_bresp(S02_AXI_BRESP), + .S02_AXI_bvalid(S02_AXI_BVALID), + .S02_AXI_rdata(S02_AXI_RDATA), + .S02_AXI_rid(S02_AXI_RID), + .S02_AXI_rlast(S02_AXI_RLAST), + .S02_AXI_rready(S02_AXI_RREADY), + .S02_AXI_rresp(S02_AXI_RRESP), + .S02_AXI_rvalid(S02_AXI_RVALID), + .S02_AXI_wdata(S02_AXI_WDATA), + .S02_AXI_wlast(S02_AXI_WLAST), + .S02_AXI_wready(S02_AXI_WREADY), + .S02_AXI_wstrb(S02_AXI_WSTRB), + .S02_AXI_wvalid(S02_AXI_WVALID), + .S03_AXI_ACLK(S03_AXI_ACLK), + .S03_AXI_ARESETN(S03_AXI_ARESETN), + .S03_AXI_araddr(S03_AXI_ARADDR), + .S03_AXI_arburst(S03_AXI_ARBURST), + .S03_AXI_arcache(S03_AXI_ARCACHE), + .S03_AXI_arid(S03_AXI_ARID), + .S03_AXI_arlen(S03_AXI_ARLEN), + .S03_AXI_arlock(S03_AXI_ARLOCK), + .S03_AXI_arprot(S03_AXI_ARPROT), + .S03_AXI_arqos(S03_AXI_ARQOS), + .S03_AXI_arready(S03_AXI_ARREADY), + .S03_AXI_arregion(S03_AXI_ARREGION), + .S03_AXI_arsize(S03_AXI_ARSIZE), + .S03_AXI_arvalid(S03_AXI_ARVALID), + .S03_AXI_awaddr(S03_AXI_AWADDR), + .S03_AXI_awburst(S03_AXI_AWBURST), + .S03_AXI_awcache(S03_AXI_AWCACHE), + .S03_AXI_awid(S03_AXI_AWID), + .S03_AXI_awlen(S03_AXI_AWLEN), + .S03_AXI_awlock(S03_AXI_AWLOCK), + .S03_AXI_awprot(S03_AXI_AWPROT), + .S03_AXI_awqos(S03_AXI_AWQOS), + .S03_AXI_awready(S03_AXI_AWREADY), + .S03_AXI_awregion(S03_AXI_AWREGION), + .S03_AXI_awsize(S03_AXI_AWSIZE), + .S03_AXI_awvalid(S03_AXI_AWVALID), + .S03_AXI_bid(S03_AXI_BID), + .S03_AXI_bready(S03_AXI_BREADY), + .S03_AXI_bresp(S03_AXI_BRESP), + .S03_AXI_bvalid(S03_AXI_BVALID), + .S03_AXI_rdata(S03_AXI_RDATA), + .S03_AXI_rid(S03_AXI_RID), + .S03_AXI_rlast(S03_AXI_RLAST), + .S03_AXI_rready(S03_AXI_RREADY), + .S03_AXI_rresp(S03_AXI_RRESP), + .S03_AXI_rvalid(S03_AXI_RVALID), + .S03_AXI_wdata(S03_AXI_WDATA), + .S03_AXI_wlast(S03_AXI_WLAST), + .S03_AXI_wready(S03_AXI_WREADY), + .S03_AXI_wstrb(S03_AXI_WSTRB), + .S03_AXI_wvalid(S03_AXI_WVALID) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc new file mode 100644 index 000000000..a169c12bf --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCONNECT_SRCS = $(IP_BUILD_DIR)/axi_interconnect/axi_interconnect.xci + +IP_AXI_INTERCONNECT = $(addprefix $(IP_BUILD_DIR)/axi_interconnect/, \ +axi_interconnect.xci.out \ +synth/axi_interconnect.v \ +) + +$(IP_AXI_INTERCONNECT_SRCS) $(IP_AXI_INTERCONNECT_OUTS) : $(IP_DIR)/axi_interconnect/axi_interconnect.xci + $(call BUILD_VIVADO_IP,axi_interconnect,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + diff --git a/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci b/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci new file mode 100644 index 000000000..8af91b716 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci @@ -0,0 +1,2674 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>axi_interconnect</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_crossbar" spirit:version="2.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKIF.ASSOCIATED_RESET"/> + <spirit:configurableElementValue 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b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXIS_FIFO_TO_AXI4LITE_SRCS = $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci + +IP_AXIS_FIFO_TO_AXI4LITE_OUTS = $(addprefix $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/, \ +axis_fifo_to_axi4lite.xci.out \ +) + +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) $(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) : $(IP_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci + $(call BUILD_VIVADO_IP,axis_fifo_to_axi4lite,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci new file mode 100644 index 000000000..80d8104d5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci @@ -0,0 +1,267 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design 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spirit:referenceId="MODELPARAM_VALUE.C_TX_FIFO_PF_THRESHOLD">2043</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RX_CUT_THROUGH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RX_DATA">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_CTRL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_CUT_THROUGH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TX_DATA">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI4_BASEADDR">0x80001000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI4_HIGHADDR">0x80002FFF</spirit:configurableElementValue> + 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spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXD_PROTOCOL">XIL_AXI_STREAM_ETH_DATA</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AXI_STR_TXD_TDATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BASEADDR">0x80000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_INTERFACE_TYPE">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TDEST">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TID">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TKEEP">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_AXIS_TSTRB">false</spirit:configurableElementValue> + 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spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.HAS_TKEEP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_RXD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.HAS_TREADY" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXC.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TKEEP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.HAS_TLAST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_STR_TXD.TDATA_NUM_BYTES" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_FULL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo 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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_RX_FIFO_DEPTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_RX_FIFO_PF_THRESHOLD" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_DEPTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TX_FIFO_PF_THRESHOLD" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_TX_CTRL" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..e96eaf838 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_xc7z*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..f72f56759 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2648 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>ddr3_32bit</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mig_7series" spirit:version="4.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue 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xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_LOCK" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_PROT" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_QOS" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.PROTOCOL" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S7_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BOARD_MIG_PARAM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XML_INPUT_FILE" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj new file mode 100644 index 000000000..495ca2a8b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj @@ -0,0 +1,164 @@ +<?xml version='1.0' encoding='UTF-8'?> +<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --> +<Project NoOfControllers="1" > + <ModuleName>ddr3_32bit</ModuleName> + <dci_inouts_inputs>1</dci_inouts_inputs> + <dci_inputs>1</dci_inputs> + <Debug_En>OFF</Debug_En> + <DataDepth_En>1024</DataDepth_En> + <LowPower_En>ON</LowPower_En> + <XADC_En>Disabled</XADC_En> + <TargetFPGA>xc7z035-ffg900/-2</TargetFPGA> + <Version>4.0</Version> + <SystemClock>Differential</SystemClock> + <ReferenceClock>No Buffer</ReferenceClock> + <SysResetPolarity>ACTIVE LOW</SysResetPolarity> + <BankSelectionFlag>FALSE</BankSelectionFlag> + <InternalVref>0</InternalVref> + <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs> + <dci_cascade>0</dci_cascade> + <FPGADevice> + <selected>7z/xc7z035-ffg900</selected> + </FPGADevice> + <Controller number="0" > + <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice> + <TimePeriod>1538</TimePeriod> + <VccAuxIO>1.8V</VccAuxIO> + <PHYRatio>4:1</PHYRatio> + <InputClkFreq>100.03</InputClkFreq> + <UIExtraClocks>0</UIExtraClocks> + <MMCM_VCO>650</MMCM_VCO> + <MMCMClkOut0> 1.000</MMCMClkOut0> + <MMCMClkOut1>1</MMCMClkOut1> + <MMCMClkOut2>1</MMCMClkOut2> + <MMCMClkOut3>1</MMCMClkOut3> + <MMCMClkOut4>1</MMCMClkOut4> + <DataWidth>32</DataWidth> + <DeepMemory>1</DeepMemory> + <DataMask>1</DataMask> + <ECC>Disabled</ECC> + <Ordering>Normal</Ordering> + <BankMachineCnt>4</BankMachineCnt> + <CustomPart>TRUE</CustomPart> + <NewPartName>MT41K512M16XX-125</NewPartName> + <RowAddress>16</RowAddress> + <ColAddress>10</ColAddress> + <BankAddress>3</BankAddress> + <MemoryVoltage>1.5V</MemoryVoltage> + <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap> + <PinSelection> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D8" SLEW="" name="ddr3_addr[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B6" SLEW="" name="ddr3_addr[10]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H7" SLEW="" name="ddr3_addr[11]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B7" SLEW="" name="ddr3_addr[12]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F7" SLEW="" name="ddr3_addr[13]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F8" SLEW="" name="ddr3_addr[14]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F9" SLEW="" name="ddr3_addr[15]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A7" SLEW="" name="ddr3_addr[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C7" SLEW="" name="ddr3_addr[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D9" SLEW="" name="ddr3_addr[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J9" SLEW="" name="ddr3_addr[4]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E8" SLEW="" name="ddr3_addr[5]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G7" SLEW="" name="ddr3_addr[6]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E7" SLEW="" name="ddr3_addr[7]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G11" SLEW="" name="ddr3_addr[8]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C6" SLEW="" name="ddr3_addr[9]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C9" SLEW="" name="ddr3_ba[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E10" SLEW="" name="ddr3_ba[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B9" SLEW="" name="ddr3_ba[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A10" SLEW="" name="ddr3_cas_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="H8" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="J8" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E11" SLEW="" name="ddr3_cke[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D11" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B16" SLEW="" name="ddr3_dm[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B11" SLEW="" name="ddr3_dm[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H13" SLEW="" name="ddr3_dm[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G15" SLEW="" name="ddr3_dm[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="" name="ddr3_dq[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dq[10]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="" name="ddr3_dq[11]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[12]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C12" SLEW="" name="ddr3_dq[13]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="" name="ddr3_dq[14]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C11" SLEW="" name="ddr3_dq[15]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[16]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[17]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[18]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[19]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A17" SLEW="" name="ddr3_dq[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J14" SLEW="" name="ddr3_dq[20]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K15" SLEW="" name="ddr3_dq[21]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J16" SLEW="" name="ddr3_dq[22]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[23]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[24]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dq[25]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[26]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[27]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[28]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[29]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="" name="ddr3_dq[30]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[31]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="" name="ddr3_dq[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="" name="ddr3_dq[4]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[5]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[6]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[7]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="" name="ddr3_dq[8]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="" name="ddr3_dq[9]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L13" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D10" SLEW="" name="ddr3_odt[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B10" SLEW="" name="ddr3_ras_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="D6" SLEW="" name="ddr3_reset_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A9" SLEW="" name="ddr3_we_n" IN_TERM="" /> + </PinSelection> + <System_Clock> + <Pin PADName="H9/G9(CC_P/N)" Bank="34" name="sys_clk_p/n" /> + </System_Clock> + <System_Control> + <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" /> + <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" /> + <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" /> + </System_Control> + <TimingParameters> + <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="350" trp="13.75" tras="35" trcd="13.75" /> + </TimingParameters> + <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength> + <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType> + <mrCasLatency name="CAS Latency" >9</mrCasLatency> + <mrMode name="Mode" >Normal</mrMode> + <mrDllReset name="DLL Reset" >No</mrDllReset> + <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode> + <emrDllEnable name="DLL Enable" >Enable</emrDllEnable> + <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength> + <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection> + <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection> + <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT> + <emrPosted name="Additive Latency (AL)" >0</emrPosted> + <emrOCD name="Write Leveling Enable" >Disabled</emrOCD> + <emrDQS name="TDQS enable" >Enabled</emrDQS> + <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS> + <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh> + <mr2CasWriteLatency name="CAS write latency" >7</mr2CasWriteLatency> + <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh> + <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange> + <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> + <PortInterface>AXI</PortInterface> + <AXIParameters> + <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM> + <C0_S_AXI_ADDR_WIDTH>31</C0_S_AXI_ADDR_WIDTH> + <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH> + <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH> + <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST> + </AXIParameters> + </Controller> + +</Project> diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj new file mode 100644 index 000000000..ffad2f7f8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj @@ -0,0 +1,164 @@ +<?xml version='1.0' encoding='UTF-8'?> +<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --> +<Project NoOfControllers="1" > + <ModuleName>ddr3_32bit</ModuleName> + <dci_inouts_inputs>1</dci_inouts_inputs> + <dci_inputs>1</dci_inputs> + <Debug_En>OFF</Debug_En> + <DataDepth_En>1024</DataDepth_En> + <LowPower_En>ON</LowPower_En> + <XADC_En>Disabled</XADC_En> + <TargetFPGA>xc7z100-ffg900/-2</TargetFPGA> + <Version>4.0</Version> + <SystemClock>Differential</SystemClock> + <ReferenceClock>No Buffer</ReferenceClock> + <SysResetPolarity>ACTIVE LOW</SysResetPolarity> + <BankSelectionFlag>FALSE</BankSelectionFlag> + <InternalVref>0</InternalVref> + <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs> + <dci_cascade>0</dci_cascade> + <FPGADevice> + <selected>7z/xc7z035-ffg900</selected> + </FPGADevice> + <Controller number="0" > + <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice> + <TimePeriod>1538</TimePeriod> + <VccAuxIO>1.8V</VccAuxIO> + <PHYRatio>4:1</PHYRatio> + <InputClkFreq>100.03</InputClkFreq> + <UIExtraClocks>0</UIExtraClocks> + <MMCM_VCO>650</MMCM_VCO> + <MMCMClkOut0> 1.000</MMCMClkOut0> + <MMCMClkOut1>1</MMCMClkOut1> + <MMCMClkOut2>1</MMCMClkOut2> + <MMCMClkOut3>1</MMCMClkOut3> + <MMCMClkOut4>1</MMCMClkOut4> + <DataWidth>32</DataWidth> + <DeepMemory>1</DeepMemory> + <DataMask>1</DataMask> + <ECC>Disabled</ECC> + <Ordering>Normal</Ordering> + <BankMachineCnt>4</BankMachineCnt> + <CustomPart>TRUE</CustomPart> + <NewPartName>MT41K512M16XX-125</NewPartName> + <RowAddress>16</RowAddress> + <ColAddress>10</ColAddress> + <BankAddress>3</BankAddress> + <MemoryVoltage>1.5V</MemoryVoltage> + <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap> + <PinSelection> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D8" SLEW="" name="ddr3_addr[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B6" SLEW="" name="ddr3_addr[10]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H7" SLEW="" name="ddr3_addr[11]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B7" SLEW="" name="ddr3_addr[12]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F7" SLEW="" name="ddr3_addr[13]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F8" SLEW="" name="ddr3_addr[14]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F9" SLEW="" name="ddr3_addr[15]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A7" SLEW="" name="ddr3_addr[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C7" SLEW="" name="ddr3_addr[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D9" SLEW="" name="ddr3_addr[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J9" SLEW="" name="ddr3_addr[4]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E8" SLEW="" name="ddr3_addr[5]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G7" SLEW="" name="ddr3_addr[6]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E7" SLEW="" name="ddr3_addr[7]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G11" SLEW="" name="ddr3_addr[8]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C6" SLEW="" name="ddr3_addr[9]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C9" SLEW="" name="ddr3_ba[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E10" SLEW="" name="ddr3_ba[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B9" SLEW="" name="ddr3_ba[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A10" SLEW="" name="ddr3_cas_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="H8" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="J8" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E11" SLEW="" name="ddr3_cke[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D11" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B16" SLEW="" name="ddr3_dm[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B11" SLEW="" name="ddr3_dm[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H13" SLEW="" name="ddr3_dm[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="G15" SLEW="" name="ddr3_dm[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="" name="ddr3_dq[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dq[10]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="" name="ddr3_dq[11]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[12]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C12" SLEW="" name="ddr3_dq[13]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="" name="ddr3_dq[14]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C11" SLEW="" name="ddr3_dq[15]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[16]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[17]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[18]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[19]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A17" SLEW="" name="ddr3_dq[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J14" SLEW="" name="ddr3_dq[20]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K15" SLEW="" name="ddr3_dq[21]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J16" SLEW="" name="ddr3_dq[22]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[23]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[24]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dq[25]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[26]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[27]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[28]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[29]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="" name="ddr3_dq[30]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[31]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="" name="ddr3_dq[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="" name="ddr3_dq[4]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[5]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[6]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[7]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="" name="ddr3_dq[8]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="" name="ddr3_dq[9]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L13" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D10" SLEW="" name="ddr3_odt[0]" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B10" SLEW="" name="ddr3_ras_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="D6" SLEW="" name="ddr3_reset_n" IN_TERM="" /> + <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A9" SLEW="" name="ddr3_we_n" IN_TERM="" /> + </PinSelection> + <System_Clock> + <Pin PADName="H9/G9(CC_P/N)" Bank="34" name="sys_clk_p/n" /> + </System_Clock> + <System_Control> + <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" /> + <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" /> + <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" /> + </System_Control> + <TimingParameters> + <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="350" trp="13.75" tras="35" trcd="13.75" /> + </TimingParameters> + <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength> + <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType> + <mrCasLatency name="CAS Latency" >9</mrCasLatency> + <mrMode name="Mode" >Normal</mrMode> + <mrDllReset name="DLL Reset" >No</mrDllReset> + <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode> + <emrDllEnable name="DLL Enable" >Enable</emrDllEnable> + <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength> + <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection> + <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection> + <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT> + <emrPosted name="Additive Latency (AL)" >0</emrPosted> + <emrOCD name="Write Leveling Enable" >Disabled</emrOCD> + <emrDQS name="TDQS enable" >Enabled</emrDQS> + <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS> + <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh> + <mr2CasWriteLatency name="CAS write latency" >7</mr2CasWriteLatency> + <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh> + <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange> + <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> + <PortInterface>AXI</PortInterface> + <AXIParameters> + <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM> + <C0_S_AXI_ADDR_WIDTH>31</C0_S_AXI_ADDR_WIDTH> + <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH> + <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH> + <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST> + </AXIParameters> + </Controller> + +</Project> diff --git a/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..888840273 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>fifo_4k_2clk</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue> + <spirit:configurableElementValue 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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo 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b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..cc0f896b8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>fifo_short_2clk</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/> + <spirit:configurableElementValue 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spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> + <spirit:configurableElementValue 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spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + 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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/> + <xilinx:configElementInfo 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</xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc b/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc new file mode 100644 index 000000000..14b705d1d --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_1TO2_SRCS = $(IP_BUILD_DIR)/hb47_1to2/hb47_1to2.xci + +IP_HB47_1TO2_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_1to2/, \ +hb47_1to2.xci.out \ +synth/hb47_1to2.vhd \ +) + +$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : $(IP_DIR)/hb47_1to2/hb47_1to2.xci + $(call BUILD_VIVADO_IP,hb47_1to2,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci b/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci new file mode 100644 index 000000000..a192027fb --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci @@ -0,0 +1,294 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>hb47_1to2</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/> + <spirit:configurableElementValue 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xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SamplePeriod" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Sample_Frequency" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc b/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc new file mode 100644 index 000000000..293f64d3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_2TO1_SRCS = $(IP_BUILD_DIR)/hb47_2to1/hb47_2to1.xci + +IP_HB47_2TO1_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_2to1/, \ +hb47_2to1.xci.out \ +synth/hb47_2to1.vhd \ +) + +$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : $(IP_DIR)/hb47_2to1/hb47_2to1.xci $(IP_DIR)/hb47_2to1/hb47.coe + $(call BUILD_VIVADO_IP,hb47_2to1,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe new file mode 100644 index 000000000..4c9a6c406 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0 + 194, + 0, +-62; diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci new file mode 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timing constraints are handled in one place (timing.xdc) +$(IP_MISC_CLOCK_GEN_SRCS) $(IP_MISC_CLOCK_GEN_OUTS) : $(IP_DIR)/misc_clock_gen/misc_clock_gen.xci + $(call BUILD_VIVADO_IP,misc_clock_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + diff --git a/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci new file mode 100644 index 000000000..2a2cc31ef --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci @@ -0,0 +1,739 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + 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spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue 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spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">166.666667</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue> + 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spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">59.989999999999995</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">113.755</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">141.292</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">198.412704761</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">105.705</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">141.292</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">305.55555</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">81.390</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">326.622</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">81.390</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">326.622</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFGCE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">meas_clk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">ddr3_dma_clk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">misc_clock_gen</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">21.875</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">6.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">6.125</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">166.666667</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">true</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue> + <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue> + </spirit:configurableElementValues> + <spirit:vendorExtensions> + <xilinx:componentInstanceExtensions> + <xilinx:configElementInfos> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_SEL" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OVERRIDE_MMCM" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMARY_PORT" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SECONDARY_SOURCE" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" xilinx:valueSource="user"/> + <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM" xilinx:valueSource="user"/> + </xilinx:configElementInfos> + </xilinx:componentInstanceExtensions> + </spirit:vendorExtensions> + </spirit:componentInstance> + </spirit:componentInstances> +</spirit:design> diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc new file mode 100644 index 000000000..26f994676 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc @@ -0,0 +1,35 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak +include $(LIB_DIR)/rfnoc/utils/Makefile.srcs + +IP_N310_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/n310_ps_bd/, \ +n310_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_N310_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/n310_ps_bd/, \ +n310_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_N310_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS) + +IP_N310_PS_BD_SRCS = $(IP_BUILD_DIR)/n310_ps_bd/n310_ps_bd/n310_ps_bd.bd + +BD_N310_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/n310_ps_bd/, \ +n310_ps_bd.bd.out \ +n310_ps_bd/n310_ps_bd_ooc.xdc \ +) + +$(IP_N310_PS_BD_SRCS) $(BD_N310_PS_BD_OUTS) $(IP_N310_PS_BDTCL_SRCS): $(IP_N310_PS_ORIG_SRCS) $(IP_N310_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,n310_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_N310_PS_HDL_SRCS)) + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl new file mode 100644 index 000000000..387f67d9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl @@ -0,0 +1,59 @@ +# Hierarchical cell: mtu +proc create_hier_cell_mtu { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create cells and wire everything up + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs] + # BUG: Vivado 2015.4 does not connect nets the first time with just the driver + connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs] + + for {set i 0} {$i < $numPorts} {incr i} { + # Create instance: xlslice_0, and set properties + set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ] + set_property -dict [ list \ + CONFIG.DIN_FROM [expr $i * 32 + 15] \ + CONFIG.DIN_TO [expr $i * 32] \ + CONFIG.DIN_WIDTH [expr $numPorts * 32] \ + CONFIG.DOUT_WIDTH {16} \ + ] $xlslice + + connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din] + + create_bd_pin -dir O -from 15 -to 0 mtu$i + connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl new file mode 100644 index 000000000..500771071 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl @@ -0,0 +1,339 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_frame_size.tcl" + +proc create_hier_cell_rx_dma_channel { parentCell nameHier } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_pin -dir I -from 15 -to 0 frame_size + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type rst m_dest_axi_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + + ######################### + # Instantiate IPs + ######################### + set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + CONFIG.C_OPERATION {not} \ + ] $reset_inv + + set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ] + set_property -dict [ list \ + CONFIG.CHDR_W {64} \ + ] $chdr_padder + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst] + + set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ] + set_property -dict [ list \ + CONFIG.ASYNC_CLK_DEST_REQ {true} \ + CONFIG.ASYNC_CLK_REQ_SRC {true} \ + CONFIG.ASYNC_CLK_SRC_DEST {false} \ + CONFIG.DMA_AXI_PROTOCOL_DEST {1} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_rx_dmac + + ######################### + # Wiring + ######################### + + # Top-level connections + connect_bd_net -net aclk_1 \ + [get_bd_pins s_axis_aclk] \ + [get_bd_pins chdr_padder/clk] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axis_aclk] + connect_bd_net -net aresetn_1 \ + [get_bd_pins m_dest_axi_aresetn] \ + [get_bd_pins reset_inv/Op1] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn] + connect_bd_net -net areset_1 \ + [get_bd_pins reset_inv/Res] \ + [get_bd_pins chdr_padder/rst] + connect_bd_net -net s_axi_aclk_1 \ + [get_bd_pins s_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 \ + [get_bd_pins s_axi_aresetn] \ + [get_bd_pins axi_rx_dmac/s_axi_aresetn] + connect_bd_net -net axi_rx_dmac_irq \ + [get_bd_pins irq] \ + [get_bd_pins axi_rx_dmac/irq] + connect_bd_net -net mtu \ + [get_bd_pins frame_size] \ + [get_bd_pins chdr_padder/len] + + # Control and DMA ports + connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \ + [get_bd_intf_pins s_axi] \ + [get_bd_intf_pins axi_rx_dmac/s_axi] + connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \ + [get_bd_intf_pins m_dest_axi] \ + [get_bd_intf_pins axi_rx_dmac/m_dest_axi] + + # AXI-Stream ports + connect_bd_intf_net -intf_net s_axis_dma \ + [get_bd_intf_pins S_AXIS] \ + [get_bd_intf_pins chdr_padder/s_axis] + connect_bd_intf_net -intf_net s_axis_dma_padded \ + [get_bd_intf_pins chdr_padder/m_axis] \ + [get_bd_intf_pins axi_rx_dmac/s_axis] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx +proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_rx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + ######################### + # Instantiate IPs + ######################### + # For sharing one S_AXI_HP port across all RX DMA engines + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + CONFIG.R_REGISTER {1} \ + ] $axi_crossbar_0 + + # For fanning out AXI-Lite bus to all RX DMA engines + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + # Routes AXI-Stream to appropriate RX DMA engine + set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI $numPorts \ + CONFIG.NUM_SI {1} \ + ] $axis_switch_0 + + # Cross domains from incoming AXI-Stream to RX DMA engines domain + # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we + # are limited to 16 RX DMA channels + set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ] + set_property -dict [ list \ + CONFIG.Clock_Type_AXI {Independent_Clock} \ + CONFIG.Empty_Threshold_Assert_Value_axis {1021} \ + CONFIG.Empty_Threshold_Assert_Value_rach {13} \ + CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wach {13} \ + CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {13} \ + CONFIG.Enable_TLAST {true} \ + CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.HAS_TKEEP {false} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TKEEP_WIDTH {0} \ + CONFIG.TSTRB_WIDTH {8} \ + CONFIG.TUSER_WIDTH {0} \ + ] $fifo_generator_0 + + set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $rx_dmac_irq_concat + + create_hier_cell_mtu $hier_obj mtu $numPorts + + ######################### + # Wiring + ######################### + connect_bd_intf_net -intf_net S00_AXIS_1 \ + [get_bd_intf_pins S_AXIS_DMA] \ + [get_bd_intf_pins fifo_generator_0/S_AXIS] + + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + + connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \ + [get_bd_intf_pins axis_switch_0/S00_AXIS] \ + [get_bd_intf_pins fifo_generator_0/M_AXIS] + + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + + connect_bd_net -net aresetn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins fifo_generator_0/s_aresetn] + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins fifo_generator_0/s_aclk] + + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] \ + [get_bd_pins axis_switch_0/aclk] \ + [get_bd_pins fifo_generator_0/m_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axis_switch_0/aresetn] + + connect_bd_net -net mtu_regs_1 \ + [get_bd_pins mtu_regs] \ + [get_bd_pins mtu/mtu_regs] + + connect_bd_net -net rx_dmac_irq_concat_dout \ + [get_bd_pins irq] \ + [get_bd_pins rx_dmac_irq_concat/dout] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + puts "Instantiating rx_dma port ${i}" + create_hier_cell_rx_dma_channel $hier_obj dma$i + + set_property -dict [ list \ + [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \ + ] $axi_crossbar_0 + + connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \ + [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \ + [get_bd_intf_pins dma${i}/S_AXIS] + + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/s_axi] + + connect_bd_intf_net -intf_net dma${i}_m_dest_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/m_dest_axi] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \ + [get_bd_pins dma${i}/s_axi_aclk] \ + [get_bd_pins dma${i}/s_axis_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins dma${i}/m_dest_axi_aresetn] \ + [get_bd_pins dma${i}/s_axi_aresetn] + + connect_bd_net -net dma${i}_irq \ + [get_bd_pins dma${i}/irq] \ + [get_bd_pins rx_dmac_irq_concat/In${i}] + + connect_bd_net -net frame_size_${i} \ + [get_bd_pins dma${i}/frame_size] \ + [get_bd_pins mtu/mtu${i}] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl new file mode 100644 index 000000000..9a4e832aa --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl @@ -0,0 +1,159 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_rx.tcl" +source "$scriptDir/chdr_dma_tx.tcl" + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 2 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + ######################### + # Instantiate IPs + ######################### + # Create instance: rx + create_hier_cell_rx_dma $hier_obj rx $numPorts + + # Create instance: tx + create_hier_cell_tx_dma $hier_obj tx $numPorts + + # Used to set frame size of RX DMA engines + set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ] + set_property -dict [ list \ +CONFIG.NUM_REGS $numPorts \ + ] $axi_regfile_0 + + set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_0 + + set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_1 + + ######################### + # Wiring + ######################### + # Clocks and resets + connect_bd_net -net bus_clk_1 \ + [get_bd_pins bus_clk] \ + [get_bd_pins rx/bus_clk] \ + [get_bd_pins tx/bus_clk] + connect_bd_net -net bus_rstn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins rx/bus_rstn] \ + [get_bd_pins tx/bus_rstn] + connect_bd_net -net clk40_1 \ + [get_bd_pins clk40] \ + [get_bd_pins rx/clk40] \ + [get_bd_pins tx/clk40] \ + [get_bd_pins axi_regfile_0/S_AXI_ACLK] + connect_bd_net -net clk40_rstn_1 \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \ + [get_bd_pins rx/clk40_rstn] \ + [get_bd_pins tx/clk40_rstn] + + # AXI buses + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins rx/s_axi_rx_dmac] + connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins rx/M_AXI_RX_DMA] + connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins tx/s_axi_tx_dmac] + connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins tx/M_AXI_TX_DMA] + connect_bd_intf_net -intf_net s_axi_regfile_1 \ + [get_bd_intf_pins s_axi_regfile] \ + [get_bd_intf_pins axi_regfile_0/S_AXI] + + # RX CHDR + connect_bd_intf_net -intf_net s_axis_dma_1 \ + [get_bd_intf_pins s_axis_dma] \ + [get_bd_intf_pins rx/S_AXIS_DMA] + + # TX CHDR + connect_bd_intf_net -intf_net m_axis_dma_1 \ + [get_bd_intf_pins tx/M_AXIS_DMA] \ + [get_bd_intf_pins m_axis_dma] + + # IRQs and Frame Sizes + connect_bd_net -net frame_sizes \ + [get_bd_pins axi_regfile_0/regs] \ + [get_bd_pins rx/mtu_regs] + connect_bd_net -net rx_irq1 \ + [get_bd_pins rx/irq] \ + [get_bd_pins util_reduced_logic_0/Op1] + connect_bd_net -net tx_irq1 \ + [get_bd_pins tx/irq] \ + [get_bd_pins util_reduced_logic_1/Op1] + connect_bd_net -net util_reduced_logic_0_Res \ + [get_bd_pins rx_irq] \ + [get_bd_pins util_reduced_logic_0/Res] + connect_bd_net -net util_reduced_logic_1_Res \ + [get_bd_pins tx_irq] \ + [get_bd_pins util_reduced_logic_1/Res] + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl new file mode 100644 index 000000000..e2d160f69 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl @@ -0,0 +1,193 @@ +# Hierarchical cell: tx +proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_tx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + + ######################### + # Instantiate IPs + ######################### + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts + ] $axi_crossbar_0 + + set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ARB_ON_TLAST {1} \ + CONFIG.ARB_ON_MAX_XFERS {0} \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_REGSLICE {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + ] $axis_interconnect_0 + + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $xlconcat_0 + + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + ######################### + # Wiring + ######################### + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins axis_interconnect_0/ACLK] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] + connect_bd_net -net bus_rstn \ + [get_bd_pins bus_rstn] \ + [get_bd_pins axis_interconnect_0/ARESETN] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconcat_0_dout \ + [get_bd_pins irq] \ + [get_bd_pins xlconcat_0/dout] + + connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \ + [get_bd_intf_pins M_AXIS_DMA] \ + [get_bd_intf_pins axis_interconnect_0/M00_AXIS] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + # Configure each port on axi_crossbar and axis_interconnect + puts "Creating TX dma port ${i}" + set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0 + set_property -dict [ list \ + [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \ + ] $axis_interconnect_0 + + set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ] + set_property -dict [ list \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + ] $axi_tx_dmac + + # Add a tuser signal indicating which DMA channel originated the packet + # Hard-coded to handle up to 16 DMA channels + # Convert i (in decimal) to 4-bit binary: + binary scan [binary format c ${i}] B* i_binary + set i_binary [string range ${i_binary} end-3 end] + + set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ] + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \ + ] $tuser_appender + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH {4} \ + CONFIG.TUSER_REMAP 4'b${i_binary} \ + ] $tuser_appender + + connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \ + [get_bd_intf_pins $axi_tx_dmac/m_axis] \ + [get_bd_intf_pins ${tuser_appender}/S_AXIS] + connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \ + [get_bd_intf_pins ${tuser_appender}/M_AXIS] \ + [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]] + connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/m_src_axi] + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/s_axi] + + connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\ + [get_bd_pins $axi_tx_dmac/m_axis_aclk] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \ + [get_bd_pins $axi_tx_dmac/s_axi_aclk] \ + [get_bd_pins $tuser_appender/aclk] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \ + [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \ + [get_bd_pins $tuser_appender/aresetn] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl new file mode 100644 index 000000000..b3516e2fa --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl @@ -0,0 +1,726 @@ +# CHANGE DESIGN NAME HERE +set design_name n310_ps_bd + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name +current_bd_design $design_name + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +set scriptDir [file dirname [info script]] + +################################################################## +# DESIGN PROCs +################################################################## +source "$scriptDir/chdr_dma_top.tcl" + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.HAS_TLAST 1 \ + CONFIG.TDATA_NUM_BYTES 8 \ + CONFIG.TDEST_WIDTH 4 \ + ] $s_axis_dma + set WR_UART [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 WR_UART ] + set M_AXI_ETH_DMA0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_ETH_DMA0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_ETH_DMA0 + set M_AXI_WR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_WR ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {62500000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_WR + set M_AXI_ETH_DMA1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_ETH_DMA1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_ETH_DMA1 + set M_AXI_JESD0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_JESD0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_JESD0 + set M_AXI_JESD1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_JESD1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_JESD1 + set M_AXI_NET0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET0 + set M_AXI_NET1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET1 + set M_AXI_NET2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET2 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET2 + set M_AXI_XBAR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_XBAR ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_XBAR + set S_AXI_GP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_GP0 + set S_AXI_GP1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_GP1 + set S_AXI_HP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP0 + set S_AXI_HP1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP1 + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + # Create ports + set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] + set DDR_VRP [ create_bd_port -dir IO DDR_VRP ] + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ] + set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set FCLK_RESET1_N [ create_bd_port -dir O -type rst FCLK_RESET1_N ] + set FCLK_RESET2_N [ create_bd_port -dir O -type rst FCLK_RESET2_N ] + set FCLK_RESET3_N [ create_bd_port -dir O -type rst FCLK_RESET3_N ] + set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ] + set_property -dict [ list \ +CONFIG.PortWidth {16} \ +CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $IRQ_F2P + set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ] + set PS_CLK [ create_bd_port -dir IO PS_CLK ] + set PS_PORB [ create_bd_port -dir IO PS_PORB ] + set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ] + set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ] + set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ] + set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ] + set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ] + set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ] + set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ] + set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ] + set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ] + set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ] + set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ] + set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ] + set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ] + set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ] + set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ] + set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ] + set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ] + set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ] + set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ] + set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ] + set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ] + set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ] + set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ] + set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ] + set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ] + set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ] + set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] + set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] + set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] + set JTAG0_TCK [ create_bd_port -dir IO JTAG0_TCK ] + set JTAG0_TMS [ create_bd_port -dir IO JTAG0_TMS ] + set JTAG0_TDI [ create_bd_port -dir IO JTAG0_TDI ] + set JTAG0_TDO [ create_bd_port -dir I JTAG0_TDO ] + set JTAG1_TCK [ create_bd_port -dir IO JTAG1_TCK ] + set JTAG1_TMS [ create_bd_port -dir IO JTAG1_TMS ] + set JTAG1_TDI [ create_bd_port -dir IO JTAG1_TDI ] + set JTAG1_TDO [ create_bd_port -dir I JTAG1_TDO ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP0_ACLK + set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] + set S_AXI_GP1_ACLK [ create_bd_port -dir I -type clk S_AXI_GP1_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_GP1_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP1_ACLK + set S_AXI_GP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP1_ARESETN ] + set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ] + set_property -dict [ list \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP0_ACLK + set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ] + set S_AXI_HP1_ACLK [ create_bd_port -dir I -type clk S_AXI_HP1_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_HP1_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP1_ACLK + set S_AXI_HP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP1_ARESETN ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ +CONFIG.ASSOCIATED_RESET {bus_rstn} \ +CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + + set M_AXI_WR_CLK [ create_bd_port -dir I -type clk M_AXI_WR_CLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {M_AXI_WR} \ +CONFIG.ASSOCIATED_RESET {M_AXI_WR_RSTn} \ +CONFIG.FREQ_HZ {62500000} \ + ] $M_AXI_WR_CLK + set M_AXI_WR_RSTn [ create_bd_port -dir I -type rst M_AXI_WR_RSTn ] + + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {M_AXI_NET0:M_AXI_NET1:M_AXI_XBAR:M_AXI_JESD0:M_AXI_JESD1:M_AXI_ETH_DMA0:M_AXI_ETH_DMA1:M_AXI_NET2} \ +CONFIG.ASSOCIATED_RESET {clk40_rstn} \ +CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + create_bd_port -dir I qsfp_sda_i + create_bd_port -dir O qsfp_sda_o + create_bd_port -dir O qsfp_sda_t + create_bd_port -dir I qsfp_scl_i + create_bd_port -dir O qsfp_scl_o + create_bd_port -dir O qsfp_scl_t + + # Create instance: axi_interconnect_hp0, and set properties + set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp0 + + set axi_interconnect_hp1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp1 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp1 + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {16} \ + ] $axi_interconnect_0 + + # Create instance: axi_uartlite_0, and set properties + set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ +CONFIG.C_BAUDRATE {115200} \ + ] $axi_uartlite_0 + + # Create instance: dma + create_hier_cell_dma [current_bd_instance .] dma 10 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {800} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_IO {MIO 6} \ +CONFIG.PCW_EN_CLK1_PORT {1} \ +CONFIG.PCW_EN_CLK2_PORT {1} \ +CONFIG.PCW_EN_CLK3_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {1} \ +CONFIG.PCW_EN_RST2_PORT {1} \ +CONFIG.PCW_EN_RST3_PORT {1} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C0_RESET_ENABLE {1} \ +CONFIG.PCW_I2C0_RESET_IO {MIO 3} \ +CONFIG.PCW_IRQ_F2P_INTR {1} \ +CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 7} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ +CONFIG.PCW_USE_S_AXI_GP0 {0} \ +CONFIG.PCW_USE_S_AXI_GP1 {0} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ +CONFIG.PCW_USE_S_AXI_HP2 {1} \ +CONFIG.PCW_USE_S_AXI_HP3 {1} \ + ] $processing_system7_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ +CONFIG.IN0_WIDTH {8} \ +CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {7} \ +CONFIG.DIN_TO {0} \ +CONFIG.DIN_WIDTH {16} \ +CONFIG.DOUT_WIDTH {8} \ + ] $xlslice_2 + + # Create instance: jtag_0, jtag_1 + set jtag_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 jtag_0 ] + set jtag_1 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 jtag_1 ] + + # Create instance: axi_iic_0 for QSFP i2c + set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] + + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net S_AXI_GP0_1 [get_bd_intf_ports S_AXI_GP0] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_GP1_1 [get_bd_intf_ports S_AXI_GP1] [get_bd_intf_pins axi_interconnect_hp1/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_HP0_1 [get_bd_intf_ports S_AXI_HP0] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI] + connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports S_AXI_HP1] [get_bd_intf_pins axi_interconnect_hp1/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M_AXI_ETH_DMA0] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M_AXI_NET0] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M_AXI_ETH_DMA1] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M_AXI_NET1] [get_bd_intf_pins axi_interconnect_0/M03_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M_AXI_XBAR] [get_bd_intf_pins axi_interconnect_0/M04_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M_AXI_JESD0] [get_bd_intf_pins axi_interconnect_0/M05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M_AXI_JESD1] [get_bd_intf_pins axi_interconnect_0/M06_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M_AXI_NET2] [get_bd_intf_pins axi_interconnect_0/M07_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_pins axi_interconnect_0/M10_AXI] [get_bd_intf_pins dma/s_axi_regfile] + connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_pins jtag_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M11_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M12_AXI [get_bd_intf_pins jtag_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M12_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M13_AXI [get_bd_intf_pins axi_interconnect_0/M13_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M14_AXI [get_bd_intf_ports M_AXI_WR] [get_bd_intf_pins axi_interconnect_0/M14_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M15_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M15_AXI] + + connect_bd_intf_net -intf_net axi_protocol_converter_hp0_M_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net axi_protocol_converter_hp1_M_AXI [get_bd_intf_pins axi_interconnect_hp1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP3] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma] + connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0] + connect_bd_intf_net -intf_net WR_UART [get_bd_intf_ports WR_UART] [get_bd_intf_pins axi_uartlite_0/UART] + + # Create port connections + connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din] + connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I] + connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I] + connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I] + connect_bd_net -net SPI1_MISO_I_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] + connect_bd_net -net SPI1_MOSI_I_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] + connect_bd_net -net SPI1_SCLK_I_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] + connect_bd_net -net SPI1_SS_I_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_pins axi_interconnect_hp0/S01_ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_pins axi_interconnect_hp0/S01_ARESETN] + connect_bd_net -net S_AXI_HP1_ACLK_1 [get_bd_pins axi_interconnect_hp1/S01_ACLK] + connect_bd_net -net S_AXI_HP1_ARESETN_1 [get_bd_pins axi_interconnect_hp1/S01_ARESETN] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/ARESETN] + connect_bd_net -net S_AXI_HP1_ACLK_1 [get_bd_ports S_AXI_HP1_ACLK] [get_bd_pins axi_interconnect_hp1/M00_ACLK] [get_bd_pins axi_interconnect_hp1/S00_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins axi_interconnect_hp1/ACLK] + connect_bd_net -net S_AXI_HP1_ARESETN_1 [get_bd_ports S_AXI_HP1_ARESETN] [get_bd_pins axi_interconnect_hp1/M00_ARESETN] [get_bd_pins axi_interconnect_hp1/S00_ARESETN] [get_bd_pins axi_interconnect_hp1/ARESETN] + connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] + connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_interconnect_0/M12_ACLK] [get_bd_pins axi_interconnect_0/M15_ACLK] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/M12_ARESETN] [get_bd_pins axi_interconnect_0/M15_ARESETN] [get_bd_pins dma/clk40_rstn] + connect_bd_net -net M_AXI_WR_CLK [get_bd_ports M_AXI_WR_CLK] [get_bd_pins axi_interconnect_0/M14_ACLK] + connect_bd_net -net M_AXI_WR_RSTn [get_bd_ports M_AXI_WR_RSTn] [get_bd_pins axi_interconnect_0/M14_ARESETN] + connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN] + connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP] + connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins jtag_0/S_AXI_ACLK] [get_bd_pins jtag_1/S_AXI_ACLK] [get_bd_pins axi_iic_0/s_axi_aclk] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins jtag_0/S_AXI_ARESETN] [get_bd_pins jtag_1/S_AXI_ARESETN] [get_bd_pins axi_iic_0/s_axi_aresetn] + connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_ports FCLK_RESET1_N] [get_bd_pins processing_system7_0/FCLK_RESET1_N] + connect_bd_net -net processing_system7_0_FCLK_RESET2_N [get_bd_ports FCLK_RESET2_N] [get_bd_pins processing_system7_0/FCLK_RESET2_N] + connect_bd_net -net processing_system7_0_FCLK_RESET3_N [get_bd_ports FCLK_RESET3_N] [get_bd_pins processing_system7_0/FCLK_RESET3_N] + connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O] + connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T] + connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O] + connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T] + connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O] + connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T] + connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O] + connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O] + connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T] + connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O] + connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O] + connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T] + connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK] + connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB] + connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB] + connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout] + connect_bd_net -net JTAG0_TCK [get_bd_ports JTAG0_TCK] [get_bd_pins jtag_0/bit_clk] + connect_bd_net -net JTAG0_TMS [get_bd_ports JTAG0_TMS] [get_bd_pins jtag_0/bit_stb] + connect_bd_net -net JTAG0_TDI [get_bd_ports JTAG0_TDI] [get_bd_pins jtag_0/bit_out] + connect_bd_net -net JTAG0_TDO [get_bd_ports JTAG0_TDO] [get_bd_pins jtag_0/bit_in] + connect_bd_net -net JTAG1_TCK [get_bd_ports JTAG1_TCK] [get_bd_pins jtag_1/bit_clk] + connect_bd_net -net JTAG1_TMS [get_bd_ports JTAG1_TMS] [get_bd_pins jtag_1/bit_stb] + connect_bd_net -net JTAG1_TDI [get_bd_ports JTAG1_TDI] [get_bd_pins jtag_1/bit_out] + connect_bd_net -net JTAG1_TDO [get_bd_ports JTAG1_TDO] [get_bd_pins jtag_1/bit_in] + connect_bd_net [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In3] + connect_bd_net [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins xlconcat_0/In4] + connect_bd_net -net qsfp_sda_i [get_bd_pins axi_iic_0/sda_i] [get_bd_ports qsfp_sda_i] + connect_bd_net -net qsfp_sda_o [get_bd_pins axi_iic_0/sda_o] [get_bd_ports qsfp_sda_o] + connect_bd_net -net qsfp_sda_t [get_bd_pins axi_iic_0/sda_t] [get_bd_ports qsfp_sda_t] + connect_bd_net -net qsfp_scl_i [get_bd_pins axi_iic_0/scl_i] [get_bd_ports qsfp_scl_i] + connect_bd_net -net qsfp_scl_o [get_bd_pins axi_iic_0/scl_o] [get_bd_ports qsfp_scl_o] + connect_bd_net -net qsfp_scl_t [get_bd_pins axi_iic_0/scl_t] [get_bd_ports qsfp_scl_t] + connect_bd_net [get_bd_ports clk40] [get_bd_pins axi_uartlite_0/s_axi_aclk] + connect_bd_net [get_bd_ports clk40_rstn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] + connect_bd_net [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M13_ACLK] + connect_bd_net [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M13_ARESETN] + + # Create address segments + create_bd_addr_seg -range 0x4000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA0/Reg] SEG_M_AXI_ETH_DMA0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40008000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA1/Reg] SEG_M_AXI_ETH_DMA1_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40014000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD0/Reg] SEG_M_AXI_JESD0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET0/Reg] SEG_M_AXI_NET0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x4000C000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET1/Reg] SEG_M_AXI_NET1_Reg + create_bd_addr_seg -range 0x20000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET2/Reg] SEG_M_AXI_NET2_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40018000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD1/Reg] SEG_M_AXI_JESD1_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_XBAR/Reg] SEG_M_AXI_XBAR_Reg + create_bd_addr_seg -range 0x10000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_dmac_0_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_dmac_1_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_dmac_2_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_dmac_3_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_dmac_4_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CF0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_5/s_axi/axi_lite] SEG_axi_dmac_5_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_6/s_axi/axi_lite] SEG_axi_dmac_6_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_7/s_axi/axi_lite] SEG_axi_dmac_7_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_8/s_axi/axi_lite] SEG_axi_dmac_8_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_9/s_axi/axi_lite] SEG_axi_dmac_9_axi_lite + create_bd_addr_seg -range 0x40000 -offset 0x43D40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_WR/Reg] SEG_M_AXI_WR_Reg + create_bd_addr_seg -range 0x10000 -offset 0x43D80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg + create_bd_addr_seg -range 0x1000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs + create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite11 + create_bd_addr_seg -range 0x10000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite13 + create_bd_addr_seg -range 0x10000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite15 + create_bd_addr_seg -range 0x10000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite17 + create_bd_addr_seg -range 0x10000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma5/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite19 + create_bd_addr_seg -range 0x10000 -offset 0x43C60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma6/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite21 + create_bd_addr_seg -range 0x10000 -offset 0x43C70000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma7/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite23 + create_bd_addr_seg -range 0x10000 -offset 0x43C80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma8/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite25 + create_bd_addr_seg -range 0x10000 -offset 0x43C90000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma9/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite27 + create_bd_addr_seg -range 0x1000 -offset 0x42100000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_0/S_AXI/reg0] SEG_jtag_0_reg0 + create_bd_addr_seg -range 0x1000 -offset 0x42200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_1/S_AXI/reg0] SEG_jtag_1_reg0 + create_bd_addr_seg -range 0x1000 -offset 0x42C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs {axi_uartlite_0/S_AXI/Reg }] SEG_WR_UART_Reg + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_5/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_6/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_7/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_8/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_9/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma5/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma6/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma7/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma8/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma9/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_GP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_HP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..b159ce4b6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,45 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..79d8850b4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,353 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>xilinx.com</spirit:vendor> + <spirit:library>xci</spirit:library> + <spirit:name>unknown</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:componentInstances> + <spirit:componentInstance> + <spirit:instanceName>one_gig_eth_pcs_pma</spirit:instanceName> + <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gig_ethernet_pcs_pma" spirit:version="16.1"/> + <spirit:configurableElementValues> + <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_INTERRUPT_PORT.PortWidth">1</spirit:configurableElementValue> + <spirit:configurableElementValue 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a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v new file mode 100644 index 000000000..e5e05c62b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v @@ -0,0 +1,188 @@ +//------------------------------------------------------------------------------ +// File : one_gig_eth_pcs_pma_clocking.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This module holds the Clocking logic for pcs/pma core. + + +`timescale 1 ps/1 ps + + +//------------------------------------------------------------------------------ +// The module declaration for the example design +//------------------------------------------------------------------------------ + +module one_gig_eth_pcs_pma_clocking + ( + input txoutclk, // txoutclk from GT transceiver. + input rxoutclk, // rxoutclk from GT transceiver. + input mmcm_reset, // MMCM Reset + output wire mmcm_locked, // MMCM locked + + output userclk, // for GT PMA reference clock + output userclk2, // 125MHz clock for core reference clock. + output rxuserclk, // for GT PMA reference clock + output rxuserclk2 // 125MHz clock for core reference clock. + ); + + wire clkout0; // MMCM output clock + wire clkout1; // MMCM output clock + wire clkfbout; // MMCM Feedback clock +// Route txoutclk input through a BUFG + wire txoutclk_bufg; + wire userclk_i; + wire rxoutclk_buf; + + //--------------------------------------------------------------------------- + // Transceiver Clock Management + //--------------------------------------------------------------------------- + + // Route txoutclk input through a BUFG + BUFG bufg_txoutclk ( + .I (txoutclk), + .O (txoutclk_bufg) + ); + + // The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is + // routed to an MMCM module where it is used to create phase and frequency + // related 62.5MHz and 125MHz clock sources + MMCME2_ADV # ( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.5), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.5), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (16.0), + .CLKFBOUT_MULT_F (16.000), + .CLKOUT0_DIVIDE_F (8.000), + .CLKOUT1_DIVIDE (16), + + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + // Output clocks + .CLKFBOUT (clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (clkout0), + .CLKOUT0B (), + .CLKOUT1 (clkout1), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN1 (txoutclk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + // This 62.5MHz clock is placed onto global clock routing and is then used + // for tranceiver TXUSRCLK/RXUSRCLK. + BUFG bufg_userclk ( + .I (clkout1), + .O (userclk_i) + ); + + + // This 125MHz clock is placed onto global clock routing and is then used + // to clock all Ethernet core logic. + BUFG bufg_userclk2 ( + .I (clkout0), + .O (userclk2) + ); + + + +assign userclk = userclk_i; + + + // Place the Rx recovered clock on a Global Clock Buffer (it may be possible + // to switch this for a BUFHCE/BUFR and BUFMR combination) + BUFG rxrecclkbufg ( + .I (rxoutclk), + .O (rxoutclk_buf) + ); + + assign rxuserclk2 = rxoutclk_buf; + assign rxuserclk = rxoutclk_buf; + +endmodule // one_gig_eth_pcs_pma_clocking diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v new file mode 100644 index 000000000..4c92d105a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v @@ -0,0 +1,238 @@ +//------------------------------------------------------------------------------ +// File : one_gig_eth_pcs_pma_support.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This module holds the support level for the pcs/pma core +// This can be used as-is in a single core design, or adapted +// for use with multi-core implementations + +`timescale 1 ps/1 ps +(* DowngradeIPIdentifiedWarnings="yes" *) + +//------------------------------------------------------------------------------ +// The module declaration for the Core Block wrapper. +//------------------------------------------------------------------------------ + +module one_gig_eth_pcs_pma_support + ( + // Transceiver Interface + //---------------------- + + + input gtrefclk, // gtrefclk routed through an IBUFG. + input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + output userclk_out, + output userclk2_out, + output rxuserclk_out, + output rxuserclk2_out, + input independent_clock_bufg, // Freerun Independent clock, + output pma_reset_out, // transceiver PMA reset signal + output mmcm_locked_out, // MMCM Locked + output resetdone, + // GMII Interface + //--------------- + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output [7:0] gmii_rxd, // Received Data to client MAC. + output gmii_rx_dv, // Received control signal to client MAC. + output gmii_rx_er, // Received control signal to client MAC. + output gmii_isolate, // Tristate control to electrically isolate GMII. + + // Management: MDIO Interface + //--------------------------- + + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + + input signal_detect, // Input from PMD to indicate presence of optical input. + input gt0_qplloutclk_in, + input gt0_qplloutrefclk_in + + + + ); + + + //--------------------------------------------------------------------------- + // Internal signals used in this block level wrapper. + //--------------------------------------------------------------------------- + + // Core <=> Transceiver interconnect + wire cplllock; // reset done indication from transceiver + wire mmcm_reset; // Reset to MMCM based on resetdone + wire mmcm_locked; // Signal indicating that MMCM has locked + wire pma_reset; // Reset synchronized to system clock + wire txoutclk; // txoutclk from GT transceiver (62.5MHz) + wire rxoutclk; // txoutclk from GT transceiver (62.5MHz) + wire userclk; + wire userclk2; + wire rxuserclk; + wire rxuserclk2; + + // GT Interface + //------------- + //wire gt0_qplloutclk; + //wire gt0_qplloutrefclk; + +one_gig_eth_pcs_pma +pcs_pma_i + ( + + // Transceiver Interface + //---------------------- + + .gtrefclk (gtrefclk), // Very high quality clock for GT transceiver. + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), // Differential +ve of serial transmission from PMA to PMD. + .txn (txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp (rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn (rxn), // Differential -ve for serial reception from PMD to PMA. + + .txoutclk (txoutclk), + .rxoutclk (rxoutclk), + .resetdone (resetdone), + .cplllock (cplllock), + .mmcm_reset (mmcm_reset), + .userclk (userclk), + .userclk2 (userclk2), + .rxuserclk (rxuserclk), + .rxuserclk2 (rxuserclk2), + .independent_clock_bufg (independent_clock_bufg), + .pma_reset (pma_reset), + .mmcm_locked (mmcm_locked), + + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .gmii_isolate (gmii_isolate), + + // Management: MDIO Interface + //--------------------------- + + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + + + // General IO's + //------------- + .status_vector (status_vector), // Core status. + .reset (pma_reset), // Asynchronous reset for entire core. + + .signal_detect (signal_detect) , // Input from PMD to indicate presence of optical input. + .gt0_qplloutclk_in (gt0_qplloutclk_in), + .gt0_qplloutrefclk_in (gt0_qplloutrefclk_in) + ); + + + //---------------------------------------------------------------------------- + // Instantiate the clocking module. + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_clocking core_clocking_i + ( + .txoutclk (txoutclk), + .rxoutclk (rxoutclk), + .mmcm_reset (mmcm_reset), + .mmcm_locked (mmcm_locked), + .userclk (userclk), + .userclk2 (userclk2), + .rxuserclk (rxuserclk), + .rxuserclk2 (rxuserclk2) + ); + +assign gtrefclk_out = gtrefclk; +assign gtrefclk_bufg_out = gtrefclk_bufg; +assign userclk_out = userclk; +assign userclk2_out = userclk2; +assign rxuserclk_out = rxuserclk; +assign rxuserclk2_out = rxuserclk2; + + + //--------------------------------------------------------------------------- + // Transceiver PMA reset circuitry + //--------------------------------------------------------------------------- + one_gig_eth_pcs_pma_resets core_resets_i + ( + .reset (reset), + .independent_clock_bufg (independent_clock_bufg), + + .pma_reset (pma_reset) + ); + +assign pma_reset_out = pma_reset; + + + assign mmcm_locked_out = mmcm_locked; + +endmodule // one_gig_eth_pcs_pma_support + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..b02424f03 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,105 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + input gt0_qplloutclk_in, + input gt0_qplloutrefclk_in, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO PHY Address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect, // Input from PMD to indicate presence of optical input. + output pma_reset_out +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (pma_reset_out), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_in (gt0_qplloutclk_in), + .gt0_qplloutrefclk_in (gt0_qplloutrefclk_in) + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc new file mode 100644 index 000000000..4dadace3b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc @@ -0,0 +1,164 @@ + + +#*********************************************************** +# The following constraints target the Transceiver Physical* +# Interface which is instantiated in the Example Design. * +#*********************************************************** +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i] + + +#----------------------------------------------------------- +# Clock source used for the IDELAY Controller (if present) - +# and for the transceiver reset circuitry - +#----------------------------------------------------------- + + +create_clock -name independent_clock -period 5.000 [get_ports independent_clock] + +#----------------------------------------------------------- +# PCS/PMA Clock period Constraints: please do not relax - +#----------------------------------------------------------- + +create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p] + + +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC H6 [get_ports gtrefclk_p] +#set_property LOC H5 [get_ports gtrefclk_n] + + +#*********************************************************** +# The following constraints target the GMII implemented in * +# the Example Design. * +#*********************************************************** +# If the GMII is intended to be an internal interface, * +# the GMII signals can be connected directly to user * +# logic and all of the following constraints in this file * +# should be removed. * +# * +# If the GMII is intended to be an external interface, * +# all of the following constraints in this file should be * +# maintained. * +#*********************************************************** + +#----------------------------------------------------------- +# GMII IOSTANDARD Constraints: please select an I/O - +# Standard (LVTTL is suggested). - +#----------------------------------------------------------- + +# Please update the IOSTANDARD according to that available in the device + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk] + +#----------------------------------------------------------- +# Lock down the GMII Tx signals to the same bank for low - +# skew. This is an example placement only. - +#----------------------------------------------------------- + + +#----------------------------------------------------------- +# To Adjust GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- +# These constraints will be set at a later date when device speed files have matured + +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en] +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er] + +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}] + + + +#----------------------------------------------------------- +# To check (analyze) GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- + +create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk] + + + +#----------------------------------------------------------- +# Fast Skew maximises output setup and hold timing - +#----------------------------------------------------------- +set_property SLEW FAST [get_ports {gmii_rxd[*]}] +set_property SLEW FAST [get_ports gmii_rx_dv] +set_property SLEW FAST [get_ports gmii_rx_er] +set_property SLEW FAST [get_ports gmii_rx_clk] + + +#----------------------------------------------------------- +# GMII Transmitter Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_txd_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_en_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_er_IBUF*] + +#----------------------------------------------------------- +# GMII Receiver Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_rxd_obuf_reg*] +#set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg] +#set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg] + + + +#----------------------------------------------------------- +# GMII Tx Elastic Buffer Constraints - +#----------------------------------------------------------- + +# Control Gray Code delay and skew across clock boundary +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}] +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}] + +# Constrain between Distributed Memory (output data) and the 1st set of flip-flops +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*/D}] + +set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] + +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..db95346bd --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/imports/, \ +ten_gig_eth_pcs_pma_example_design.v \ +ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +ten_gig_eth_pcs_pma_support.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..8af7da882 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,192 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:design xmlns:xilinx="http://www.xilinx.com" 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File : ten_gig_eth_pcs_pma_gt_common.v +//----------------------------------------------------------------------------- +// Description: This file contains the +// 10GBASE-R Transceiver GT Common block. +//----------------------------------------------------------------------------- +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + +`timescale 1ps / 1ps + +module ten_gig_eth_pcs_pma_gt_common # ( + parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware + ( + input refclk, + input qpllreset, + output qplllock, + output qplloutclk, + output qplloutrefclk, + input [2:0] qpllrefclksel + ); + + +//***************************** Parameter Declarations ************************ + localparam QPLL_FBDIV_TOP = 66; + + localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 : + (QPLL_FBDIV_TOP == 20) ? 10'b0000110000 : + (QPLL_FBDIV_TOP == 32) ? 10'b0001100000 : + (QPLL_FBDIV_TOP == 40) ? 10'b0010000000 : + (QPLL_FBDIV_TOP == 64) ? 10'b0011100000 : + (QPLL_FBDIV_TOP == 66) ? 10'b0101000000 : + (QPLL_FBDIV_TOP == 80) ? 10'b0100100000 : + (QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000; + + localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 : + (QPLL_FBDIV_TOP == 20) ? 1'b1 : + (QPLL_FBDIV_TOP == 32) ? 1'b1 : + (QPLL_FBDIV_TOP == 40) ? 1'b1 : + (QPLL_FBDIV_TOP == 64) ? 1'b1 : + (QPLL_FBDIV_TOP == 66) ? 1'b0 : + (QPLL_FBDIV_TOP == 80) ? 1'b1 : + (QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1; + +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + +//********************************* Main Body of Code************************** + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + + wire gt0_gtrefclk0_common_in; + wire gt0_qpllreset_in; + wire gt0_qplllock_out; + wire gt0_qplloutclk_i; + wire gt0_qplloutrefclk_i; + + assign gt0_gtrefclk0_common_in = refclk; + assign gt0_qpllreset_in = qpllreset; + assign qplllock = gt0_qplllock_out; + assign qplloutclk = gt0_qplloutclk_i; + assign qplloutrefclk = gt0_qplloutrefclk_i; + + + //_________________________________________________________________________ + //_________________________________________________________________________ + //_________________________GTXE2_COMMON____________________________________ + + GTXE2_COMMON # + ( + // Simulation attributes + .SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("4.0"), + + + //----------------COMMON BLOCK Attributes--------------- + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (27'h0680181), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV_IN), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (1) + ) + gtxe2_common_0_i + ( + //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + .DRPADDR (tied_to_ground_vec_i[7:0]), + .DRPCLK (tied_to_ground_i), + .DRPDI (tied_to_ground_vec_i[15:0]), + .DRPDO (), + .DRPEN (tied_to_ground_i), + .DRPRDY (), + .DRPWE (tied_to_ground_i), + //-------------------- Common Block - Ref Clock Ports --------------------- + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (gt0_gtrefclk0_common_in), + .GTREFCLK1 (tied_to_ground_i), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //--------------------- Common Block - Clocking Ports ---------------------- + .QPLLOUTCLK (gt0_qplloutclk_i), + .QPLLOUTREFCLK (gt0_qplloutrefclk_i), + .REFCLKOUTMONITOR (), + //----------------------- Common Block - QPLL Ports ------------------------ + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .QPLLLOCK (gt0_qplllock_out), + .QPLLLOCKDETCLK (1'b0), + .QPLLLOCKEN (tied_to_vcc_i), + .QPLLOUTRESET (tied_to_ground_i), + .QPLLPD (tied_to_ground_i), + .QPLLREFCLKLOST (), + .QPLLREFCLKSEL (qpllrefclksel), + .QPLLRESET (gt0_qpllreset_in), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + //------------------------------- QPLL Ports ------------------------------- + .BGBYPASSB (tied_to_vcc_i), + .BGMONITORENB (tied_to_vcc_i), + .BGPDB (tied_to_vcc_i), + .BGRCALOVRD (5'b11111), + .PMARSVD (8'b00000000), + .RCALENB (tied_to_vcc_i) + + ); + + + + + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..5c798136f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,241 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable, + output qpllreset, + input qplllock, + input qplloutclk, + input qplloutrefclk, + output tx_out_clk +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + assign tx_out_clk = txclk322; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .rxrecclk_out(), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc new file mode 100644 index 000000000..3e637368a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc @@ -0,0 +1,91 @@ +## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. + +create_clock -period 6.400 [get_ports {dclk}] + +create_clock -period 6.400 [get_ports refclk_p] + +create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] + +# False paths for async reset removal synchronizers +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}] + + +## Sample constraint for GT location +#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i] +#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}] + +set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}] +set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}] + +set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk] + + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}] +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}] +################################################################### + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}] +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}] +################################################################### + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..7c1d09fe6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output dclk +); + + wire dclk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Dividing independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + |