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Diffstat (limited to 'fpga/usrp3/top/e31x/sim/dram_test/Makefile')
| -rw-r--r-- | fpga/usrp3/top/e31x/sim/dram_test/Makefile | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/fpga/usrp3/top/e31x/sim/dram_test/Makefile b/fpga/usrp3/top/e31x/sim/dram_test/Makefile new file mode 100644 index 000000000..164f956f3 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/dram_test/Makefile @@ -0,0 +1,65 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (<device>/<package>/<speedgrade>) +ARCH = zynq +PART_ID= xc7z020/clg484/-1 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/mig_7series_0/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_MIG_7SERIES_0_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_test_tb + +SIM_SRCS = \ +$(abspath dram_test_tb.sv) \ +$(IP_MIG_7SERIES_0_SIM_OUTS) \ +$(IP_MIG_7SERIES_TG_SRCS) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |