diff options
Diffstat (limited to 'fpga/usrp3/top/b200/sim/sim_b200_io')
5 files changed, 225 insertions, 0 deletions
diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg new file mode 100644 index 000000000..4ecabdecf --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg @@ -0,0 +1,112 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="./isim.wdb" id="1" type="auto"> + <top_modules> + <top_module name="b200_io_tb" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="4" /> + <wvobject fp_name="group18" type="group"> + <obj_property name="label">Test Bench</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/tb_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">tb_clk</obj_property> + <obj_property name="ObjectShortName">tb_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">reset</obj_property> + <obj_property name="ObjectShortName">reset</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/mimo" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">mimo</obj_property> + <obj_property name="ObjectShortName">mimo</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group33" type="group"> + <obj_property name="label">RX</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/dut/rx_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rx_clk</obj_property> + <obj_property name="ObjectShortName">rx_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_frame" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rx_frame</obj_property> + <obj_property name="ObjectShortName">rx_frame</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_data" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">rx_data[11:0]</obj_property> + <obj_property name="ObjectShortName">rx_data[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group32" type="group"> + <obj_property name="label">TX</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/dut/tx_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">tx_clk</obj_property> + <obj_property name="ObjectShortName">tx_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_frame" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">tx_frame</obj_property> + <obj_property name="ObjectShortName">tx_frame</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_data" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">tx_data[11:0]</obj_property> + <obj_property name="ObjectShortName">tx_data[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group13" type="group"> + <obj_property name="label">Internal</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/dut/radio_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">radio_clk</obj_property> + <obj_property name="ObjectShortName">radio_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_i0" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">rx_i0[11:0]</obj_property> + <obj_property name="ObjectShortName">rx_i0[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_q0" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">rx_q0[11:0]</obj_property> + <obj_property name="ObjectShortName">rx_q0[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_i1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">rx_i1[11:0]</obj_property> + <obj_property name="ObjectShortName">rx_i1[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_q1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">rx_q1[11:0]</obj_property> + <obj_property name="ObjectShortName">rx_q1[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_i0" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">tx_i0[11:0]</obj_property> + <obj_property name="ObjectShortName">tx_i0[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_q0" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">tx_q0[11:0]</obj_property> + <obj_property name="ObjectShortName">tx_q0[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_i1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">tx_i1[11:0]</obj_property> + <obj_property name="ObjectShortName">tx_i1[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_q1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">tx_q1[11:0]</obj_property> + <obj_property name="ObjectShortName">tx_q1[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + </wvobject> +</wave_config> diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v new file mode 100644 index 000000000..04e9079e1 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v @@ -0,0 +1,14 @@ + + initial + begin + reset <= 1; + mimo <= 0; + repeat(10) @(posedge rx_clk); + reset <= 0; + + repeat(10) @(posedge rx_clk); + + mimo_burst(20); + repeat(10) @(posedge rx_clk); + $finish; + end diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim new file mode 100755 index 000000000..dc0ec02b7 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +# usrp3/top/b200/sim/sim_b200_io/siso +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../../../lib/axi \ + --sourcelibdir ../../../../../lib/fifo \ + --sourcelibdir ../../../../../lib/control \ + --sourcelibdir ../../../coregen \ + --sourcelibdir ../../../ \ + --sourcelibdir ../../../../../lib/timing \ + --sourcelibdir ../../../../../lib/vita \ + --sourcelibdir ../../../../../lib/packet_proc \ + --sourcelibdir ../../../../../lib/dsp \ + --sourcelibdir ../../../../../lib/wishbone \ + --sourcelibdir ../../../../../lib/gpif2 \ + --sourcelibdir ../../../../../lib/io \ + ../../b200_io_tb.v + +fuse work.b200_io_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_io_tb.exe + +# run the simulation scrip +./b200_io_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v new file mode 100644 index 000000000..ad2e7fc57 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v @@ -0,0 +1,13 @@ + + initial + begin + reset <= 1; + mimo <= 0; + repeat(10) @(posedge rx_clk); + reset <= 0; + repeat(10) @(posedge rx_clk); + + siso_burst(20); + repeat(10) @(posedge rx_clk); + $finish; + end diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg new file mode 100644 index 000000000..7ef57498f --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg @@ -0,0 +1,64 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="./isim.wdb" id="1" type="auto"> + <top_modules> + <top_module name="b200_io_tb" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="3" /> + <wvobject fp_name="group18" type="group"> + <obj_property name="label">Test Bench</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/tb_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">tb_clk</obj_property> + <obj_property name="ObjectShortName">tb_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/reset" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">reset</obj_property> + <obj_property name="ObjectShortName">reset</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/mimo" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">mimo</obj_property> + <obj_property name="ObjectShortName">mimo</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group33" type="group"> + <obj_property name="label">RX</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/dut/rx_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rx_clk</obj_property> + <obj_property name="ObjectShortName">rx_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_frame" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rx_frame</obj_property> + <obj_property name="ObjectShortName">rx_frame</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/rx_data" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">rx_data[11:0]</obj_property> + <obj_property name="ObjectShortName">rx_data[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + </wvobject> + <wvobject fp_name="group32" type="group"> + <obj_property name="label">TX</obj_property> + <obj_property name="DisplayName">label</obj_property> + <wvobject fp_name="/b200_io_tb/dut/tx_clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">tx_clk</obj_property> + <obj_property name="ObjectShortName">tx_clk</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_frame" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">tx_frame</obj_property> + <obj_property name="ObjectShortName">tx_frame</obj_property> + </wvobject> + <wvobject fp_name="/b200_io_tb/dut/tx_data" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">tx_data[11:0]</obj_property> + <obj_property name="ObjectShortName">tx_data[11:0]</obj_property> + <obj_property name="Radix">HEXRADIX</obj_property> + </wvobject> + </wvobject> +</wave_config> |