diff options
Diffstat (limited to 'fpga/usrp3/top/b200/radio_b200.v')
| -rw-r--r-- | fpga/usrp3/top/b200/radio_b200.v | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/fpga/usrp3/top/b200/radio_b200.v b/fpga/usrp3/top/b200/radio_b200.v index a0ea808a5..7771851a3 100644 --- a/fpga/usrp3/top/b200/radio_b200.v +++ b/fpga/usrp3/top/b200/radio_b200.v @@ -1,19 +1,7 @@ // // Copyright 2013 Ettus Research LLC // -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see <http://www.gnu.org/licenses/>. -// + // radio top level module for b200 // Contains all clock-rate DSP components, all radio and hardware controls and settings @@ -35,6 +23,7 @@ module radio_b200 output [63:0] debug ); + // /////////////////////////////////////////////////////////////////////////////// // FIFO Interfacing to the bus clk domain @@ -73,7 +62,11 @@ module radio_b200 wire [63:0] rmux_tdata_r; wire rmux_tlast_r, rmux_tvalid_r, rmux_tready_r; - + + wire [63:0] rx_tdata_int; + wire rx_tready_int, rx_tvalid_int; + wire rx_tlast_int; + axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo (.reset(bus_rst), .i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}), @@ -89,10 +82,17 @@ module radio_b200 .i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}), .o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata})); - axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo + axi_fifo_2clk #(.WIDTH(65), .SIZE(0)) rx_fifo (.reset(radio_rst), .i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}), - .o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata})); + .o_aclk(bus_clk), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int), .o_tdata({rx_tlast_int, rx_tdata_int})); + + axi_packet_gate #(.WIDTH(64), .SIZE(RADIO_FIFO_SIZE)) buffer_whole_pkt + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata(rx_tdata_int), .i_tlast(rx_tlast_int), .i_terror(1'b0), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int), + .o_tdata(rx_tdata), .o_tlast(rx_tlast), .o_tvalid(rx_tvalid), .o_tready(rx_tready) + ); // ///////////////////////////////////////////////////////////////////////////////////// // Setting bus and controls @@ -227,7 +227,7 @@ module radio_b200 wire [31:0] rx_sid; wire [11:0] rx_seqnum; wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i; - + new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), @@ -281,6 +281,11 @@ module radio_b200 .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(), .o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r)); + // DEBUG LOGIC - NOT FOR PRODUCTION + assign debug = 0; + + + endmodule // radio_b200 |