diff options
Diffstat (limited to 'fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1')
| -rw-r--r-- | fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf | 241 | ||||
| -rw-r--r-- | fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf | 44 |
2 files changed, 285 insertions, 0 deletions
diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf new file mode 100644 index 000000000..75ffef7f3 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf @@ -0,0 +1,241 @@ +## SPI Nets + +NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = "H20" ; +NET "fx3_miso" LOC = "G20" ; +NET "fx3_mosi" LOC = "AA20" ; +NET "fx3_sclk" LOC = "Y21" ; + +NET "pll_ce" LOC = "W11" ; +NET "pll_mosi" LOC = "AB11" ; +NET "pll_sclk" LOC = "Y12" ; + +NET "FPGA_RXD0" LOC = "AB8" ; +NET "FPGA_TXD0" LOC = "AB7" ; + +NET "SCL_FPGA" LOC = "P21" ; +NET "SDA_FPGA" LOC = "W22" ; + +## Catalina Controls + +NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<2>" LOC = "L3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<3>" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<4>" LOC = "M4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<6>" LOC = "L4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<8>" LOC = "M2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<11>" LOC = "G3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = "K5" ;# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = "K4" ;# | IOSTANDARD = LVCMOS18; + +NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug<0>" LOC = "C14" ; +NET "debug<1>" LOC = "F15" ; +NET "debug<2>" LOC = "A18" ; +NET "debug<3>" LOC = "A17" ; +NET "debug<4>" LOC = "E14" ; +NET "debug<5>" LOC = "G13" ; +NET "debug<6>" LOC = "D13" ; +NET "debug<7>" LOC = "F13" ; +NET "debug<8>" LOC = "D8" ; +NET "debug<9>" LOC = "A6" ; +NET "debug<10>" LOC = "D7" ; +NET "debug<11>" LOC = "A5" ; +NET "debug<12>" LOC = "B6" ; +NET "debug<13>" LOC = "A3" ; +NET "debug<14>" LOC = "A7" ; +NET "debug<15>" LOC = "A8" ; +NET "debug<16>" LOC = "B18" ; +NET "debug<17>" LOC = "C17" ; +NET "debug<18>" LOC = "H13" ; +NET "debug<19>" LOC = "D12" ; +NET "debug<20>" LOC = "H14" ; +NET "debug<21>" LOC = "C10" ; +NET "debug<22>" LOC = "D10" ; +NET "debug<23>" LOC = "C8" ; +NET "debug<24>" LOC = "D9" ; +NET "debug<25>" LOC = "C5" ; +NET "debug<26>" LOC = "A9" ; +NET "debug<27>" LOC = "B8" ; +NET "debug<28>" LOC = "A4" ; +NET "debug<29>" LOC = "C7" ; +NET "debug<30>" LOC = "C6" ; +NET "debug<31>" LOC = "D6" ; + +NET "debug_clk<0>" LOC = "A12" ; +NET "debug_clk<1>" LOC = "C12" ; + +## GPIF + +NET "IFCLK" LOC = "H21" ; +NET "FX3_EXTINT" LOC = "U20" ; + +NET "GPIF_CTL0" LOC = "V20" ; +NET "GPIF_CTL1" LOC = "T22" ; +NET "GPIF_CTL2" LOC = "R22" ; +NET "GPIF_CTL3" LOC = "U22" ; +NET "GPIF_CTL4" LOC = "P19" ; +NET "GPIF_CTL5" LOC = "N22" ; +NET "GPIF_CTL6" LOC = "T21" ; +NET "GPIF_CTL7" LOC = "V21" ; +NET "GPIF_CTL8" LOC = "K18" ; +NET "GPIF_CTL9" LOC = "R20" ; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = "P22" ; +NET "GPIF_CTL12" LOC = "M20" ; + +NET "GPIF_D<0>" LOC = "T17" ; +NET "GPIF_D<1>" LOC = "U14" ; +NET "GPIF_D<2>" LOC = "U13" ; +NET "GPIF_D<3>" LOC = "AA6" ; +NET "GPIF_D<4>" LOC = "AB6" ; +NET "GPIF_D<5>" LOC = "Y3" ; +NET "GPIF_D<6>" LOC = "AB3" ; +NET "GPIF_D<7>" LOC = "AA4" ; +NET "GPIF_D<8>" LOC = "AA2" ; +NET "GPIF_D<9>" LOC = "AB2" ; +NET "GPIF_D<10>" LOC = "AB19" ; +NET "GPIF_D<11>" LOC = "AA18" ; +NET "GPIF_D<12>" LOC = "AB18" ; +NET "GPIF_D<13>" LOC = "Y13" ; +NET "GPIF_D<14>" LOC = "AA12" ; +NET "GPIF_D<15>" LOC = "AB12" ; +NET "GPIF_D<16>" LOC = "N20" ; +NET "GPIF_D<17>" LOC = "L20" ; +NET "GPIF_D<18>" LOC = "N19" ; +NET "GPIF_D<19>" LOC = "M22" ; +NET "GPIF_D<20>" LOC = "L19" ; +NET "GPIF_D<21>" LOC = "M21" ; +NET "GPIF_D<22>" LOC = "M19" ; +NET "GPIF_D<23>" LOC = "K22" ; +NET "GPIF_D<24>" LOC = "J20" ; +NET "GPIF_D<25>" LOC = "L22" ; +NET "GPIF_D<26>" LOC = "K19" ; +NET "GPIF_D<27>" LOC = "H22" ; +NET "GPIF_D<28>" LOC = "J22" ; +NET "GPIF_D<29>" LOC = "K20" ; +NET "GPIF_D<30>" LOC = "G22" ; +NET "GPIF_D<31>" LOC = "F22" ; + +## GPS + +NET "gps_lock" LOC = "Y17" ; +NET "gps_out_enable" LOC = "V22" ; +NET "gps_ref_enable" LOC = "AB13" ; +NET "gps_rxd" LOC = "AB14" ; +NET "gps_txd" LOC = "W12" ; +NET "gps_txd_nmea" LOC = "AA14" ; + +## LEDS + +NET "LED_RX1" LOC = "C22" ; +NET "LED_RX2" LOC = "L15" ; +NET "LED_TXRX1_TX" LOC = "C20" ; +NET "LED_TXRX2_RX" LOC = "D21" ; +NET "LED_TXRX1_RX" LOC = "K16" ; +NET "LED_TXRX2_TX" LOC = "D22" ; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = "Y15" ; +NET "pll_lock" LOC = "AB10" ; +NET "AUX_PWR_ON" LOC = "AA21" ; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = "AB15" ; +NET "PPS_IN_EXT" LOC = "AB16" ; +NET "PPS_IN_INT" LOC = "AB21" ; +NET "pps_out" LOC = "AB17" ; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = "W4" ; +NET "SFDX1_TX" LOC = "T18" ; +NET "SFDX2_RX" LOC = "F18" ; +NET "SFDX2_TX" LOC = "H17" ; +NET "SRX1_RX" LOC = "Y7" ; +NET "SRX1_TX" LOC = "AA8" ; +NET "SRX2_RX" LOC = "J17" ; +NET "SRX2_TX" LOC = "F19" ; +NET "tx_bandsel_a" LOC = "N16" ; +NET "tx_bandsel_b" LOC = "M16" ; +NET "tx_enable1" LOC = "Y4" ; +NET "tx_enable2" LOC = "R19" ; +NET "rx_bandsel_a" LOC = "T20" ; +NET "rx_bandsel_b" LOC = "U19" ; +NET "rx_bandsel_c" LOC = "P20" ; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf new file mode 100644 index 000000000..82d68aceb --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf @@ -0,0 +1,44 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_*" IOB = TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D<*>" TNM = gpif_net_out; +INST "GPIF_D<*>" TNM = gpif_net_in; +INST "GPIF_CTL0" TNM = gpif_net_out; +INST "GPIF_CTL1" TNM = gpif_net_out; +INST "GPIF_CTL2" TNM = gpif_net_out; +INST "GPIF_CTL3" TNM = gpif_net_out; +INST "GPIF_CTL4" TNM = gpif_net_in; +INST "GPIF_CTL5" TNM = gpif_net_in; +INST "GPIF_CTL6" TNM = gpif_net_in; +INST "GPIF_CTL7" TNM = gpif_net_out; +INST "GPIF_CTL8" TNM = gpif_net_in; +INST "GPIF_CTL11" TNM = gpif_net_out; +INST "GPIF_CTL12" TNM = gpif_net_out; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; |