diff options
Diffstat (limited to 'fpga/usrp3/tools/make/viv_simulator.mak')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_simulator.mak | 99 |
1 files changed, 90 insertions, 9 deletions
diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index add3e651d..3ee4a727c 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -28,12 +28,62 @@ PART_NAME=$(subst /,,$(PART_ID)) # Usage: SETUP_AND_LAUNCH_SIMULATION # Args: $1 = Simulator Name # ------------------------------------------------------------------- + +# Resolve path +EXP_DESIGN_SRCS = $(call RESOLVE_PATHS,$(DESIGN_SRCS)) +EXP_SIM_SRCS = $(call RESOLVE_PATHS,$(SIM_SRCS)) +EXP_INC_SRCS = $(call RESOLVE_PATHS,$(INC_SRCS)) + +# (NOQ) No quotes! +NOQ_DESIGN_SRCS := $(subst $\",,$(EXP_DESIGN_SRCS)) +NOQ_SIM_SRCS := $(subst $\",,$(EXP_SIM_SRCS)) +NOQ_INC_SRCS := $(subst $\",,$(EXP_INC_SRCS)) + +# Separate out VHDL +NOQ_DESIGN_VHDL := $(filter %.vhd,$(NOQ_DESIGN_SRCS)) +NOQ_SIM_VHDL := $(filter %.vhd,$(NOQ_SIM_SRCS)) +NOQ_VHDL := $(NOQ_DESIGN_VHDL) $(NOQ_SIM_VHDL) + +# Separate out System Verilog +NOQ_DESIGN_SV := $(filter %.sv,$(NOQ_DESIGN_SRCS)) +NOQ_SIM_SV := $(filter %.sv,$(NOQ_SIM_SRCS)) +NOQ_SV := $(NOQ_DESIGN_SV) $(NOQ_SIM_SV) +# Fetch packages from include list to compile +NOQ_PKG_SV := $(filter %.sv,$(NOQ_INC_SRCS)) + +# Seperate out Verilog +NOQ_INC_DIRS := $(sort $(dir $(NOQ_INC_SRCS))) +NOQ_DESIGN_VERILOG := $(filter %.v,$(NOQ_DESIGN_SRCS)) +NOQ_SIM_VERILOG := $(filter %.v,$(NOQ_SIM_SRCS)) +NOQ_VERILOG := $(NOQ_DESIGN_VERILOG) $(NOQ_SIM_VERILOG) + +# Modelsim Load libraries +MODELSIM_LIBS += unisims_ver + +# Arguments for various simulators +MODELSIM_ARGS += -quiet +SVLOG_ARGS += -quiet +SVLOG_ARGS += +define+WORKING_DIR="\"${CURDIR}\"" +VLOG_ARGS += -quiet +VLOG_ARGS += +define+WORKING_DIR="\"${CURDIR}\"" +VHDL_ARGS += -quiet + +# Working directory for standalone ModelSim execution +MODELSIM_PROJ_DIR ?= modelsim_proj + +# Check if we want to load the ModelSim GUI +ifeq ($(GUI), 1) + MODELSIM_ARGS += -do "run -all" +else + MODELSIM_ARGS += -c -do "run -all; quit -f" +endif + SETUP_AND_LAUNCH_SIMULATION = \ @ \ export VIV_SIMULATOR=$1; \ - export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ - export VIV_SIM_SRCS=$(call RESOLVE_PATHS,$(SIM_SRCS)); \ - export VIV_INC_SRCS=$(call RESOLVE_PATHS,$(INC_SRCS)); \ + export VIV_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \ + export VIV_SIM_SRCS=$(EXP_SIM_SRCS); \ + export VIV_INC_SRCS=$(EXP_INC_SRCS); \ export VIV_SIM_TOP=$(SIM_TOP); \ export VIV_SYNTH_TOP="$(SYNTH_DUT)"; \ export VIV_PART_NAME=$(PART_NAME); \ @@ -61,20 +111,51 @@ xclean: @rm -f xvlog.pb @rm -f vivado_pid*.str -##vsim: Run the simulation using Modelsim +##vsim: Run the simulation using ModelSim (via vivado) vsim: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) $(call SETUP_AND_LAUNCH_SIMULATION,Modelsim) -##vlint: Run verilog compiler to lint files. -vlint: .check_tool - @vlog $(SIM_SRCS) +incdir+$(BASE_DIR)/../sim/axi +incdir+$(BASE_DIR)/../sim/general +incdir+$(BASE_DIR)/../sim/control +incdir+$(BASE_DIR)/../sim/rfnoc +incdir+$(BASE_DIR)/../lib/rfnoc +##modelsim: Run the simulation using Modelsim (natively) +modelsim: .check_tool vlint + cd $(MODELSIM_PROJ_DIR) && vsim $(MODELSIM_ARGS) $(foreach lib,$(MODELSIM_LIBS),-L $(lib)) $(SIM_TOP) -##vclean: Cleanup Modelsim intermediate files + +# NOTE: VHDL files require a correct compile order. This script compiles files +# in the order they are defined in $(DESIGN_SRC), then $SIM_SRC) + +##vlint: Run ModelSim compiler to lint files. +vlint: .check_tool $(COMPLIBDIR) $(DESIGN_SRCS) $(SIM_SRCS) $(INC_SRCS) + $(shell mkdir -p ./modelsim_proj) + $(file >modelsim_proj/svlogarglist.txt,/* Auto generated argument file for vlog -sv */) + $(file >>modelsim_proj/svlogarglist.txt,-sv) + $(foreach dir,$(NOQ_INC_DIRS), $(file >>modelsim_proj/svlogarglist.txt,+incdir+$(dir))) + $(foreach src,$(NOQ_PKG_SV), $(file >>modelsim_proj/svlogarglist.txt,$(src))) + $(foreach src,$(NOQ_SV), $(file >>modelsim_proj/svlogarglist.txt,$(src))) + $(file >modelsim_proj/vlogarglist.txt,/* Auto generated argument file for vlog */) + $(file >>modelsim_proj/vlogarglist.txt,-vlog01compat) + $(foreach dir,$(NOQ_INC_DIRS), $(file >>modelsim_proj/vlogarglist.txt,+incdir+$(dir))) + $(foreach src,$(NOQ_VERILOG), $(file >>modelsim_proj/vlogarglist.txt,$(src))) + $(file >modelsim_proj/vcomarglist.txt,/* Auto generated argument file for vcom */) + $(file >>modelsim_proj/vcomarglist.txt,-2008) + $(foreach src,$(NOQ_VHDL),$(file >>modelsim_proj/vcomarglist.txt,$(src))) +ifneq ($(strip $(NOQ_SV)),) + @echo "*** COMPILING SYSTEM VERILOG ***" + cd $(MODELSIM_PROJ_DIR) && vlog $(SVLOG_ARGS) -f svlogarglist.txt +endif +ifneq ($(strip $(NOQ_VERILOG)),) + @echo "*** COMPILING VERILOG ***" + cd $(MODELSIM_PROJ_DIR) && vlog $(VLOG_ARGS) -f vlogarglist.txt +endif +ifneq ($(strip $(NOQ_VHDL)),) + @echo "*** COMPILING VHDL ***" + cd $(MODELSIM_PROJ_DIR) && vcom $(VHDL_ARGS) -f vcomarglist.txt +endif + +##vclean: Cleanup ModelSim intermediate files vclean: @rm -f modelsim*.log @rm -rf modelsim_proj @rm -f vivado_pid*.str - @rm -rf work # Use clean with :: to support allow "make clean" to work with multiple makefiles clean:: xclean vclean |