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-rw-r--r--fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore4
-rwxr-xr-xfpga/usrp3/sim/duc_chain_x300/dctest/run_isim17
-rwxr-xr-xfpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl9
3 files changed, 0 insertions, 30 deletions
diff --git a/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore b/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore
deleted file mode 100644
index 7826d75e2..000000000
--- a/fpga/usrp3/sim/duc_chain_x300/dctest/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-fuse*
-isim*
-*.exe
-*.wcfg
diff --git a/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim b/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim
deleted file mode 100755
index 0672e32a6..000000000
--- a/fpga/usrp3/sim/duc_chain_x300/dctest/run_isim
+++ /dev/null
@@ -1,17 +0,0 @@
-rm -rf fuse* *.exe isim
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work --sourcelibext .v \
- --sourcelibdir ../../../lib/dsp \
- --sourcelibdir ../../../lib/control \
- --sourcelibdir ../../../top/x300/coregen_dsp \
- --sourcelibdir ${XILINX}/verilog/src/unimacro \
- ../../../lib/dsp/duc_chain_x300_tb.v
-
-
-
-fuse work.duc_chain_x300_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o duc_chain_x300_tb.exe
-
-# run the simulation scrip
-./duc_chain_x300_tb.exe -tclbatch simcmds.tcl # -gui
-
-
diff --git a/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl b/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl
deleted file mode 100755
index 3dcfd3eaf..000000000
--- a/fpga/usrp3/sim/duc_chain_x300/dctest/simcmds.tcl
+++ /dev/null
@@ -1,9 +0,0 @@
-# file: simcmds.tcl
-
-# create the simulation script
-#vcd dumpfile isim.vcd
-#vcd dumpvars -m /bus_clk_gen_tb -l 0
-#wave add /
-run 1 s
-quit
-