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-rw-r--r--fpga/usrp3/lib/timing/pps.v22
1 files changed, 0 insertions, 22 deletions
diff --git a/fpga/usrp3/lib/timing/pps.v b/fpga/usrp3/lib/timing/pps.v
deleted file mode 100644
index 49d3641b7..000000000
--- a/fpga/usrp3/lib/timing/pps.v
+++ /dev/null
@@ -1,22 +0,0 @@
-//
-// Copyright 2014 Ettus Research LLC
-//
-
-module pps_generator
- #(parameter CLK_FREQ=0, DUTY=25)
- (input clk, input reset, output pps);
-
- reg[31:0] count;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 32'b1;
- end else if (count >= CLK_FREQ) begin
- count <= 32'b1;
- end else begin
- count <= count + 1'b1;
- end
- end
-
- assign pps = (count < CLK_FREQ * DUTY / 100);
-endmodule //pps_generator