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-rw-r--r--fpga/usrp3/lib/sim/tx/.gitignore5
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim40
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog16
-rw-r--r--fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v20
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim40
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog16
-rw-r--r--fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v20
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim40
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog16
-rw-r--r--fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v25
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim40
-rwxr-xr-xfpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog16
-rw-r--r--fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v24
13 files changed, 318 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/tx/.gitignore b/fpga/usrp3/lib/sim/tx/.gitignore
new file mode 100644
index 000000000..257fc3311
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/.gitignore
@@ -0,0 +1,5 @@
+*.log
+*.exe
+*.vcd
+isim*
+fuse* \ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
new file mode 100755
index 000000000..8ecd3e31d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_isim
@@ -0,0 +1,40 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
+vlogcomp -work work ../../../dsp/duc_chain.v
+vlogcomp -work work ../../../dsp/hb_interp.v
+vlogcomp -work work ../../../dsp/small_hb_int.v
+vlogcomp -work work ../../../dsp/cic_interp.v
+vlogcomp -work work ../../../dsp/cic_int_shifter.v
+vlogcomp -work work ../../../dsp/cic_strober.v
+vlogcomp -work work ../../../dsp/cordic_stage.v
+vlogcomp -work work ../../../dsp/cordic_z24.v
+vlogcomp -work work ../../../dsp/clip.v
+vlogcomp -work work ../../../dsp/round.v
+vlogcomp -work work ../../../dsp/round_reg.v
+vlogcomp -work work ../../../dsp/sign_extend.v
+vlogcomp -work work ../../../dsp/add2_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round_reg.v
+vlogcomp -work work ../../../dsp/srl.v
+vlogcomp -work work ../../../dsp/acc.v
+vlogcomp -work work ../../../dsp/clip_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round.v
+vlogcomp -work work ../../../dsp/add2.v
+vlogcomp -work work ../../../vita/new_tx_control.v
+vlogcomp -work work ../../../vita/new_tx_deframer.v
+vlogcomp -work work ../../../vita/tx_responder.v
+vlogcomp -work work ../../../vita/context_packet_gen.v
+vlogcomp -work work ../../../vita/trigger_context_pkt.v
+vlogcomp -work work ../../../control/setting_reg.v
+vlogcomp -work work ../../../control/ram_2port.v
+vlogcomp -work work ../../../fifo/axi_fifo.v
+vlogcomp -work work ../../../fifo/axi_mux4.v
+vlogcomp -work work ../../../fifo/axi_fifo_short.v
+vlogcomp -work work ../../../timing/time_compare.v
+
+
+
+fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
+
+# run the simulation scrip
+#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
+./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
new file mode 100755
index 000000000..8ae57a610
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/run_iverilog
@@ -0,0 +1,16 @@
+iverilog -y . \
+-D SIM_SCRIPT=true \
+../../../vita/new_tx_tb.v \
+-y ../../../vita/ \
+-y ../../../fifo/ \
+-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
+-y ../../../control/ \
+-y ../../../timing/ \
+-y ../../../dsp/ \
+/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
+-y ../../../../../usrp2/models/ \
+-Wall \
+-o new_tx_tb.exe
+
+./new_tx_tb.exe
+
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
new file mode 100644
index 000000000..9ded9d35e
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_burst/simulation_script.v
@@ -0,0 +1,20 @@
+ initial
+ begin
+ tvalid <= 1'b0;
+ while(reset)
+ @(posedge clk);
+ write_setting_bus(SR_ERROR_POLICY,32'h4);
+ write_setting_bus(SR_PACKETS,32'h8000_0002);
+
+ write_setting_bus(SR_INTERP,32'h1);
+
+ // Burst of len 2
+ send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 8 triggers Intra burst seq_id error
+ send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 2
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+ end // initial begin
+ \ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
new file mode 100755
index 000000000..8ecd3e31d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_isim
@@ -0,0 +1,40 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
+vlogcomp -work work ../../../dsp/duc_chain.v
+vlogcomp -work work ../../../dsp/hb_interp.v
+vlogcomp -work work ../../../dsp/small_hb_int.v
+vlogcomp -work work ../../../dsp/cic_interp.v
+vlogcomp -work work ../../../dsp/cic_int_shifter.v
+vlogcomp -work work ../../../dsp/cic_strober.v
+vlogcomp -work work ../../../dsp/cordic_stage.v
+vlogcomp -work work ../../../dsp/cordic_z24.v
+vlogcomp -work work ../../../dsp/clip.v
+vlogcomp -work work ../../../dsp/round.v
+vlogcomp -work work ../../../dsp/round_reg.v
+vlogcomp -work work ../../../dsp/sign_extend.v
+vlogcomp -work work ../../../dsp/add2_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round_reg.v
+vlogcomp -work work ../../../dsp/srl.v
+vlogcomp -work work ../../../dsp/acc.v
+vlogcomp -work work ../../../dsp/clip_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round.v
+vlogcomp -work work ../../../dsp/add2.v
+vlogcomp -work work ../../../vita/new_tx_control.v
+vlogcomp -work work ../../../vita/new_tx_deframer.v
+vlogcomp -work work ../../../vita/tx_responder.v
+vlogcomp -work work ../../../vita/context_packet_gen.v
+vlogcomp -work work ../../../vita/trigger_context_pkt.v
+vlogcomp -work work ../../../control/setting_reg.v
+vlogcomp -work work ../../../control/ram_2port.v
+vlogcomp -work work ../../../fifo/axi_fifo.v
+vlogcomp -work work ../../../fifo/axi_mux4.v
+vlogcomp -work work ../../../fifo/axi_fifo_short.v
+vlogcomp -work work ../../../timing/time_compare.v
+
+
+
+fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
+
+# run the simulation scrip
+#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
+./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
new file mode 100755
index 000000000..8ae57a610
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/run_iverilog
@@ -0,0 +1,16 @@
+iverilog -y . \
+-D SIM_SCRIPT=true \
+../../../vita/new_tx_tb.v \
+-y ../../../vita/ \
+-y ../../../fifo/ \
+-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
+-y ../../../control/ \
+-y ../../../timing/ \
+-y ../../../dsp/ \
+/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
+-y ../../../../../usrp2/models/ \
+-Wall \
+-o new_tx_tb.exe
+
+./new_tx_tb.exe
+
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
new file mode 100644
index 000000000..5dc608bc2
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_mid_burst_policy_next_packet/simulation_script.v
@@ -0,0 +1,20 @@
+ initial
+ begin
+ tvalid <= 1'b0;
+ while(reset)
+ @(posedge clk);
+ write_setting_bus(SR_ERROR_POLICY,32'h2);
+ write_setting_bus(SR_PACKETS,32'h8000_0002);
+
+ write_setting_bus(SR_INTERP,32'h1);
+
+ // Burst of len 2
+ send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 8 triggers Intra burst seq_id error
+ send_burst_with_seqid_error(8/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 2
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h00b/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+ end // initial begin
+ \ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim
new file mode 100755
index 000000000..8ecd3e31d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_isim
@@ -0,0 +1,40 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
+vlogcomp -work work ../../../dsp/duc_chain.v
+vlogcomp -work work ../../../dsp/hb_interp.v
+vlogcomp -work work ../../../dsp/small_hb_int.v
+vlogcomp -work work ../../../dsp/cic_interp.v
+vlogcomp -work work ../../../dsp/cic_int_shifter.v
+vlogcomp -work work ../../../dsp/cic_strober.v
+vlogcomp -work work ../../../dsp/cordic_stage.v
+vlogcomp -work work ../../../dsp/cordic_z24.v
+vlogcomp -work work ../../../dsp/clip.v
+vlogcomp -work work ../../../dsp/round.v
+vlogcomp -work work ../../../dsp/round_reg.v
+vlogcomp -work work ../../../dsp/sign_extend.v
+vlogcomp -work work ../../../dsp/add2_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round_reg.v
+vlogcomp -work work ../../../dsp/srl.v
+vlogcomp -work work ../../../dsp/acc.v
+vlogcomp -work work ../../../dsp/clip_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round.v
+vlogcomp -work work ../../../dsp/add2.v
+vlogcomp -work work ../../../vita/new_tx_control.v
+vlogcomp -work work ../../../vita/new_tx_deframer.v
+vlogcomp -work work ../../../vita/tx_responder.v
+vlogcomp -work work ../../../vita/context_packet_gen.v
+vlogcomp -work work ../../../vita/trigger_context_pkt.v
+vlogcomp -work work ../../../control/setting_reg.v
+vlogcomp -work work ../../../control/ram_2port.v
+vlogcomp -work work ../../../fifo/axi_fifo.v
+vlogcomp -work work ../../../fifo/axi_mux4.v
+vlogcomp -work work ../../../fifo/axi_fifo_short.v
+vlogcomp -work work ../../../timing/time_compare.v
+
+
+
+fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
+
+# run the simulation scrip
+#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
+./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
new file mode 100755
index 000000000..8ae57a610
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/run_iverilog
@@ -0,0 +1,16 @@
+iverilog -y . \
+-D SIM_SCRIPT=true \
+../../../vita/new_tx_tb.v \
+-y ../../../vita/ \
+-y ../../../fifo/ \
+-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
+-y ../../../control/ \
+-y ../../../timing/ \
+-y ../../../dsp/ \
+/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
+-y ../../../../../usrp2/models/ \
+-Wall \
+-o new_tx_tb.exe
+
+./new_tx_tb.exe
+
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
new file mode 100644
index 000000000..368a817b6
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_burst/simulation_script.v
@@ -0,0 +1,25 @@
+ initial
+ begin
+ tvalid <= 1'b0;
+ while(reset)
+ @(posedge clk);
+ write_setting_bus(SR_ERROR_POLICY,32'h4);
+ write_setting_bus(SR_PACKETS,32'h8000_0002);
+
+ write_setting_bus(SR_INTERP,32'h1);
+
+ // Burst of len 2
+ send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 2
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Inter burst sequence error
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 2
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+
+ end // initial begin
+ \ No newline at end of file
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim
new file mode 100755
index 000000000..8ecd3e31d
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_isim
@@ -0,0 +1,40 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp --define SIM_SCRIPT=true --define ISIM=true -work work ../../../vita/new_tx_tb.v
+vlogcomp -work work ../../../dsp/duc_chain.v
+vlogcomp -work work ../../../dsp/hb_interp.v
+vlogcomp -work work ../../../dsp/small_hb_int.v
+vlogcomp -work work ../../../dsp/cic_interp.v
+vlogcomp -work work ../../../dsp/cic_int_shifter.v
+vlogcomp -work work ../../../dsp/cic_strober.v
+vlogcomp -work work ../../../dsp/cordic_stage.v
+vlogcomp -work work ../../../dsp/cordic_z24.v
+vlogcomp -work work ../../../dsp/clip.v
+vlogcomp -work work ../../../dsp/round.v
+vlogcomp -work work ../../../dsp/round_reg.v
+vlogcomp -work work ../../../dsp/sign_extend.v
+vlogcomp -work work ../../../dsp/add2_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round_reg.v
+vlogcomp -work work ../../../dsp/srl.v
+vlogcomp -work work ../../../dsp/acc.v
+vlogcomp -work work ../../../dsp/clip_reg.v
+vlogcomp -work work ../../../dsp/add2_and_round.v
+vlogcomp -work work ../../../dsp/add2.v
+vlogcomp -work work ../../../vita/new_tx_control.v
+vlogcomp -work work ../../../vita/new_tx_deframer.v
+vlogcomp -work work ../../../vita/tx_responder.v
+vlogcomp -work work ../../../vita/context_packet_gen.v
+vlogcomp -work work ../../../vita/trigger_context_pkt.v
+vlogcomp -work work ../../../control/setting_reg.v
+vlogcomp -work work ../../../control/ram_2port.v
+vlogcomp -work work ../../../fifo/axi_fifo.v
+vlogcomp -work work ../../../fifo/axi_mux4.v
+vlogcomp -work work ../../../fifo/axi_fifo_short.v
+vlogcomp -work work ../../../timing/time_compare.v
+
+
+
+fuse work.new_tx_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o new_tx_tb.exe
+
+# run the simulation scrip
+#./new_tx_tb.exe -gui #-tclbatch simcmds.tcl
+./new_tx_tb.exe
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
new file mode 100755
index 000000000..8ae57a610
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/run_iverilog
@@ -0,0 +1,16 @@
+iverilog -y . \
+-D SIM_SCRIPT=true \
+../../../vita/new_tx_tb.v \
+-y ../../../vita/ \
+-y ../../../fifo/ \
+-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
+-y ../../../control/ \
+-y ../../../timing/ \
+-y ../../../dsp/ \
+/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
+-y ../../../../../usrp2/models/ \
+-Wall \
+-o new_tx_tb.exe
+
+./new_tx_tb.exe
+
diff --git a/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
new file mode 100644
index 000000000..fddffb871
--- /dev/null
+++ b/fpga/usrp3/lib/sim/tx/test_seq_error_policy_next_packet/simulation_script.v
@@ -0,0 +1,24 @@
+ initial
+ begin
+ tvalid <= 1'b0;
+ while(reset)
+ @(posedge clk);
+ write_setting_bus(SR_ERROR_POLICY,32'h2);
+ write_setting_bus(SR_PACKETS,32'h8000_0002);
+
+ write_setting_bus(SR_INTERP,32'h1);
+
+ // Burst of len 2
+ send_burst(2/*count*/,5/*len*/,32'hA000_0000/*start*/,64'h100/*time*/,12'h000/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 2
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h200/*time*/,12'h002/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Inter burst sequence error
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h300/*time*/,12'h015/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ // Burst of 2
+ send_burst(2/*count*/,10/*len*/,32'hC000_0000/*start*/,64'h400/*time*/,12'h0017/*seqnum*/,1/*sendat*/, 32'hDEADBEEF/*sid*/);
+
+ end // initial begin
+ \ No newline at end of file
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-20 17:42:25 +0000