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-rw-r--r--fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv21
1 files changed, 11 insertions, 10 deletions
diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
index 38664c20f..f209820df 100644
--- a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
+++ b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
@@ -29,7 +29,17 @@ module chdr_dechunker_tb();
reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
reg [63:0] o_last_tdata = 0;
-
+ reg [63:0] i_tdata;
+ reg i_tlast;
+ reg i_tvalid;
+ wire i_tready;
+
+ wire [63:0] o_tdata;
+ wire o_tlast, o_tvalid, o_tready;
+
+ reg result;
+
+
always #10 clk = ~clk;
initial $dumpfile("chdr_dechunker_tb.vcd");
@@ -106,15 +116,6 @@ module chdr_dechunker_tb();
#100 reset = 0;
end
- reg [63:0] i_tdata;
- reg i_tlast;
- reg i_tvalid;
- wire i_tready;
-
- wire [63:0] o_tdata;
- wire o_tlast, o_tvalid, o_tready;
-
- reg result;
initial begin
quantum <= 8;
i_tvalid <= 0;