diff options
Diffstat (limited to 'fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile new file mode 100644 index 000000000..f73cbdae9 --- /dev/null +++ b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/Makefile @@ -0,0 +1,33 @@ +# +# Copyright 2016 Ettus Research +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../../../top) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = chdr_dechunker_tb + +# Add test bench, user design under test, and +# additional user created files +SIM_SRCS = $(abspath \ +chdr_dechunker_tb.sv \ +) + +MODELSIM_USER_DO = $(abspath wave.do) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |