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-rw-r--r--fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv6
1 files changed, 2 insertions, 4 deletions
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
index 53aae3719..e47145088 100644
--- a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
+++ b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
@@ -36,8 +36,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0000),
.RAMP_STOP(14'h3FFF),
- .RAMP_INCR(14'h0001),
- .NTH_CYCLE(1)
+ .RAMP_INCR(14'h0001)
) dut0 (
.clk(clk),
.rst(rst),
@@ -54,8 +53,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0100),
.RAMP_STOP(14'h0FFF),
- .RAMP_INCR(14'h0001),
- .NTH_CYCLE(1)
+ .RAMP_INCR(14'h0001)
) dut1 (
.clk(clk),
.rst(rst),