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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-03-19 19:55:53 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-03-23 08:23:51 -0500 |
| commit | 5c7237fb407cfccaee205980d97e40ce10768c2a (patch) | |
| tree | dbdba3dcefff2d3cdeab27fa371c203b3398aa81 /fpga/usrp3/lib/sim/io_cap_gen | |
| parent | b721621237c0cd4150e9310cf443d4fb3a735388 (diff) | |
| download | uhd-5c7237fb407cfccaee205980d97e40ce10768c2a.tar.gz uhd-5c7237fb407cfccaee205980d97e40ce10768c2a.tar.bz2 uhd-5c7237fb407cfccaee205980d97e40ce10768c2a.zip | |
fpga: Fix errors found by linting with vsim
Diffstat (limited to 'fpga/usrp3/lib/sim/io_cap_gen')
| -rw-r--r-- | fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv index 53aae3719..e47145088 100644 --- a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv +++ b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv @@ -36,8 +36,7 @@ module cap_pattern_verifier_tb(); .PATTERN("RAMP"), .RAMP_START(14'h0000), .RAMP_STOP(14'h3FFF), - .RAMP_INCR(14'h0001), - .NTH_CYCLE(1) + .RAMP_INCR(14'h0001) ) dut0 ( .clk(clk), .rst(rst), @@ -54,8 +53,7 @@ module cap_pattern_verifier_tb(); .PATTERN("RAMP"), .RAMP_START(14'h0100), .RAMP_STOP(14'h0FFF), - .RAMP_INCR(14'h0001), - .NTH_CYCLE(1) + .RAMP_INCR(14'h0001) ) dut1 ( .clk(clk), .rst(rst), |