diff options
Diffstat (limited to 'fpga/usrp3/lib/sim/io_cap_gen/catgen')
| -rwxr-xr-x | fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build | 21 | ||||
| -rw-r--r-- | fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v | 103 |
2 files changed, 124 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build new file mode 100755 index 000000000..072495479 --- /dev/null +++ b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.build @@ -0,0 +1,21 @@ + +#!/bin/sh + +rm -rf isim* +rm -rf catgen_tb +rm -rf fuse* +\ +# --sourcelibdir ../../models \ + +vlogcomp \ + --sourcelibext .v \ + --sourcelibdir ../../coregen \ + --sourcelibdir ../../control_lib \ + --sourcelibdir . \ + --sourcelibdir $XILINX/verilog/src \ + --sourcelibdir $XILINX/verilog/src/unisims \ + --work work \ + catgen_tb.v + + +fuse -o catgen_tb catgen_tb
\ No newline at end of file diff --git a/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v new file mode 100644 index 000000000..e55f2de32 --- /dev/null +++ b/fpga/usrp3/lib/sim/io_cap_gen/catgen/catgen_tb.v @@ -0,0 +1,103 @@ +// +// Copyright 2014 Ettus Research LLC +// Copyright 2018 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +`timescale 1ns/1ps + +module catgen_tb(); + + wire GSR, GTS; + glbl glbl( ); + + reg clk = 0; + reg reset = 1; + wire ddrclk; + + always #100 clk = ~clk; + + initial $dumpfile("catgen_tb.vcd"); + initial $dumpvars(0,catgen_tb); + + wire [11:0] pins; + wire frame; + + reg mimo; + reg [7:0] count; + reg tx_strobe; + + wire [11:0] i0 = {4'hA,count}; + wire [11:0] q0 = {4'hB,count}; + wire [11:0] i1 = {4'hC,count}; + wire [11:0] q1 = {4'hD,count}; + + initial + begin + #1000 reset = 0; + BURST(4); + BURST(5); + MIMO_BURST(4); + MIMO_BURST(5); + #2000; + $finish; + end + + task BURST; + input [7:0] len; + + begin + tx_strobe <= 0; + mimo <= 0; + count <= 0; + @(posedge clk); + @(posedge clk); + repeat(len) + begin + tx_strobe <= 1; + @(posedge clk); + count <= count + 1; + end + tx_strobe <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + endtask // BURST + + task MIMO_BURST; + input [7:0] len; + + begin + tx_strobe <= 0; + mimo <= 1; + count <= 0; + @(posedge clk); + @(posedge clk); + repeat(len) + begin + tx_strobe <= 1; + @(posedge clk); + tx_strobe <= 0; + @(posedge clk); + count <= count + 1; + end + tx_strobe <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + endtask // BURST + + catgen_ddr_cmos catgen + (.data_clk(ddrclk), + .reset(reset), + .mimo(mimo), + .tx_frame(frame), + .tx_d(pins), + .tx_clk(clk), + .tx_strobe(tx_strobe), + .i0(i0),.q0(q0), + .i1(i1),.q1(q1)); + +endmodule // hb_chain_tb |