diff options
Diffstat (limited to 'fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile b/fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile new file mode 100644 index 000000000..90733cb5d --- /dev/null +++ b/fpga/usrp3/lib/sim/dsp/variable_delay_line/Makefile @@ -0,0 +1,47 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../../../top) +# Include viv_sim_preamble after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/dsp/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(DSP_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = variable_delay_line_tb + +# Add test bench, user design under test, and +# additional user created files +SIM_SRCS = $(abspath \ +variable_delay_line_tb.sv \ +) + +# MODELSIM_USER_DO = $(abspath wave.do) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |