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Diffstat (limited to 'fpga/usrp3/lib/sim/axi_packet_gate/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/sim/axi_packet_gate/Makefile | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/axi_packet_gate/Makefile b/fpga/usrp3/lib/sim/axi_packet_gate/Makefile new file mode 100644 index 000000000..625a02877 --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_packet_gate/Makefile @@ -0,0 +1,46 @@ +# +# Copyright 2016 Ettus Research +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../../top) +# Include viv_sim_preamble after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/fifo/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(CONTROL_LIB_SRCS) \ +$(FIFO_SRCS) \ +$(LIB_DIR)/fifo/axi_packet_gate.v \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = axi_packet_gate_tb + +# Add test bench, user design under test, and +# additional user created files +SIM_SRCS = $(abspath \ +axi_packet_gate_tb.sv \ +) + +# MODELSIM_USER_DO = $(abspath wave.do) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |