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-rwxr-xr-xfpga/usrp3/lib/sim/axi_fifo/run_sim11
1 files changed, 0 insertions, 11 deletions
diff --git a/fpga/usrp3/lib/sim/axi_fifo/run_sim b/fpga/usrp3/lib/sim/axi_fifo/run_sim
deleted file mode 100755
index 89bf95f1e..000000000
--- a/fpga/usrp3/lib/sim/axi_fifo/run_sim
+++ /dev/null
@@ -1,11 +0,0 @@
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../fifo/axi_fifo_tb.v
-vlogcomp -work work ../../fifo/axi_fifo.v
-vlogcomp -work work ../../control/ram_2port.v
-
-
-
-fuse work.axi_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_fifo_tb.exe
-
-# run the simulation scrip
-./axi_fifo_tb.exe -gui #-tclbatch simcmds.tcl