diff options
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv index de54d5ee0..8151ed761 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv @@ -35,6 +35,7 @@ module rfnoc_block_duc_tb(); // Block configuration localparam int CHDR_W = 64; + localparam int SAMP_W = 32; localparam int THIS_PORTID = 'h123; localparam int MTU = 8; localparam int NUM_PORTS = 1; @@ -49,6 +50,7 @@ module rfnoc_block_duc_tb(); bit rfnoc_chdr_clk; bit rfnoc_ctrl_clk; + bit ce_clk; sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst()); sim_clock_gen #(CHDR_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst()); @@ -59,6 +61,8 @@ module rfnoc_block_duc_tb(); // Bus Functional Models //--------------------------------------------------------------------------- + typedef ChdrData #(CHDR_W, SAMP_W)::chdr_word_t chdr_word_t; + RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk); AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0); AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0); |