diff options
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc')
3 files changed, 311 insertions, 330 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v index 56a13ee0a..c4b362cd6 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v @@ -1,132 +1,115 @@ // -// Copyright 2019 Ettus Research, A National Instruments Company +// Copyright 2019 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // // Module: noc_shell_ddc // -// Description: A NoC Shell for RFNoC. This should eventually be replaced -// by an auto-generated NoC Shell. +// Description: // +// This is a tool-generated NoC-shell for the ddc block. +// See the RFNoC specification for more information about NoC shells. +// +// Parameters: +// +// THIS_PORTID : Control crossbar port to which this block is connected +// CHDR_W : AXIS-CHDR data bus width +// MTU : Maximum transmission unit (i.e., maximum packet size in +// + +`default_nettype none + module noc_shell_ddc #( - parameter [31:0] NOC_ID = 32'h0, - parameter [ 9:0] THIS_PORTID = 10'd0, - parameter CHDR_W = 64, - parameter [ 0:0] CTRLPORT_SLV_EN = 1, - parameter [ 0:0] CTRLPORT_MST_EN = 1, - parameter [ 5:0] CTRL_FIFO_SIZE = 6, - parameter [ 5:0] NUM_DATA_I = 1, - parameter [ 5:0] NUM_DATA_O = 1, - parameter ITEM_W = 32, - parameter NIPC = 2, - parameter PYLD_FIFO_SIZE = 10, - parameter MTU = 10 -)( - //--------------------------------------------------------------------------- + parameter [9:0] THIS_PORTID = 10'd0, + parameter CHDR_W = 64, + parameter [5:0] MTU = 10, + parameter NUM_PORTS = 1, + parameter NUM_HB = 3, + parameter CIC_MAX_DECIM = 255 +) ( + //--------------------- // Framework Interface - //--------------------------------------------------------------------------- + //--------------------- - // RFNoC Framework Clocks and Resets - input wire rfnoc_chdr_clk, - output wire rfnoc_chdr_rst, - input wire rfnoc_ctrl_clk, - output wire rfnoc_ctrl_rst, - // RFNoC Backend Interface - input wire [ 511:0] rfnoc_core_config, - output wire [ 511:0] rfnoc_core_status, - // CHDR Input Ports (from framework) - input wire [(CHDR_W*NUM_DATA_I)-1:0] s_rfnoc_chdr_tdata, - input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tlast, - input wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tvalid, - output wire [ NUM_DATA_I-1:0] s_rfnoc_chdr_tready, - // CHDR Output Ports (to framework) - output wire [(CHDR_W*NUM_DATA_O)-1:0] m_rfnoc_chdr_tdata, - output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tlast, - output wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tvalid, - input wire [ NUM_DATA_O-1:0] m_rfnoc_chdr_tready, - // AXIS-Ctrl Input Port (from framework) - input wire [ 31:0] s_rfnoc_ctrl_tdata, - input wire s_rfnoc_ctrl_tlast, - input wire s_rfnoc_ctrl_tvalid, - output wire s_rfnoc_ctrl_tready, - // AXIS-Ctrl Output Port (to framework) - output wire [ 31:0] m_rfnoc_ctrl_tdata, - output wire m_rfnoc_ctrl_tlast, - output wire m_rfnoc_ctrl_tvalid, - input wire m_rfnoc_ctrl_tready, + // RFNoC Framework Clocks + input wire rfnoc_chdr_clk, + input wire rfnoc_ctrl_clk, + input wire ce_clk, - //--------------------------------------------------------------------------- - // Client Control Port Interface - //--------------------------------------------------------------------------- + // NoC Shell Generated Resets + output wire rfnoc_chdr_rst, + output wire rfnoc_ctrl_rst, + output wire ce_rst, - // Clock - input wire ctrlport_clk, - input wire ctrlport_rst, - // Master - output wire m_ctrlport_req_wr, - output wire m_ctrlport_req_rd, - output wire [19:0] m_ctrlport_req_addr, - output wire [31:0] m_ctrlport_req_data, - output wire [ 3:0] m_ctrlport_req_byte_en, - output wire m_ctrlport_req_has_time, - output wire [63:0] m_ctrlport_req_time, - input wire m_ctrlport_resp_ack, - input wire [ 1:0] m_ctrlport_resp_status, - input wire [31:0] m_ctrlport_resp_data, - // Slave - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [ 9:0] s_ctrlport_req_portid, - input wire [15:0] s_ctrlport_req_rem_epid, - input wire [ 9:0] s_ctrlport_req_rem_portid, - input wire [31:0] s_ctrlport_req_data, - input wire [ 3:0] s_ctrlport_req_byte_en, - input wire s_ctrlport_req_has_time, - input wire [63:0] s_ctrlport_req_time, - output wire s_ctrlport_resp_ack, - output wire [ 1:0] s_ctrlport_resp_status, - output wire [31:0] s_ctrlport_resp_data, + // RFNoC Backend Interface + input wire [511:0] rfnoc_core_config, + output wire [511:0] rfnoc_core_status, - //--------------------------------------------------------------------------- - // Client Data Interface - //--------------------------------------------------------------------------- + // AXIS-CHDR Input Ports (from framework) + input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata, + input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast, + input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid, + output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready, + // AXIS-CHDR Output Ports (to framework) + output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata, + output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast, + output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid, + input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready, - // Clock - input wire axis_data_clk, - input wire axis_data_rst, + // AXIS-Ctrl Control Input Port (from framework) + input wire [31:0] s_rfnoc_ctrl_tdata, + input wire s_rfnoc_ctrl_tlast, + input wire s_rfnoc_ctrl_tvalid, + output wire s_rfnoc_ctrl_tready, + // AXIS-Ctrl Control Output Port (to framework) + output wire [31:0] m_rfnoc_ctrl_tdata, + output wire m_rfnoc_ctrl_tlast, + output wire m_rfnoc_ctrl_tvalid, + input wire m_rfnoc_ctrl_tready, - // Output data stream (to user logic) - output wire [(NUM_DATA_I*ITEM_W*NIPC)-1:0] m_axis_tdata, - output wire [ (NUM_DATA_I*NIPC)-1:0] m_axis_tkeep, - output wire [ NUM_DATA_I-1:0] m_axis_tlast, - output wire [ NUM_DATA_I-1:0] m_axis_tvalid, - input wire [ NUM_DATA_I-1:0] m_axis_tready, - // Sideband information - output wire [ (NUM_DATA_I*64)-1:0] m_axis_ttimestamp, - output wire [ NUM_DATA_I-1:0] m_axis_thas_time, - output wire [ (NUM_DATA_I*16)-1:0] m_axis_tlength, - output wire [ NUM_DATA_I-1:0] m_axis_teov, - output wire [ NUM_DATA_I-1:0] m_axis_teob, + //--------------------- + // Client Interface + //--------------------- - // Input data stream (from user logic) - input wire [(NUM_DATA_O*ITEM_W*NIPC)-1:0] s_axis_tdata, - input wire [ (NUM_DATA_O*NIPC)-1:0] s_axis_tkeep, - input wire [ NUM_DATA_O-1:0] s_axis_tlast, - input wire [ NUM_DATA_O-1:0] s_axis_tvalid, - output wire [ NUM_DATA_O-1:0] s_axis_tready, - // Sideband info (sampled on the first cycle of the packet) - input wire [ (NUM_DATA_O*64)-1:0] s_axis_ttimestamp, - input wire [ NUM_DATA_O-1:0] s_axis_thas_time, - input wire [ NUM_DATA_O-1:0] s_axis_teov, - input wire [ NUM_DATA_O-1:0] s_axis_teob + // CtrlPort Clock and Reset + output wire ctrlport_clk, + output wire ctrlport_rst, + // CtrlPort Master + output wire m_ctrlport_req_wr, + output wire m_ctrlport_req_rd, + output wire [19:0] m_ctrlport_req_addr, + output wire [31:0] m_ctrlport_req_data, + output wire m_ctrlport_req_has_time, + output wire [63:0] m_ctrlport_req_time, + input wire m_ctrlport_resp_ack, + input wire [31:0] m_ctrlport_resp_data, + + // AXI-Stream Data Clock and Reset + output wire axis_data_clk, + output wire axis_data_rst, + // Data Stream to User Logic: in + output wire [NUM_PORTS*32*1-1:0] m_in_axis_tdata, + output wire [NUM_PORTS*1-1:0] m_in_axis_tkeep, + output wire [NUM_PORTS-1:0] m_in_axis_tlast, + output wire [NUM_PORTS-1:0] m_in_axis_tvalid, + input wire [NUM_PORTS-1:0] m_in_axis_tready, + output wire [NUM_PORTS*64-1:0] m_in_axis_ttimestamp, + output wire [NUM_PORTS-1:0] m_in_axis_thas_time, + output wire [NUM_PORTS*16-1:0] m_in_axis_tlength, + output wire [NUM_PORTS-1:0] m_in_axis_teov, + output wire [NUM_PORTS-1:0] m_in_axis_teob, + // Data Stream to User Logic: out + input wire [NUM_PORTS*32*1-1:0] s_out_axis_tdata, + input wire [NUM_PORTS*1-1:0] s_out_axis_tkeep, + input wire [NUM_PORTS-1:0] s_out_axis_tlast, + input wire [NUM_PORTS-1:0] s_out_axis_tvalid, + output wire [NUM_PORTS-1:0] s_out_axis_tready, + input wire [NUM_PORTS*64-1:0] s_out_axis_ttimestamp, + input wire [NUM_PORTS-1:0] s_out_axis_thas_time, + input wire [NUM_PORTS-1:0] s_out_axis_teov, + input wire [NUM_PORTS-1:0] s_out_axis_teob ); - - localparam SNK_INFO_FIFO_SIZE = 4; - localparam SNK_PYLD_FIFO_SIZE = PYLD_FIFO_SIZE; - localparam SRC_INFO_FIFO_SIZE = 4; - localparam SRC_PYLD_FIFO_SIZE = (MTU > PYLD_FIFO_SIZE) ? MTU : PYLD_FIFO_SIZE; //--------------------------------------------------------------------------- // Backend Interface @@ -142,18 +125,18 @@ module noc_shell_ddc #( wire [63:0] data_o_flush_done; backend_iface #( - .NOC_ID (NOC_ID), - .NUM_DATA_I (NUM_DATA_I), - .NUM_DATA_O (NUM_DATA_O), - .CTRL_FIFOSIZE (CTRL_FIFO_SIZE), + .NOC_ID (32'hDDC00000), + .NUM_DATA_I (0+NUM_PORTS), + .NUM_DATA_O (0+NUM_PORTS), + .CTRL_FIFOSIZE ($clog2(64)), .MTU (MTU) ) backend_iface_i ( .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), .rfnoc_core_config (rfnoc_core_config), .rfnoc_core_status (rfnoc_core_status), - .rfnoc_chdr_rst (rfnoc_chdr_rst), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst), .data_i_flush_en (data_i_flush_en), .data_i_flush_timeout (data_i_flush_timeout), .data_i_flush_active (data_i_flush_active), @@ -165,51 +148,70 @@ module noc_shell_ddc #( ); //--------------------------------------------------------------------------- + // Reset Generation + //--------------------------------------------------------------------------- + + wire ce_rst_pulse; + + pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_ce ( + .clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (), + .clk_b(ce_clk), .pulse_b (ce_rst_pulse) + ); + + pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_ce ( + .clk(ce_clk), .rst(1'b0), + .pulse_in(ce_rst_pulse), .pulse_out(ce_rst) + ); + + //--------------------------------------------------------------------------- // Control Path //--------------------------------------------------------------------------- + assign ctrlport_clk = ce_clk; + assign ctrlport_rst = ce_rst; + ctrlport_endpoint #( - .THIS_PORTID (THIS_PORTID ), - .SYNC_CLKS (0 ), - .AXIS_CTRL_MST_EN (CTRLPORT_SLV_EN), - .AXIS_CTRL_SLV_EN (CTRLPORT_MST_EN), - .SLAVE_FIFO_SIZE (CTRL_FIFO_SIZE ) - ) ctrlport_ep_i ( - .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), - .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), - .ctrlport_clk (ctrlport_clk ), - .ctrlport_rst (ctrlport_rst ), - .s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata ), - .s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast ), - .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid ), - .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready ), - .m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata ), - .m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast ), - .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid ), - .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready ), - .m_ctrlport_req_wr (m_ctrlport_req_wr ), - .m_ctrlport_req_rd (m_ctrlport_req_rd ), - .m_ctrlport_req_addr (m_ctrlport_req_addr ), - .m_ctrlport_req_data (m_ctrlport_req_data ), - .m_ctrlport_req_byte_en (m_ctrlport_req_byte_en ), - .m_ctrlport_req_has_time (m_ctrlport_req_has_time ), - .m_ctrlport_req_time (m_ctrlport_req_time ), - .m_ctrlport_resp_ack (m_ctrlport_resp_ack ), - .m_ctrlport_resp_status (m_ctrlport_resp_status ), - .m_ctrlport_resp_data (m_ctrlport_resp_data ), - .s_ctrlport_req_wr (s_ctrlport_req_wr ), - .s_ctrlport_req_rd (s_ctrlport_req_rd ), - .s_ctrlport_req_addr (s_ctrlport_req_addr ), - .s_ctrlport_req_portid (s_ctrlport_req_portid ), - .s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid ), - .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid), - .s_ctrlport_req_data (s_ctrlport_req_data ), - .s_ctrlport_req_byte_en (s_ctrlport_req_byte_en ), - .s_ctrlport_req_has_time (s_ctrlport_req_has_time ), - .s_ctrlport_req_time (s_ctrlport_req_time ), - .s_ctrlport_resp_ack (s_ctrlport_resp_ack ), - .s_ctrlport_resp_status (s_ctrlport_resp_status ), - .s_ctrlport_resp_data (s_ctrlport_resp_data ) + .THIS_PORTID (THIS_PORTID), + .SYNC_CLKS (0), + .AXIS_CTRL_MST_EN (0), + .AXIS_CTRL_SLV_EN (1), + .SLAVE_FIFO_SIZE ($clog2(64)) + ) ctrlport_endpoint_i ( + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .ctrlport_clk (ctrlport_clk), + .ctrlport_rst (ctrlport_rst), + .s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready), + .m_ctrlport_req_wr (m_ctrlport_req_wr), + .m_ctrlport_req_rd (m_ctrlport_req_rd), + .m_ctrlport_req_addr (m_ctrlport_req_addr), + .m_ctrlport_req_data (m_ctrlport_req_data), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (m_ctrlport_req_has_time), + .m_ctrlport_req_time (m_ctrlport_req_time), + .m_ctrlport_resp_ack (m_ctrlport_resp_ack), + .m_ctrlport_resp_status (2'b0), + .m_ctrlport_resp_data (m_ctrlport_resp_data), + .s_ctrlport_req_wr (1'b0), + .s_ctrlport_req_rd (1'b0), + .s_ctrlport_req_addr (20'b0), + .s_ctrlport_req_portid (10'b0), + .s_ctrlport_req_rem_epid (16'b0), + .s_ctrlport_req_rem_portid (10'b0), + .s_ctrlport_req_data (32'b0), + .s_ctrlport_req_byte_en (4'hF), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), + .s_ctrlport_resp_ack (), + .s_ctrlport_resp_status (), + .s_ctrlport_resp_data () ); //--------------------------------------------------------------------------- @@ -217,75 +219,87 @@ module noc_shell_ddc #( //--------------------------------------------------------------------------- genvar i; - generate - for (i = 0; i < NUM_DATA_I; i = i + 1) begin: chdr_to_data - chdr_to_axis_data #( - .CHDR_W (CHDR_W), - .ITEM_W (ITEM_W), - .NIPC (NIPC), - .SYNC_CLKS (0), - .INFO_FIFO_SIZE (SNK_INFO_FIFO_SIZE), - .PYLD_FIFO_SIZE (SNK_PYLD_FIFO_SIZE) - ) chdr_to_axis_data_i ( - .axis_chdr_clk (rfnoc_chdr_clk), - .axis_chdr_rst (rfnoc_chdr_rst), - .axis_data_clk (axis_data_clk), - .axis_data_rst (axis_data_rst), - .s_axis_chdr_tdata (s_rfnoc_chdr_tdata [(i*CHDR_W)+:CHDR_W]), - .s_axis_chdr_tlast (s_rfnoc_chdr_tlast [i]), - .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid [i]), - .s_axis_chdr_tready (s_rfnoc_chdr_tready [i]), - .m_axis_tdata (m_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]), - .m_axis_tkeep (m_axis_tkeep [i*NIPC +: NIPC]), - .m_axis_tlast (m_axis_tlast [i]), - .m_axis_tvalid (m_axis_tvalid [i]), - .m_axis_tready (m_axis_tready [i]), - .m_axis_ttimestamp (m_axis_ttimestamp [i*64 +: 64]), - .m_axis_thas_time (m_axis_thas_time [i]), - .m_axis_tlength (m_axis_tlength [i*16 +: 16]), - .m_axis_teov (m_axis_teov [i]), - .m_axis_teob (m_axis_teob [i]), - .flush_en (data_i_flush_en), - .flush_timeout (data_i_flush_timeout), - .flush_active (data_i_flush_active [i]), - .flush_done (data_i_flush_done [i]) - ); - end + assign axis_data_clk = ce_clk; + assign axis_data_rst = ce_rst; + + //--------------------- + // Input Data Paths + //--------------------- + + for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in + chdr_to_axis_data #( + .CHDR_W (CHDR_W), + .ITEM_W (32), + .NIPC (1), + .SYNC_CLKS (0), + .INFO_FIFO_SIZE ($clog2(32)), + .PYLD_FIFO_SIZE ($clog2(MTU)) + ) chdr_to_axis_data_in_in ( + .axis_chdr_clk (rfnoc_chdr_clk), + .axis_chdr_rst (rfnoc_chdr_rst), + .axis_data_clk (axis_data_clk), + .axis_data_rst (axis_data_rst), + .s_axis_chdr_tdata (s_rfnoc_chdr_tdata[((0+i)*CHDR_W)+:CHDR_W]), + .s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]), + .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]), + .s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]), + .m_axis_tdata (m_in_axis_tdata[(32*1)*i+:(32*1)]), + .m_axis_tkeep (m_in_axis_tkeep[1*i+:1]), + .m_axis_tlast (m_in_axis_tlast[i]), + .m_axis_tvalid (m_in_axis_tvalid[i]), + .m_axis_tready (m_in_axis_tready[i]), + .m_axis_ttimestamp (m_in_axis_ttimestamp[64*i+:64]), + .m_axis_thas_time (m_in_axis_thas_time[i]), + .m_axis_tlength (m_in_axis_tlength[i*16+:16]), + .m_axis_teov (m_in_axis_teov[i]), + .m_axis_teob (m_in_axis_teob[i]), + .flush_en (data_i_flush_en), + .flush_timeout (data_i_flush_timeout), + .flush_active (data_i_flush_active[0+i]), + .flush_done (data_i_flush_done[0+i]) + ); + end + + //--------------------- + // Output Data Paths + //--------------------- + + for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out + axis_data_to_chdr #( + .CHDR_W (CHDR_W), + .ITEM_W (32), + .NIPC (1), + .SYNC_CLKS (0), + .INFO_FIFO_SIZE ($clog2(32)), + .PYLD_FIFO_SIZE ($clog2(MTU)), + .MTU (MTU) + ) axis_data_to_chdr_out_out ( + .axis_chdr_clk (rfnoc_chdr_clk), + .axis_chdr_rst (rfnoc_chdr_rst), + .axis_data_clk (axis_data_clk), + .axis_data_rst (axis_data_rst), + .m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]), + .m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]), + .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]), + .m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]), + .s_axis_tdata (s_out_axis_tdata[(32*1)*i+:(32*1)]), + .s_axis_tkeep (s_out_axis_tkeep[1*i+:1]), + .s_axis_tlast (s_out_axis_tlast[i]), + .s_axis_tvalid (s_out_axis_tvalid[i]), + .s_axis_tready (s_out_axis_tready[i]), + .s_axis_ttimestamp (s_out_axis_ttimestamp[64*i+:64]), + .s_axis_thas_time (s_out_axis_thas_time[i]), + .s_axis_teov (s_out_axis_teov[i]), + .s_axis_teob (s_out_axis_teob[i]), + .flush_en (data_o_flush_en), + .flush_timeout (data_o_flush_timeout), + .flush_active (data_o_flush_active[0+i]), + .flush_done (data_o_flush_done[0+i]) + ); + end + +endmodule // noc_shell_ddc - for (i = 0; i < NUM_DATA_O; i = i + 1) begin: data_to_chdr - axis_data_to_chdr #( - .CHDR_W (CHDR_W), - .ITEM_W (ITEM_W), - .NIPC (NIPC), - .SYNC_CLKS (0), - .INFO_FIFO_SIZE (4), - .PYLD_FIFO_SIZE (SRC_INFO_FIFO_SIZE), - .MTU (SRC_PYLD_FIFO_SIZE) - ) axis_data_to_chdr_i ( - .axis_chdr_clk (rfnoc_chdr_clk), - .axis_chdr_rst (rfnoc_chdr_rst), - .axis_data_clk (axis_data_clk), - .axis_data_rst (axis_data_rst), - .m_axis_chdr_tdata (m_rfnoc_chdr_tdata [i*CHDR_W +: CHDR_W]), - .m_axis_chdr_tlast (m_rfnoc_chdr_tlast [i]), - .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid [i]), - .m_axis_chdr_tready (m_rfnoc_chdr_tready [i]), - .s_axis_tdata (s_axis_tdata [i*ITEM_W*NIPC +: ITEM_W*NIPC]), - .s_axis_tkeep (s_axis_tkeep [i*NIPC +: NIPC]), - .s_axis_tlast (s_axis_tlast [i]), - .s_axis_tvalid (s_axis_tvalid [i]), - .s_axis_tready (s_axis_tready [i]), - .s_axis_ttimestamp (s_axis_ttimestamp [i*64 +: 64]), - .s_axis_thas_time (s_axis_thas_time [i]), - .s_axis_teov (s_axis_teov [i]), - .s_axis_teob (s_axis_teob [i]), - .flush_en (data_o_flush_en), - .flush_timeout (data_o_flush_timeout), - .flush_active (data_o_flush_active [i]), - .flush_done (data_o_flush_done [i]) - ); - end - endgenerate -endmodule +`default_nettype wire diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v index 3162743b6..039541880 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc.v @@ -14,8 +14,6 @@ // NUM_PORTS : Number of DDCs to instantiate // MTU : Maximum transmission unit (i.e., maximum packet size) in // CHDR words is 2**MTU. -// CTRL_FIFO_SIZE : Size of the Control Port slave FIFO. This affects the -// number of outstanding commands that can be pending. // NUM_HB : Number of half-band decimation blocks to include (0-3) // CIC_MAX_DECIM : Maximum decimation to support in the CIC filter // @@ -25,7 +23,6 @@ module rfnoc_block_ddc #( parameter CHDR_W = 64, parameter NUM_PORTS = 2, parameter MTU = 10, - parameter CTRL_FIFO_SIZE = 6, parameter NUM_HB = 3, parameter CIC_MAX_DECIM = 255 ) ( @@ -75,8 +72,6 @@ module rfnoc_block_ddc #( localparam ITEM_W = 32; localparam NIPC = 1; - localparam NOC_ID = 'hDDC0_0000; - localparam COMPAT_MAJOR = 16'h0; localparam COMPAT_MINOR = 16'h0; @@ -88,8 +83,6 @@ module rfnoc_block_ddc #( // Signal Declarations //--------------------------------------------------------------------------- - wire rfnoc_chdr_rst; - wire ctrlport_req_wr; wire ctrlport_req_rd; wire [19:0] ctrlport_req_addr; @@ -118,103 +111,74 @@ module rfnoc_block_ddc #( wire [ NUM_PORTS*64-1:0] s_axis_data_ttimestamp; wire [ NUM_PORTS-1:0] s_axis_data_thas_time; - wire ddc_rst; - - // Cross the CHDR reset to the ce_clk domain - synchronizer ddc_rst_sync_i ( - .clk (ce_clk), - .rst (1'b0), - .in (rfnoc_chdr_rst), - .out (ddc_rst) - ); - //--------------------------------------------------------------------------- // NoC Shell //--------------------------------------------------------------------------- + wire ce_rst; + noc_shell_ddc #( - .NOC_ID (NOC_ID), - .THIS_PORTID (THIS_PORTID), - .CHDR_W (CHDR_W), - .CTRLPORT_SLV_EN (0), - .CTRLPORT_MST_EN (1), - .CTRL_FIFO_SIZE (CTRL_FIFO_SIZE), - .NUM_DATA_I (NUM_PORTS), - .NUM_DATA_O (NUM_PORTS), - .ITEM_W (ITEM_W), - .NIPC (NIPC), - .PYLD_FIFO_SIZE (MTU), - .MTU (MTU) + .THIS_PORTID (THIS_PORTID), + .CHDR_W (CHDR_W), + .MTU (MTU), + .NUM_PORTS (NUM_PORTS) ) noc_shell_ddc_i ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_chdr_rst (rfnoc_chdr_rst), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .rfnoc_ctrl_rst (), - .rfnoc_core_config (rfnoc_core_config), - .rfnoc_core_status (rfnoc_core_status), - .s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata), - .s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast), - .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid), - .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready), - .m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata), - .m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast), - .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid), - .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready), - .s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata), - .s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast), - .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid), - .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata), - .m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast), - .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid), - .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready), - .ctrlport_clk (ce_clk), - .ctrlport_rst (ddc_rst), - .m_ctrlport_req_wr (ctrlport_req_wr), - .m_ctrlport_req_rd (ctrlport_req_rd), - .m_ctrlport_req_addr (ctrlport_req_addr), - .m_ctrlport_req_data (ctrlport_req_data), - .m_ctrlport_req_byte_en (), - .m_ctrlport_req_has_time (ctrlport_req_has_time), - .m_ctrlport_req_time (ctrlport_req_time), - .m_ctrlport_resp_ack (ctrlport_resp_ack), - .m_ctrlport_resp_status (AXIS_CTRL_STS_OKAY), - .m_ctrlport_resp_data (ctrlport_resp_data), - .s_ctrlport_req_wr (1'b0), - .s_ctrlport_req_rd (1'b0), - .s_ctrlport_req_addr (20'b0), - .s_ctrlport_req_portid (10'b0), - .s_ctrlport_req_rem_epid (16'b0), - .s_ctrlport_req_rem_portid (10'b0), - .s_ctrlport_req_data (32'b0), - .s_ctrlport_req_byte_en (4'b0), - .s_ctrlport_req_has_time (1'b0), - .s_ctrlport_req_time (64'b0), - .s_ctrlport_resp_ack (), - .s_ctrlport_resp_status (), - .s_ctrlport_resp_data (), - .axis_data_clk (ce_clk), - .axis_data_rst (ddc_rst), - .m_axis_tdata (m_axis_data_tdata), - .m_axis_tkeep (), - .m_axis_tlast (m_axis_data_tlast), - .m_axis_tvalid (m_axis_data_tvalid), - .m_axis_tready (m_axis_data_tready), - .m_axis_ttimestamp (m_axis_data_ttimestamp), - .m_axis_thas_time (m_axis_data_thas_time), - .m_axis_tlength (m_axis_data_tlength), - .m_axis_teov (), - .m_axis_teob (m_axis_data_teob), - .s_axis_tdata (s_axis_data_tdata), - .s_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}), - .s_axis_tlast (s_axis_data_tlast), - .s_axis_tvalid (s_axis_data_tvalid), - .s_axis_tready (s_axis_data_tready), - .s_axis_ttimestamp (s_axis_data_ttimestamp), - .s_axis_thas_time (s_axis_data_thas_time), - .s_axis_teov ({NUM_PORTS{1'b0}}), - .s_axis_teob (s_axis_data_teob) + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ce_clk), + .rfnoc_chdr_rst (), + .rfnoc_ctrl_rst (), + .ce_rst (ce_rst), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status), + .s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata), + .s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast), + .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid), + .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready), + .m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata), + .m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast), + .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid), + .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready), + .s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready), + .ctrlport_clk (), + .ctrlport_rst (), + .m_ctrlport_req_wr (ctrlport_req_wr), + .m_ctrlport_req_rd (ctrlport_req_rd), + .m_ctrlport_req_addr (ctrlport_req_addr), + .m_ctrlport_req_data (ctrlport_req_data), + .m_ctrlport_req_has_time (ctrlport_req_has_time), + .m_ctrlport_req_time (ctrlport_req_time), + .m_ctrlport_resp_ack (ctrlport_resp_ack), + .m_ctrlport_resp_data (ctrlport_resp_data), + .axis_data_clk (), + .axis_data_rst (), + .m_in_axis_tdata (m_axis_data_tdata), + .m_in_axis_tkeep (), + .m_in_axis_tlast (m_axis_data_tlast), + .m_in_axis_tvalid (m_axis_data_tvalid), + .m_in_axis_tready (m_axis_data_tready), + .m_in_axis_ttimestamp (m_axis_data_ttimestamp), + .m_in_axis_thas_time (m_axis_data_thas_time), + .m_in_axis_tlength (m_axis_data_tlength), + .m_in_axis_teov (), + .m_in_axis_teob (m_axis_data_teob), + .s_out_axis_tdata (s_axis_data_tdata), + .s_out_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}), + .s_out_axis_tlast (s_axis_data_tlast), + .s_out_axis_tvalid (s_axis_data_tvalid), + .s_out_axis_tready (s_axis_data_tready), + .s_out_axis_ttimestamp (s_axis_data_ttimestamp), + .s_out_axis_thas_time (s_axis_data_thas_time), + .s_out_axis_teov ({NUM_PORTS{1'b0}}), + .s_out_axis_teob (s_axis_data_teob) ); @@ -240,7 +204,7 @@ module rfnoc_block_ddc #( .NUM_PORTS (NUM_PORTS) ) ctrlport_to_settings_bus_i ( .ctrlport_clk (ce_clk), - .ctrlport_rst (ddc_rst), + .ctrlport_rst (ce_rst), .s_ctrlport_req_wr (ctrlport_req_wr), .s_ctrlport_req_rd (ctrlport_req_rd), .s_ctrlport_req_addr (ctrlport_req_addr), @@ -256,7 +220,9 @@ module rfnoc_block_ddc #( .set_has_time (set_has_time), .rb_stb (rb_stb), .rb_addr (rb_addr), - .rb_data (rb_data)); + .rb_data (rb_data), + .timestamp (64'b0) + ); //--------------------------------------------------------------------------- @@ -333,7 +299,7 @@ module rfnoc_block_ddc #( .SR_TAG_ADDRS(SR_FREQ_ADDR)) axi_tag_time ( .clk(ce_clk), - .reset(ddc_rst), + .reset(ce_rst), .clear(clear_tx_seqnum[i]), .tick_rate(16'd1), .timed_cmd_fifo_full(timed_cmd_fifo_full), @@ -370,7 +336,7 @@ module rfnoc_block_ddc #( .SR_M_ADDR(SR_M_ADDR), .SR_CONFIG_ADDR(SR_CONFIG_ADDR)) axi_rate_change ( - .clk(ce_clk), .reset(ddc_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user), + .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user), .src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]), .set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data), .i_tdata({m_axis_tagged_tag,m_axis_tagged_tdata}), .i_tlast(m_axis_tagged_tlast), @@ -403,7 +369,7 @@ module rfnoc_block_ddc #( .NUM_HB(NUM_HB), .CIC_MAX_DECIM(CIC_MAX_DECIM)) ddc ( - .clk(ce_clk), .reset(ddc_rst), + .clk(ce_clk), .reset(ce_rst), .clear(clear_user | clear_tx_seqnum[i]), // Use AXI Rate Change's clear user to reset block to initial state after EOB .set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data), .timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data), diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv index 8b0790909..86f64ab4c 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv @@ -40,6 +40,7 @@ module rfnoc_block_ddc_tb(); localparam int NUM_PORTS = 1; localparam int NUM_HB = 3; localparam int CIC_MAX_DECIM = 255; + localparam int NOC_ID = 32'hDDC00000; //--------------------------------------------------------------------------- @@ -297,7 +298,7 @@ module rfnoc_block_ddc_tb(); //------------------------------------------------------------------------- test.start_test("Verify Block Info", 2us); - `ASSERT_ERROR(blk_ctrl.get_noc_id() == rfnoc_block_ddc_i.NOC_ID, "Incorrect NOC_ID Value"); + `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value"); `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS, "Incorrect NUM_DATA_I Value"); `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS, "Incorrect NUM_DATA_O Value"); `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value"); |