3 files changed, 65 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/hls/addsub_hls/Makefile.inc b/fpga/usrp3/lib/hls/addsub_hls/Makefile.inc
new file mode 100644
index 000000000..0e2f0737a
--- /dev/null
+++ b/fpga/usrp3/lib/hls/addsub_hls/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# Copyright 2015-2017 Ettus Research
+# Copyright 2016 Ettus Research, a National Instruments Company
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+# Add C/C++/tcl files relative to usrp3/lib/hls/<ip> directory
+HLS_IP_ADDSUB_HLS_SRCS = \
+addsub_hls.cpp \
+addsub_hls.tcl
+
+HLS_IP_ADDSUB_HLS_OUTS = $(addprefix $(IP_BUILD_DIR)/addsub_hls/, \
+solution/impl/verilog/addsub_hls.v \
+)
+
+# Sources in lib directory
+HLS_IP_ADDSUB_HLS_LIB_SRCS = $(addprefix $(HLS_IP_DIR)/addsub_hls/, $(HLS_IP_ADDSUB_HLS_SRCS))
+
+# Build with HLS
+$(HLS_IP_ADDSUB_HLS_OUTS) : $(HLS_IP_ADDSUB_HLS_LIB_SRCS)
+	$(call BUILD_VIVADO_HLS_IP,addsub_hls,$(PART_ID),$(HLS_IP_ADDSUB_HLS_LIB_SRCS),$(HLS_IP_DIR),$(IP_BUILD_DIR),)
diff --git a/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp
new file mode 100644
index 000000000..1cb27c119
--- /dev/null
+++ b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.cpp
@@ -0,0 +1,41 @@
+//
+// Copyright 2016 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+
+#include <complex>
+#include "ap_int.h"
+
+struct axis_cplx {
+    std::complex<short int> data;
+    ap_uint<1> last;
+};
+
+// AXI-Stream port type is compatible with pointer, reference, & array input / ouputs only
+// See UG902 Vivado High Level Synthesis guide (2014.4) pg 157 Figure 1-49
+void addsub_hls (axis_cplx &a, axis_cplx &b, axis_cplx &add, axis_cplx &sub) {
+
+    // Remove ap ctrl ports (ap_start, ap_ready, ap_idle, etc) since we only use the AXI-Stream ports
+    #pragma HLS INTERFACE ap_ctrl_none port=return
+    // Set ports as AXI-Stream
+    #pragma HLS INTERFACE axis port=sub
+    #pragma HLS INTERFACE axis port=add
+    #pragma HLS INTERFACE axis port=a
+    #pragma HLS INTERFACE axis port=b
+    // Need to pack our complex<short int> into a 32-bit word
+    // Otherwise, compiler complains that our AXI-Stream interfaces have two data fields (i.e. data.real, data.imag)
+    #pragma HLS DATA_PACK variable=sub.data
+    #pragma HLS DATA_PACK variable=add.data
+    #pragma HLS DATA_PACK variable=a.data
+    #pragma HLS DATA_PACK variable=b.data
+
+    // Complex add / subtract
+    add.data.real() = a.data.real() + b.data.real();
+    add.data.imag() = a.data.imag() + b.data.imag();
+    sub.data.real() = a.data.real() - b.data.real();
+    sub.data.imag() = a.data.imag() - b.data.imag();
+    // Pass through tlast
+    add.last = a.last;
+    sub.last = a.last;
+}
diff --git a/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl
new file mode 100644
index 000000000..a089fb628
--- /dev/null
+++ b/fpga/usrp3/lib/hls/addsub_hls/addsub_hls.tcl
@@ -0,0 +1,2 @@
+# Set target clock rate to 200 MHz
+create_clock -period 5 -name default