19 files changed, 149 insertions, 208 deletions

diff --git a/fpga/usrp3/lib/control/Makefile.srcs b/fpga/usrp3/lib/control/Makefile.srcs
index 9e44579ad..3576e0ee7 100644
--- a/fpga/usrp3/lib/control/Makefile.srcs
+++ b/fpga/usrp3/lib/control/Makefile.srcs
@@ -24,4 +24,5 @@ axi_test_vfifo.v \
 dram_2port.v \
 cvita_uart.v \
 serial_to_settings.v \
+filter_bad_sid.v \
 ))
diff --git a/fpga/usrp3/lib/control/arb_qualify_master.v b/fpga/usrp3/lib/control/arb_qualify_master.v
index e9c67b7ac..df17fac57 100644
--- a/fpga/usrp3/lib/control/arb_qualify_master.v
+++ b/fpga/usrp3/lib/control/arb_qualify_master.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //
 // This module forms the qualification engine for a single master as
diff --git a/fpga/usrp3/lib/control/axi_crossbar.v b/fpga/usrp3/lib/control/axi_crossbar.v
index c64931b6e..a408f69f0 100644
--- a/fpga/usrp3/lib/control/axi_crossbar.v
+++ b/fpga/usrp3/lib/control/axi_crossbar.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 `define LOG2(N) (\
                  N < 2 ? 0 : \
diff --git a/fpga/usrp3/lib/control/axi_crossbar_tb.v b/fpga/usrp3/lib/control/axi_crossbar_tb.v
index b14f859d4..1994cb352 100644
--- a/fpga/usrp3/lib/control/axi_crossbar_tb.v
+++ b/fpga/usrp3/lib/control/axi_crossbar_tb.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 `timescale  1 ps / 1 ps
 
 module axi_crossbar_tb;
diff --git a/fpga/usrp3/lib/control/axi_fifo_header.v b/fpga/usrp3/lib/control/axi_fifo_header.v
index 1a0d13cd0..ceac8e324 100644
--- a/fpga/usrp3/lib/control/axi_fifo_header.v
+++ b/fpga/usrp3/lib/control/axi_fifo_header.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //
 // This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
diff --git a/fpga/usrp3/lib/control/axi_forwarding_cam.v b/fpga/usrp3/lib/control/axi_forwarding_cam.v
index cb6e82684..2f28b5640 100644
--- a/fpga/usrp3/lib/control/axi_forwarding_cam.v
+++ b/fpga/usrp3/lib/control/axi_forwarding_cam.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //
 // This module implements a highly customized TCAM that enbales forwarding
diff --git a/fpga/usrp3/lib/control/axi_slave_mux.v b/fpga/usrp3/lib/control/axi_slave_mux.v
index 3f2424584..1a307aba5 100644
--- a/fpga/usrp3/lib/control/axi_slave_mux.v
+++ b/fpga/usrp3/lib/control/axi_slave_mux.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
    
 
diff --git a/fpga/usrp3/lib/control/cvita_uart.v b/fpga/usrp3/lib/control/cvita_uart.v
index e0d4697ce..cbb272fc2 100644
--- a/fpga/usrp3/lib/control/cvita_uart.v
+++ b/fpga/usrp3/lib/control/cvita_uart.v
@@ -2,19 +2,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //create a compressed vita based uart data interface
 
diff --git a/fpga/usrp3/lib/control/filter_bad_sid.v b/fpga/usrp3/lib/control/filter_bad_sid.v
new file mode 100644
index 000000000..864094951
--- /dev/null
+++ b/fpga/usrp3/lib/control/filter_bad_sid.v
@@ -0,0 +1,72 @@
+// Discard silently packets which don't match this SID
+
+module filter_bad_sid
+  (
+   input clk,
+   input reset,
+   input clear,
+   //
+   input [64:0] i_tdata,
+   input i_tvalid,
+   output i_tready,
+   //
+   output [64:0] o_tdata,
+   output o_tvalid,
+   input  o_tready,
+   //
+   output reg [15:0] count
+   );
+
+   reg [1:0] state;
+   wire      good_sid;
+   wire      qualify_i_tvalid;
+   
+   localparam IDLE = 0;
+   localparam ACCEPT = 1;
+   localparam DISCARD = 2;
+   
+
+   always @(posedge clk)
+     if (reset | clear) begin
+	state <= IDLE;
+	count <= 0;
+     end else
+       case(state)
+	 //
+	 IDLE: begin
+	    if  (i_tvalid && i_tready)
+	      if (good_sid)
+		state <= ACCEPT;
+	      else begin
+		 count <= count + 1;
+		 state <= DISCARD;
+	      end	    
+	 end
+	 //
+	 ACCEPT: begin
+	    if (i_tvalid && i_tready && i_tdata[64]) 
+	      state <= IDLE;
+	 end
+	 //
+	 DISCARD: begin
+	    if (i_tvalid && i_tready && i_tdata[64]) 
+	      state <= IDLE;
+	 end
+       endcase // case(state)
+   
+   assign good_sid = ((i_tdata[15:0] == 16'h00A0) || (i_tdata[15:0] == 16'h00B0));
+   
+   assign qualify_i_tvalid = (state == IDLE) ? good_sid : ((state == DISCARD) ? 1'b0 : 1'b1);
+
+   //
+   // Buffer output, break combinatorial timing paths
+   //
+   axi_fifo_short #(.WIDTH(65)) fifo_short
+     (
+      .clk(clk), .reset(reset), .clear(clear),
+      .i_tdata(i_tdata), .i_tvalid(i_tvalid && qualify_i_tvalid), .i_tready(i_tready),
+      .o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
+      .space(), .occupied()
+      );
+   
+endmodule // axi_fast_fifo
diff --git a/fpga/usrp3/lib/control/gpio_atr.v b/fpga/usrp3/lib/control/gpio_atr.v
index 16449a711..2e2f812f3 100644
--- a/fpga/usrp3/lib/control/gpio_atr.v
+++ b/fpga/usrp3/lib/control/gpio_atr.v
@@ -2,24 +2,14 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module gpio_atr
   #(parameter BASE = 0,
-    parameter WIDTH = 32)
+    parameter WIDTH = 32,
+    parameter default_ddr = 0,
+    parameter default_idle = 0)
    (input clk, input reset,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     input rx, input tx,
@@ -32,7 +22,7 @@ module gpio_atr
    reg [WIDTH-1:0]    gpio_pipe;
    
    
-   setting_reg #(.my_addr(BASE+0), .width(WIDTH)) reg_idle
+   setting_reg #(.my_addr(BASE+0), .width(WIDTH), .at_reset(default_idle)) reg_idle
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
       .out(in_idle),.changed());
 
@@ -48,7 +38,7 @@ module gpio_atr
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
       .out(in_fdx),.changed());
 
-   setting_reg #(.my_addr(BASE+4), .width(WIDTH)) reg_ddr
+   setting_reg #(.my_addr(BASE+4), .width(WIDTH), .at_reset(default_ddr)) reg_ddr
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),
       .out(ddr),.changed());
 
diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v
index 89dc93d82..0e4fcd88a 100644
--- a/fpga/usrp3/lib/control/por_gen.v
+++ b/fpga/usrp3/lib/control/por_gen.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module por_gen
diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v
index ab93157a4..434af0ff3 100644
--- a/fpga/usrp3/lib/control/ram_2port.v
+++ b/fpga/usrp3/lib/control/ram_2port.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 
diff --git a/fpga/usrp3/lib/control/reset_sync.v b/fpga/usrp3/lib/control/reset_sync.v
index 3a58c0a5f..da284e62e 100644
--- a/fpga/usrp3/lib/control/reset_sync.v
+++ b/fpga/usrp3/lib/control/reset_sync.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 
diff --git a/fpga/usrp3/lib/control/serial_to_settings.v b/fpga/usrp3/lib/control/serial_to_settings.v
index 53e112a62..3dcd80b23 100644
--- a/fpga/usrp3/lib/control/serial_to_settings.v
+++ b/fpga/usrp3/lib/control/serial_to_settings.v
@@ -10,7 +10,9 @@ module serial_to_settings
    // Settngs bus out
    output reg set_stb,
    output reg [7:0] set_addr,
-   output reg [31:0] set_data
+   output reg [31:0] set_data,
+   // Debug
+   output [31:0] debug
    );
 
    reg [2:0] 	 state;
@@ -105,6 +107,14 @@ module serial_to_settings
 	  
 	endcase // case(state)
      end // else: !if(reset)
+
+   assign debug =
+		 {
+		  counter[4:0],
+		  state[2:0],
+		  scl_reg,
+		  sda_reg
+		  };
    
 
 
diff --git a/fpga/usrp3/lib/control/serial_to_settings_tb.v b/fpga/usrp3/lib/control/serial_to_settings_tb.v
index 8111c115e..adaa2c985 100644
--- a/fpga/usrp3/lib/control/serial_to_settings_tb.v
+++ b/fpga/usrp3/lib/control/serial_to_settings_tb.v
@@ -45,6 +45,34 @@ module serial_to_settings_tb();
       .set_data(set_data)
       );
 
+   // Nasty HAck to convert settings to wishbone crudely.
+   reg 	       wb_stb;
+   wire        wb_ack_o;
+   
+   
+   always @(posedge clk)
+     if (reset)
+       wb_stb <= 0;
+     else
+       wb_stb <= set_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb);
+   
+     simple_uart debug_uart
+     (
+      .clk_i(clk), 
+      .rst_i(reset),
+      .we_i(wb_stb), 
+      .stb_i(wb_stb), 
+      .cyc_i(wb_stb), 
+      .ack_o(wb_ack_o),
+      .adr_i(set_addr[2:0]), 
+      .dat_i(set_data[31:0]), 
+      .dat_o(),
+      .rx_int_o(), 
+      .tx_int_o(), 
+      .tx_o(txd), 
+      .rx_i(rxd), 
+      .baud_o()
+      );
    
    //
    // Bring in a simulation script here
diff --git a/fpga/usrp3/lib/control/setting_reg.v b/fpga/usrp3/lib/control/setting_reg.v
index e9c1c73ac..1664f54e2 100644
--- a/fpga/usrp3/lib/control/setting_reg.v
+++ b/fpga/usrp3/lib/control/setting_reg.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011-2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //----------------------------------------------------------------------
 //-- A settings register is a peripheral for the settings register bus.
diff --git a/fpga/usrp3/lib/control/settings_bus_crossclock.v b/fpga/usrp3/lib/control/settings_bus_crossclock.v
index de74f67ee..2a6e7e7ef 100644
--- a/fpga/usrp3/lib/control/settings_bus_crossclock.v
+++ b/fpga/usrp3/lib/control/settings_bus_crossclock.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011-2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 
diff --git a/fpga/usrp3/lib/control/simple_i2c_core.v b/fpga/usrp3/lib/control/simple_i2c_core.v
index 9c61de8fb..47f1ac82a 100644
--- a/fpga/usrp3/lib/control/simple_i2c_core.v
+++ b/fpga/usrp3/lib/control/simple_i2c_core.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // Simple I2C core
 
diff --git a/fpga/usrp3/lib/control/simple_spi_core.v b/fpga/usrp3/lib/control/simple_spi_core.v
index b94515e40..b4d410433 100644
--- a/fpga/usrp3/lib/control/simple_spi_core.v
+++ b/fpga/usrp3/lib/control/simple_spi_core.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2012 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // Simple SPI core, the simplest, yet complete spi core I can think of
 
@@ -69,9 +57,9 @@ module simple_spi_core
         output ready,
 
         //spi interface, slave selects, clock, data in, data out
-        output [WIDTH-1:0] sen,
+        output reg [WIDTH-1:0] sen,
         output sclk,
-        output mosi,
+        output reg mosi,
         input miso,
 
         //optional debug output
@@ -113,22 +101,30 @@ module simple_spi_core
     assign sclk = sclk_reg;
 
     //serial enables either idle or enabled based on state
+    // IJB. One pipeline stage to break critical path from register in I/O pads.
     wire sen_is_idle = (state == WAIT_TRIG) || (state == IDLE_SEN);
     wire [23:0] sen24 = (sen_is_idle)? SEN_IDLE : (SEN_IDLE ^ slave_select);
     reg [WIDTH-1:0] sen_reg;
-    always @(posedge clock) sen_reg <= sen24[WIDTH-1:0];
-    assign sen = sen_reg;
+    always @(posedge clock) 
+      sen_reg <= sen24[WIDTH-1:0];
+    always @(posedge clock) 
+      sen <= sen_reg;
 
     //data output shift register
+   // IJB. One pipeline stage to break critical path from register in I/O pads.
     reg [31:0] dataout_reg;
     wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0};
-    assign mosi = dataout_reg[31];
+   
+   always @(posedge clock)
+     mosi <= dataout_reg[31];
 
     //data input shift register
-   // IJB. One pipeline stage to break critical path from register in I/O pads.
-   reg 		miso_pipe;
-   always @(posedge clock)
-     miso_pipe = miso;
+   // IJB. Two pipeline stages to break critical path from register in I/O pads.
+   reg 		miso_pipe, miso_pipe2;
+   always @(posedge clock) begin
+      miso_pipe2 <= miso;
+      miso_pipe <= miso_pipe2;
+   end
    
     reg [31:0] datain_reg;
     wire [31:0] datain_next = {datain_reg[30:0], miso_pipe};