diff options
Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv')
-rw-r--r-- | fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv | 10 | ||||
-rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv | 10 | ||||
-rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 12 | ||||
-rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv | 14 | ||||
-rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv | 9 | ||||
-rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv | 22 |
6 files changed, 38 insertions, 39 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv b/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv index cfba6d2eb..de7a82ae8 100644 --- a/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv +++ b/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv @@ -186,7 +186,7 @@ interface AxiStreamPacketIf #( end end end - + //--------------------------------------- // Packing functions //--------------------------------------- @@ -292,9 +292,9 @@ interface AxiStreamPacketIf #( localparam USER_TRAILING_WIDTH = USER_WIDTH >= TRAILING_WIDTH ? TRAILING_WIDTH : USER_WIDTH; assert (TUSER) else - $fatal("Can't get trailing if TUSER doesn't exist"); + $fatal(1, "Can't get trailing if TUSER doesn't exist"); assert (USER_WIDTH >= TRAILING_WIDTH) else - $fatal("USER_WIDTH is to narrow to contain trailing"); + $fatal(1, "USER_WIDTH is to narrow to contain trailing"); return trailing2keep(tuser[USER_TRAILING_WIDTH-1:0]); endfunction : get_trailing_bytes @@ -302,9 +302,9 @@ interface AxiStreamPacketIf #( localparam USER_TRAILING_WIDTH = USER_WIDTH >= TRAILING_WIDTH ? TRAILING_WIDTH : USER_WIDTH; assert (TUSER) else - $fatal("Can't set trailing if TUSER doesn't exist"); + $fatal(1, "Can't set trailing if TUSER doesn't exist"); assert (USER_WIDTH >= TRAILING_WIDTH) else - $fatal("USER_WIDTH is to narrow to set trailing"); + $fatal(1, "USER_WIDTH is to narrow to set trailing"); tuser[USER_TRAILING_WIDTH-1:0] = keep2trailing(keep); endtask : set_trailing_bytes diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv index 57124a0b5..cb56a68e2 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv @@ -57,15 +57,15 @@ module axi4s_add_bytes #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.USER_WIDTH >= UWIDTH) else - $fatal("i.USER_WIDTH is to small"); + $fatal(1, "i.USER_WIDTH is to small"); assert (o.USER_WIDTH >= UWIDTH) else - $fatal("o.USER_WIDTH is to small"); + $fatal(1, "o.USER_WIDTH is to small"); assert (ADD_START == 0) else - $fatal("Only tested for ADD_START = 0"); + $fatal(1, "Only tested for ADD_START = 0"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index c3c71999d..3a434ceb0 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -27,17 +27,17 @@ module axi4s_fifo #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.TDATA == o.TDATA) else - $fatal("TDATA present mismatch"); + $fatal(1, "TDATA present mismatch"); assert (i.TUSER == o.TUSER) else - $fatal("TUSER present mismatch"); + $fatal(1, "TUSER present mismatch"); assert (i.TKEEP == o.TKEEP) else - $fatal("TKEEP present mismatch"); + $fatal(1, "TKEEP present mismatch"); assert (i.TLAST == o.TLAST) else - $fatal("TLAST present mismatch"); + $fatal(1, "TLAST present mismatch"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv index a1b744adf..a6d190d92 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_packet_gate.sv @@ -35,19 +35,19 @@ module axi4s_packet_gate #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.TDATA == o.TDATA) else - $fatal("TDATA present mismatch"); + $fatal(1, "TDATA present mismatch"); assert (i.TUSER == o.TUSER) else - $fatal("TUSER present mismatch"); + $fatal(1, "TUSER present mismatch"); assert (i.TKEEP == o.TKEEP) else - $fatal("TKEEP present mismatch"); + $fatal(1, "TKEEP present mismatch"); assert (i.TLAST == 1) else - $fatal("i.TLAST not present"); + $fatal(1, "i.TLAST not present"); assert (o.TLAST == 1) else - $fatal("o.TLAST not present"); + $fatal(1, "o.TLAST not present"); end localparam WIDTH = i.DWIDTH + i.UWIDTH + i.KWIDTH; diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv index 382cdb13b..9522a356a 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv @@ -69,11 +69,11 @@ module axi4s_remove_bytes #( localparam MIDDLE = END_BYTE >= START_BYTE; `include "axi4s.vh" - + // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), @@ -162,7 +162,7 @@ module axi4s_remove_bytes #( //----------------------------------------------------------------------- function automatic logic [START_BYTE*8-1:0] start_part([s0.DATA_WIDTH-1:0] data); begin - // workaround :: modelsim optimizer can fail if there is aposibility of a 0+:0 + // workaround :: modelsim optimizer can fail if there is a possibility of a 0+:0 localparam MY_START_BYTE = START_BYTE ? START_BYTE : 1; return data[0+:MY_START_BYTE*8]; end @@ -468,7 +468,6 @@ module axi4s_remove_bytes #( // the WRAP case leans forward one word since it bridges to // the next word so it needs to reach end_plus early - // REMOVE statemachine always_comb begin : reached_end_comb if (MCASE==MS_WRAP) begin reached_end = s0.reached_packet_byte(REM_END); @@ -487,7 +486,7 @@ module axi4s_remove_bytes #( logic s0_tready; always_comb s0.tready = s0_tready; - // Remove Statemachine + // Remove State Machine always_comb begin : remove_next_state // default assignment of next_state next_remove_state = remove_state; diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv index 0660ee961..d146539b2 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv @@ -37,34 +37,34 @@ module axi4s_width_conv #( initial begin if(i.TKEEP) begin assert (!I_USER_TRAILING_BYTES) else - $fatal("I_USER_TRAILING_BYTE set at the same time as TKEEP"); + $fatal(1, "I_USER_TRAILING_BYTE set at the same time as TKEEP"); assert (!i.TUSER) else - $fatal("i.TUSER set- This module does not pass user"); + $fatal(1, "i.TUSER set- This module does not pass user"); end else if(I_USER_TRAILING_BYTES) begin assert (i.USER_WIDTH >= i.TRAILING_WIDTH ) else - $fatal("i.USER_WIDTH does not match TRAILING_WIDTH"); + $fatal(1, "i.USER_WIDTH does not match TRAILING_WIDTH"); end else begin assert (!i.TUSER) else - $fatal("This module does not pass generic user_data"); + $fatal(1, "This module does not pass generic user_data"); end if(o.TKEEP) begin assert (!O_USER_TRAILING_BYTES) else - $fatal("O_USER_TRAILING_BYTE set at the same time as TKEEP"); + $fatal(1, "O_USER_TRAILING_BYTE set at the same time as TKEEP"); assert (!o.TUSER) else - $fatal("O.TUSER set- This module does not pass user"); + $fatal(1, "O.TUSER set- This module does not pass user"); end else if(O_USER_TRAILING_BYTES) begin assert (o.USER_WIDTH >= o.TRAILING_WIDTH) else - $fatal("o.USER_WIDTH does not match TRAILING_WIDTH"); + $fatal(1, "o.USER_WIDTH does not match TRAILING_WIDTH"); end else begin assert (!o.TUSER) else - $fatal("This module does not pass generic user_data"); + $fatal(1, "This module does not pass generic user_data"); end assert (i.TLAST == 1) else - $fatal("i.TLAST not present"); + $fatal(1, "i.TLAST not present"); assert (o.TLAST == 1) else - $fatal("o.TLAST not present"); + $fatal(1, "o.TLAST not present"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), @@ -105,7 +105,7 @@ module axi4s_width_conv #( always_comb s1.tkeep = 'X; always_comb begin : assign_s1_tuser s1.tuser = 0; - // MODELSIM_BUG - deleting the s1_bytes assignment causes modelsim failures. + // MODELSIM_BUG - deleting the s1_bytes assignment causes ModelSim failures. s1_bytes = s1.keep2trailing(s1_tkeep); s1.set_trailing_bytes(s1_tkeep); end |