diff options
Diffstat (limited to 'fpga/usrp2')
| -rw-r--r-- | fpga/usrp2/sdr_lib/dspengine_16to8.v | 6 | ||||
| -rw-r--r-- | fpga/usrp2/sdr_lib/dspengine_8to16.v | 8 | ||||
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/N2x0/u2plus_core.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/USRP2/u2_core.v | 4 |
5 files changed, 13 insertions, 13 deletions
diff --git a/fpga/usrp2/sdr_lib/dspengine_16to8.v b/fpga/usrp2/sdr_lib/dspengine_16to8.v index 448c57d35..1d6746dd1 100644 --- a/fpga/usrp2/sdr_lib/dspengine_16to8.v +++ b/fpga/usrp2/sdr_lib/dspengine_16to8.v @@ -1,5 +1,5 @@ -// Copyright 2011-2012 Ettus Research LLC +// Copyright 2011-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -181,8 +181,8 @@ module dspengine_16to8 assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } : (dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } : - (last_o&~even_o) ? {4'h0, 16'd0, i8, q8 } : - {4'h0, i8, q8, i8_reg, q8_reg }; + (last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } : + {4'h0, i8_reg, q8_reg, i8, q8 }; assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr; diff --git a/fpga/usrp2/sdr_lib/dspengine_8to16.v b/fpga/usrp2/sdr_lib/dspengine_8to16.v index 85187d78d..64246ac13 100644 --- a/fpga/usrp2/sdr_lib/dspengine_8to16.v +++ b/fpga/usrp2/sdr_lib/dspengine_8to16.v @@ -1,5 +1,5 @@ -// Copyright 2012 Ettus Research LLC +// Copyright 2012-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -75,13 +75,13 @@ module dspengine_8to16 wire [15:0] data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd; reg [7:0] i8_0, q8_0; - wire [7:0] i8_1 = access_dat_i[31:24]; - wire [7:0] q8_1 = access_dat_i[23:16]; + wire [7:0] i8_1 = access_dat_i[15:8]; + wire [7:0] q8_1 = access_dat_i[7:0]; reg skip; always @(posedge clk) - { i8_0, q8_0 } <= access_dat_i[15:0]; + { i8_0, q8_0 } <= access_dat_i[31:16]; always @(posedge clk) if(reset | clear) diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 9fe09c60e..7f137f0d1 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -1,5 +1,5 @@ // -// Copyright 2011-2012 Ettus Research LLC +// Copyright 2011-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -71,7 +71,7 @@ module u1plus_core localparam SR_GPIO = 224; // 5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd11, 16'd3}; //major, minor + localparam compat_num = {16'd11, 16'd4}; //major, minor //assign run signals used for ATR logic wire [NUM_RX_DSPS-1:0] run_rx_n; diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index e2539e183..f616681d2 100644 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -1,5 +1,5 @@ // -// Copyright 2011-2012 Ettus Research LLC +// Copyright 2011-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -448,7 +448,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd10, 16'd0}; //major, minor + localparam compat_num = {16'd10, 16'd1}; //major, minor wire [31:0] irq_readback = {18'b0, button, spi_ready, clk_status, serdes_link_up, 10'b0}; diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index d8fe8cf10..aed69a9bd 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -1,5 +1,5 @@ // -// Copyright 2011-2012 Ettus Research LLC +// Copyright 2011-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -456,7 +456,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd10, 16'd0}; //major, minor + localparam compat_num = {16'd10, 16'd1}; //major, minor wire [31:0] irq_readback = {19'b0, spi_ready, clk_status, serdes_link_up, 10'b0}; |