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-rw-r--r--fpga/usrp2/top/B100/B100.ucf200
-rw-r--r--fpga/usrp2/top/B100/B100.v172
-rw-r--r--fpga/usrp2/top/B100/Makefile.B10098
-rw-r--r--fpga/usrp2/top/B100/Makefile.u1plus (renamed from fpga/usrp2/top/B100/Makefile)4
-rw-r--r--fpga/usrp2/top/B100/u1plus.ucf4
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v11
-rw-r--r--fpga/usrp2/top/E1x0/u1e.ucf6
-rw-r--r--fpga/usrp2/top/E1x0/u1e.v5
-rw-r--r--fpga/usrp2/top/E1x0/u1e_core.v25
9 files changed, 493 insertions, 32 deletions
diff --git a/fpga/usrp2/top/B100/B100.ucf b/fpga/usrp2/top/B100/B100.ucf
new file mode 100644
index 000000000..69fd49971
--- /dev/null
+++ b/fpga/usrp2/top/B100/B100.ucf
@@ -0,0 +1,200 @@
+## Main Clock
+NET "CLK_FPGA_P" LOC = "R7" ;
+NET "CLK_FPGA_N" LOC = "T7" ;
+
+## I2C
+NET "SDA_FPGA" LOC = "T13" ;
+NET "SCL_FPGA" LOC = "R13" ;
+
+## CGEN
+NET "cgen_st_ld" LOC = "M13" ;
+NET "cgen_st_refmon" LOC = "J14" ;
+NET "cgen_st_status" LOC = "P6" ;
+NET "cgen_ref_sel" LOC = "T2" ;
+NET "cgen_sync_b" LOC = "H15" ;
+
+## FPGA Config
+#NET "fpga_cfg_din" LOC = "T14" ;
+#NET "fpga_cfg_cclk" LOC = "R14" ;
+#NET "fpga_cfg_init_b" LOC = "T12" ;
+
+## MISC
+#NET "mystery_bus<1>" LOC = "C4" ;
+#NET "mystery_bus<0>" LOC = "E7" ;
+NET "reset_n" LOC = "D5" ;
+NET "PPS_IN" LOC = "M14" ;
+NET "reset_codec" LOC = "B14" ;
+
+## GPIF
+NET "GPIF_D<15>" LOC = "P7" ;
+NET "GPIF_D<14>" LOC = "N8" ;
+NET "GPIF_D<13>" LOC = "T5" ;
+NET "GPIF_D<12>" LOC = "T6" ;
+NET "GPIF_D<11>" LOC = "N6" ;
+NET "GPIF_D<10>" LOC = "P5" ;
+NET "GPIF_D<9>" LOC = "R3" ;
+NET "GPIF_D<8>" LOC = "T3" ;
+NET "GPIF_D<7>" LOC = "N12" ;
+NET "GPIF_D<6>" LOC = "P13" ;
+NET "GPIF_D<5>" LOC = "P11" ;
+NET "GPIF_D<4>" LOC = "R9" ;
+NET "GPIF_D<3>" LOC = "T9" ;
+NET "GPIF_D<2>" LOC = "N9" ;
+NET "GPIF_D<1>" LOC = "P9" ;
+NET "GPIF_D<0>" LOC = "P8" ;
+
+NET "GPIF_CTL<3>" LOC = "N5" ;
+NET "GPIF_CTL<2>" LOC = "M11" ;
+NET "GPIF_CTL<1>" LOC = "M9" ;
+NET "GPIF_CTL<0>" LOC = "M7" ;
+
+NET "GPIF_RDY<3>" LOC = "N11" ;
+NET "GPIF_RDY<2>" LOC = "T10" ;
+NET "GPIF_RDY<1>" LOC = "T4" ;
+NET "GPIF_RDY<0>" LOC = "R5" ;
+
+NET "GPIF_CS" LOC = "P12" ;
+NET "GPIF_SLOE" LOC = "R11" ;
+NET "GPIF_PKTEND" LOC = "P10" ;
+NET "GPIF_ADR<0>" LOC = "T11" ;
+NET "GPIF_ADR<1>" LOC = "H16" ;
+
+NET "IFCLK" LOC = "T8" ;
+
+## LEDs
+NET "debug_led<2>" LOC = "R2" ;
+NET "debug_led<1>" LOC = "N4" ;
+NET "debug_led<0>" LOC = "P4" ;
+
+## Debug bus
+NET "debug_clk<0>" LOC = "K15" ;
+NET "debug_clk<1>" LOC = "K14" ;
+NET "debug<0>" LOC = "K16" ;
+NET "debug<1>" LOC = "J16" ;
+NET "debug<2>" LOC = "C16" ;
+NET "debug<3>" LOC = "C15" ;
+NET "debug<4>" LOC = "E13" ;
+NET "debug<5>" LOC = "D14" ;
+NET "debug<6>" LOC = "D16" ;
+NET "debug<7>" LOC = "D15" ;
+NET "debug<8>" LOC = "E14" ;
+NET "debug<9>" LOC = "F13" ;
+NET "debug<10>" LOC = "G13" ;
+NET "debug<11>" LOC = "F14" ;
+NET "debug<12>" LOC = "E16" ;
+NET "debug<13>" LOC = "F15" ;
+NET "debug<14>" LOC = "H13" ;
+NET "debug<15>" LOC = "G14" ;
+NET "debug<16>" LOC = "G16" ;
+NET "debug<17>" LOC = "F16" ;
+NET "debug<18>" LOC = "J12" ;
+NET "debug<19>" LOC = "J13" ;
+NET "debug<20>" LOC = "L14" ;
+NET "debug<21>" LOC = "L16" ;
+NET "debug<22>" LOC = "M15" ;
+NET "debug<23>" LOC = "M16" ;
+NET "debug<24>" LOC = "L13" ;
+NET "debug<25>" LOC = "K13" ;
+NET "debug<26>" LOC = "P16" ;
+NET "debug<27>" LOC = "N16" ;
+NET "debug<28>" LOC = "R15" ;
+NET "debug<29>" LOC = "P15" ;
+NET "debug<30>" LOC = "N13" ;
+NET "debug<31>" LOC = "N14" ;
+
+## ADC
+NET "adc<11>" LOC = "B15" ;
+NET "adc<10>" LOC = "A8" ;
+NET "adc<9>" LOC = "B8" ;
+NET "adc<8>" LOC = "C8" ;
+NET "adc<7>" LOC = "D8" ;
+NET "adc<6>" LOC = "C9" ;
+NET "adc<5>" LOC = "A9" ;
+NET "adc<4>" LOC = "C10" ;
+NET "adc<3>" LOC = "D9" ;
+NET "adc<2>" LOC = "A3" ;
+NET "adc<1>" LOC = "B3" ;
+NET "adc<0>" LOC = "A4" ;
+NET "RXSYNC" LOC = "D10" ;
+
+## DAC
+NET "TXBLANK" LOC = "K1" ;
+NET "TXSYNC" LOC = "J2" ;
+NET "dac<0>" LOC = "J1" ;
+NET "dac<1>" LOC = "H3" ;
+NET "dac<2>" LOC = "J3" ;
+NET "dac<3>" LOC = "G2" ;
+NET "dac<4>" LOC = "H1" ;
+NET "dac<5>" LOC = "N3" ;
+NET "dac<6>" LOC = "M4" ;
+NET "dac<7>" LOC = "R1" ;
+NET "dac<8>" LOC = "P2" ;
+NET "dac<9>" LOC = "P1" ;
+NET "dac<10>" LOC = "M1" ;
+NET "dac<11>" LOC = "N1" ;
+NET "dac<12>" LOC = "M3" ;
+NET "dac<13>" LOC = "L4" ;
+
+## TX DB
+NET "io_tx<0>" LOC = "K4" ;
+NET "io_tx<1>" LOC = "L3" ;
+NET "io_tx<2>" LOC = "L2" ;
+NET "io_tx<3>" LOC = "F1" ;
+NET "io_tx<4>" LOC = "F3" ;
+NET "io_tx<5>" LOC = "G3" ;
+NET "io_tx<6>" LOC = "E3" ;
+NET "io_tx<7>" LOC = "E2" ;
+NET "io_tx<8>" LOC = "E4" ;
+NET "io_tx<9>" LOC = "F4" ;
+NET "io_tx<10>" LOC = "D1" ;
+NET "io_tx<11>" LOC = "E1" ;
+NET "io_tx<12>" LOC = "D4" ;
+NET "io_tx<13>" LOC = "D3" ;
+NET "io_tx<14>" LOC = "C2" ;
+NET "io_tx<15>" LOC = "C1" ;
+
+## RX DB
+NET "io_rx<0>" LOC = "D7" ;
+NET "io_rx<1>" LOC = "C6" ;
+NET "io_rx<2>" LOC = "A6" ;
+NET "io_rx<3>" LOC = "B6" ;
+NET "io_rx<4>" LOC = "E9" ;
+NET "io_rx<5>" LOC = "A7" ;
+NET "io_rx<6>" LOC = "C7" ;
+NET "io_rx<7>" LOC = "B10" ;
+NET "io_rx<8>" LOC = "A10" ;
+NET "io_rx<9>" LOC = "C11" ;
+NET "io_rx<10>" LOC = "A11" ;
+NET "io_rx<11>" LOC = "D11" ;
+NET "io_rx<12>" LOC = "B12" ;
+NET "io_rx<13>" LOC = "A12" ;
+NET "io_rx<14>" LOC = "A14" ;
+NET "io_rx<15>" LOC = "A13" ;
+
+## SPI
+#NET "SEN_AUX" LOC = "C12" ;
+#NET "SCLK_AUX" LOC = "D12" ;
+#NET "MISO_AUX" LOC = "J5" ;
+NET "SCLK_CODEC" LOC = "K3" ;
+NET "SEN_CODEC" LOC = "D13" ;
+NET "MOSI_CODEC" LOC = "C13" ;
+NET "MISO_CODEC" LOC = "G4" ;
+
+NET "MISO_RX_DB" LOC = "E6" ;
+NET "SEN_RX_DB" LOC = "B4" ;
+NET "MOSI_RX_DB" LOC = "A5" ;
+NET "SCLK_RX_DB" LOC = "C5" ;
+
+NET "MISO_TX_DB" LOC = "J4" ;
+NET "SEN_TX_DB" LOC = "N2" ;
+NET "MOSI_TX_DB" LOC = "L1" ;
+NET "SCLK_TX_DB" LOC = "G1" ;
+
+## Dedicated pins
+#NET "TMS" LOC = "B2" ;
+#NET "TDO" LOC = "B16" ;
+#NET "TDI" LOC = "B1" ;
+#NET "TCK" LOC = "A15" ;
+
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "T15" ;
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
new file mode 100644
index 000000000..f2d75c54e
--- /dev/null
+++ b/fpga/usrp2/top/B100/B100.v
@@ -0,0 +1,172 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module B100
+ (input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+
+ // GPIF
+ inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
+ input [1:0] GPIF_ADR, output GPIF_CS, output GPIF_SLOE, output GPIF_PKTEND,
+ input IFCLK,
+
+ inout SDA_FPGA, inout SCL_FPGA, // I2C
+
+ output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI
+ output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI
+ output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI
+
+ input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+
+ inout [15:0] io_tx, inout [15:0] io_rx,
+
+ output [13:0] dac, output TXSYNC, output TXBLANK,
+ input [11:0] adc, input RXSYNC,
+
+ input PPS_IN,
+ input reset_n, output reset_codec
+ );
+
+ assign reset_codec = 1; // Believed to be active low
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Clocking
+ wire clk_fpga, clk_fpga_in, reset;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
+ clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+ BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
+
+ reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // SPI
+ wire mosi, sclk, miso;
+ assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
+ assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
+ assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
+ assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
+ (~SEN_CODEC & MISO_CODEC);
+
+ // /////////////////////////////////////////////////////////////////////////
+ // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+ assign TXBLANK = 0;
+ wire [13:0] tx_i, tx_q;
+
+ genvar i;
+ generate
+ for(i=0;i<14;i=i+1)
+ begin : gen_dacout
+ ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D0(tx_i[i]), // 1-bit data input (associated with C0)
+ .D1(tx_q[i]), // 1-bit data input (associated with C1)
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+ end // block: gen_dacout
+ endgenerate
+ ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D0(1'b0), // 1-bit data input (associated with C0)
+ .D1(1'b1), // 1-bit data input (associated with C1)
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+
+ // /////////////////////////////////////////////////////////////////////////
+ // RX ADC -- handles deinterleaving
+
+ reg [11:0] rx_i, rx_q;
+ wire [11:0] rx_a, rx_b;
+
+ genvar j;
+ generate
+ for(j=0;j<12;j=j+1)
+ begin : gen_adcin
+ IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
+ .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock
+ .Q1(rx_b[j]), // 1-bit output captured with C1 clock
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D(adc[j]), // 1-bit DDR data input
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+ end // block: gen_adcin
+ endgenerate
+
+ IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
+ .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
+ .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
+ .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
+ IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock
+ .Q1(rxsync_1), // 1-bit output captured with C1 clock
+ .C0(clk_fpga), // 1-bit clock input
+ .C1(~clk_fpga), // 1-bit clock input
+ .CE(1'b1), // 1-bit clock enable input
+ .D(RXSYNC), // 1-bit DDR data input
+ .R(1'b0), // 1-bit reset input
+ .S(1'b0)); // 1-bit set input
+
+ always @(posedge clk_fpga)
+ if(rxsync_0)
+ begin
+ rx_i <= rx_b;
+ rx_q <= rx_a;
+ end
+ else
+ begin
+ rx_i <= rx_a;
+ rx_q <= rx_b;
+ end
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Main U1E Core
+ u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
+ .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .debug_txd(), .debug_rxd(1'b1),
+ .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
+ .gpif_misc({GPIF_CS,GPIF_SLOE,GPIF_PKTEND}),
+ .gpif_clk(IFCLK),
+
+ .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
+ .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
+ .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon),
+ .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
+ .io_tx(io_tx), .io_rx(io_rx),
+ .tx_i(tx_i), .tx_q(tx_q),
+ .rx_i(rx_i), .rx_q(rx_q),
+ .pps_in(PPS_IN) );
+
+endmodule // B100
diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100
new file mode 100644
index 000000000..90dd25942
--- /dev/null
+++ b/fpga/usrp2/top/B100/Makefile.B100
@@ -0,0 +1,98 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE := B100
+BUILD_DIR := build-B100/
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../gpif/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan3A" \
+device XC3S1400A \
+package ft256 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+B100.v \
+u1plus_core.v \
+B100.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPIF_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile.u1plus
index 7ab56f9bd..e08a11126 100644
--- a/fpga/usrp2/top/B100/Makefile
+++ b/fpga/usrp2/top/B100/Makefile.u1plus
@@ -5,8 +5,8 @@
##################################################
# Project Setup
##################################################
-BUILD_DIR := build/
-export TOP_MODULE := u1plus
+TOP_MODULE := u1plus
+BUILD_DIR := build-u1plus/
export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
include ../Makefile.common
diff --git a/fpga/usrp2/top/B100/u1plus.ucf b/fpga/usrp2/top/B100/u1plus.ucf
index cd89878e3..3ecc4daf2 100644
--- a/fpga/usrp2/top/B100/u1plus.ucf
+++ b/fpga/usrp2/top/B100/u1plus.ucf
@@ -199,5 +199,5 @@ NET "SCLK_TX_DB" LOC = "G1" ;
#NET "TDI" LOC = "B1" ;
#NET "TCK" LOC = "A15" ;
-##NET "fpga_cfg_prog_b" LOC = "A2" ;
-##NET "fpga_cfg_done" LOC = "T15" ;
+#NET "fpga_cfg_prog_b" LOC = "A2" ;
+#NET "fpga_cfg_done" LOC = "T15" ;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index b40083201..61c1df04c 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -205,7 +205,7 @@ module u1plus_core
.data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
.data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
.data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
+
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
@@ -297,7 +297,8 @@ module u1plus_core
.sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
.sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
- assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0;
+ assign s5_ack = 0;
+ assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0;
assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0;
// /////////////////////////////////////////////////////////////////////////////////////
@@ -410,10 +411,10 @@ module u1plus_core
// only have 64 regs, 32 bits each with current setup...
settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE
- (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi),
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi),
.wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
.strobe(set_stb),.addr(set_addr),.data(set_data) );
-
+
// /////////////////////////////////////////////////////////////////////////
// ATR Controller -- Slave #6
@@ -457,7 +458,7 @@ module u1plus_core
// /////////////////////////////////////////////////////////////////////////////////////
// Debug circuitry
- assign debug_clk = { gpif_clk, clk_fpga };
+ assign debug_clk = 2'b00; // { gpif_clk, clk_fpga };
assign debug = 0;
assign debug_gpio_0 = 0;
assign debug_gpio_1 = 0;
diff --git a/fpga/usrp2/top/E1x0/u1e.ucf b/fpga/usrp2/top/E1x0/u1e.ucf
index 0c487a601..278fc289a 100644
--- a/fpga/usrp2/top/E1x0/u1e.ucf
+++ b/fpga/usrp2/top/E1x0/u1e.ucf
@@ -67,8 +67,10 @@ NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug
NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug
## Overo UART
-#NET "overo_txd1" LOC = "C6" ;
-#NET "overo_rxd1" LOC = "D6" ;
+NET "overo_txd1" LOC = "C6" ;
+NET "overo_rxd1" LOC = "D6" ;
+NET "fpga_txd1" LOC = "AB9" ;
+NET "fpga_rxd1" LOC = "AB8" ;
## FTDI UART to USB converter
NET "FPGA_TXD" LOC = "G19" ;
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v
index ff2e08394..903ef7a6f 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/u1e.v
@@ -22,6 +22,7 @@ module u1e
(input CLK_FPGA_P, input CLK_FPGA_N, // Diff
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
input debug_pb, output FPGA_TXD, input FPGA_RXD,
+ output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1,
// GPMC
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -59,6 +60,10 @@ module u1e
clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
// /////////////////////////////////////////////////////////////////////////
+ // UART level conversion
+ assign fpga_txd1 = overo_txd1;
+ assign overo_rxd1 = fpga_rxd1;
+
// SPI
wire mosi, sclk, miso;
assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index 20dd98a36..e1bb50890 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -489,26 +489,9 @@ module u1e_core
// /////////////////////////////////////////////////////////////////////////////////////
// Debug circuitry
- assign debug_clk = { EM_CLK, clk_fpga };
-
-/*
- assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
- { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
- { EM_D } };
-
-*/
- assign debug = debug_gpmc;
-
- assign debug_gpio_0 = { {run_tx, 2'b0, strobe_rx0, tx_i[11:0]},
- {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
-
- assign debug_gpio_1 = debug_vt;
+ assign debug_clk = 2'b00; //{ EM_CLK, clk_fpga };
+ assign debug = 0;
+ assign debug_gpio_0 = 0;
+ assign debug_gpio_1 = 0;
-/*
- assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
- {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
- {2'b0, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
- {2'b0, bus_error, debug_gpmc[4:0] },
- {misc_gpio[7:0]} };
- */
endmodule // u1e_core
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 18:45:34 +0000