diff options
Diffstat (limited to 'fpga/usrp2/vrt/vita_rx_chain.v')
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index 8b41e5fa8..c57e6cc05 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -1,5 +1,5 @@ // -// Copyright 2011 Ettus Research LLC +// Copyright 2011-2012 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -20,21 +20,31 @@ module vita_rx_chain #(parameter BASE=0, parameter UNIT=0, parameter FIFOSIZE=10, - parameter PROT_ENG_FLAGS=1) - (input clk, input reset, input clear, + parameter PROT_ENG_FLAGS=1, + parameter DSP_NUMBER=0) + (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [63:0] vita_time, output overrun, - input [31:0] sample, output run, input strobe, + input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, + input [63:0] vita_time, + input [31:0] sample, input strobe, output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i, + output overrun, output run, output clear_o, output [31:0] debug ); - + wire [100:0] sample_data; wire sample_dst_rdy, sample_src_rdy; wire [31:0] vrc_debug, vrf_debug; wire [35:0] rx_data_int; wire rx_src_rdy_int, rx_dst_rdy_int; - + + wire clear; + assign clear_o = clear; + + setting_reg #(.my_addr(BASE+3)) sr + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear)); + vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -65,9 +75,10 @@ module vita_rx_chain .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); - dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 - (.clk(clk),.reset(reset),.clear(clear), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + vita_rx_engine_glue #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+3), .BUF_SIZE(FIFOSIZE)) dspengine_rx + (.clock(clk),.reset(reset),.clear(clear), + .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); |