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Diffstat (limited to 'fpga/usrp2/top/u2_rev3_2rx_iad/README')
| -rw-r--r-- | fpga/usrp2/top/u2_rev3_2rx_iad/README | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/README b/fpga/usrp2/top/u2_rev3_2rx_iad/README deleted file mode 100644 index 3efc5305b..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/README +++ /dev/null @@ -1,32 +0,0 @@ -This is a custom build for USRP2 FPGA. It allows using a BasicRX or -LFRX board and feed two independent, real signals. In addition, instead -of the CIC/HB decimator, which optimizes frequency response, it uses an -integrate and dump decimator, which optimizes for time-domain impulse -response. - -These changes have been made in dsp_core_rx.v: - -* A second DDC has been added, sharing a frequency register with - the existing DDC. - -* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... - into the receive FIFO. This limits the host configured decimation - to 8 intead of 4. Use gr.deinterleave to recover the streams. - -* The ADCs are hardcoded: - - RX_A ==> DDC #1 I-input - 0 ==> DDC #1 Q-input - RX_B ==> DDC #2 I-input - 0 ==> DDC #2 Q-input - - Thus, the input mux has been disabled. - -* The CIC/HB decimator has been replaced by an integrate and dump at - the decimation rate. - -* To assist with meeting timing, the external RAM has been disabled. - -The basic application is to coherently sample two real IF streams and -downconvert to baseband, while minimizing the impulse response duration -of the resampling filters. |