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-rw-r--r--fpga/usrp2/top/u2_rev3/u2_rev3.ucf151
1 files changed, 76 insertions, 75 deletions
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
index 6aa699d2a..deaeecb53 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ;
NET "PHY_INTn" LOC = "AB13" ;
NET "PHY_RESETn" LOC = "AA19" ;
NET "PHY_CLK" LOC = "V15" ;
-NET "RAM_D[0]" LOC = "N20" ;
-NET "RAM_D[1]" LOC = "N21" ;
-NET "RAM_D[2]" LOC = "N22" ;
-NET "RAM_D[3]" LOC = "M17" ;
-NET "RAM_D[4]" LOC = "M18" ;
-NET "RAM_D[5]" LOC = "M19" ;
-NET "RAM_D[6]" LOC = "M20" ;
-NET "RAM_D[7]" LOC = "M21" ;
-NET "RAM_D[8]" LOC = "M22" ;
-NET "RAM_D[9]" LOC = "Y22" ;
-NET "RAM_D[10]" LOC = "Y21" ;
-NET "RAM_D[11]" LOC = "Y20" ;
-NET "RAM_D[12]" LOC = "Y19" ;
-NET "RAM_D[13]" LOC = "W22" ;
-NET "RAM_D[14]" LOC = "W21" ;
-NET "RAM_D[15]" LOC = "W20" ;
-NET "RAM_D[16]" LOC = "W19" ;
-NET "RAM_D[17]" LOC = "V22" ;
-NET "RAM_A[0]" LOC = "U21" ;
-NET "RAM_A[1]" LOC = "T19" ;
-NET "RAM_A[2]" LOC = "V21" ;
-NET "RAM_A[3]" LOC = "V20" ;
-NET "RAM_A[4]" LOC = "T20" ;
-NET "RAM_A[5]" LOC = "T21" ;
-NET "RAM_A[6]" LOC = "T22" ;
-NET "RAM_A[7]" LOC = "T18" ;
-NET "RAM_A[8]" LOC = "R18" ;
-NET "RAM_A[9]" LOC = "P19" ;
-NET "RAM_A[10]" LOC = "P21" ;
-NET "RAM_A[11]" LOC = "P22" ;
-NET "RAM_A[12]" LOC = "N19" ;
-NET "RAM_A[13]" LOC = "N17" ;
-NET "RAM_A[14]" LOC = "N18" ;
-NET "RAM_A[15]" LOC = "T17" ;
-NET "RAM_A[16]" LOC = "U19" ;
-NET "RAM_A[17]" LOC = "U18" ;
-NET "RAM_A[18]" LOC = "V19" ;
-NET "RAM_CE1n" LOC = "U20" ;
-NET "RAM_CENn" LOC = "P18" ;
-NET "RAM_CLK" LOC = "P17" ;
-NET "RAM_WEn" LOC = "R22" ;
-NET "RAM_OEn" LOC = "R21" ;
-NET "RAM_LDn" LOC = "R19" ;
+NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
+NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ;
NET "ser_enable" LOC = "W11" ;
NET "ser_prbsen" LOC = "AA3" ;
NET "ser_loopen" LOC = "Y4" ;
@@ -264,22 +264,22 @@ NET "sdi_tx_adc" LOC = "J4" ;
NET "sen_tx_dac" LOC = "H4" ;
NET "sclk_tx_dac" LOC = "J5" ;
NET "sdi_tx_dac" LOC = "J6" ;
-NET "io_tx[0]" LOC = "K4" ;
-NET "io_tx[1]" LOC = "K3" ;
-NET "io_tx[2]" LOC = "G1" ;
-NET "io_tx[3]" LOC = "G5" ;
-NET "io_tx[4]" LOC = "H5" ;
-NET "io_tx[5]" LOC = "F3" ;
-NET "io_tx[6]" LOC = "F2" ;
-NET "io_tx[7]" LOC = "F5" ;
-NET "io_tx[8]" LOC = "G6" ;
-NET "io_tx[9]" LOC = "E2" ;
-NET "io_tx[10]" LOC = "E1" ;
-NET "io_tx[11]" LOC = "E3" ;
-NET "io_tx[12]" LOC = "F4" ;
-NET "io_tx[13]" LOC = "D2" ;
-NET "io_tx[14]" LOC = "D4" ;
-NET "io_tx[15]" LOC = "E4" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
NET "sen_rx_db" LOC = "D22" ;
NET "sclk_rx_db" LOC = "F19" ;
NET "sdo_rx_db" LOC = "G20" ;
@@ -291,22 +291,22 @@ NET "sdi_rx_adc" LOC = "H22" ;
NET "sen_rx_dac" LOC = "J18" ;
NET "sclk_rx_dac" LOC = "J19" ;
NET "sdi_rx_dac" LOC = "J21" ;
-NET "io_rx[0]" LOC = "L21" ;
-NET "io_rx[1]" LOC = "L20" ;
-NET "io_rx[2]" LOC = "L19" ;
-NET "io_rx[3]" LOC = "L18" ;
-NET "io_rx[4]" LOC = "L17" ;
-NET "io_rx[5]" LOC = "K22" ;
-NET "io_rx[6]" LOC = "K21" ;
-NET "io_rx[7]" LOC = "K20" ;
-NET "io_rx[8]" LOC = "G22" ;
-NET "io_rx[9]" LOC = "G21" ;
-NET "io_rx[10]" LOC = "F21" ;
-NET "io_rx[11]" LOC = "F20" ;
-NET "io_rx[12]" LOC = "G19" ;
-NET "io_rx[13]" LOC = "G18" ;
-NET "io_rx[14]" LOC = "G17" ;
-NET "io_rx[15]" LOC = "E22" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
NET "clk_to_mac" TNM_NET = "clk_to_mac";
TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
@@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 08:19:43 +0000