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diff --git a/fpga/usrp2/top/N2x0/u2plus.ucf b/fpga/usrp2/top/N2x0/u2plus.ucf
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+++ b/fpga/usrp2/top/N2x0/u2plus.ucf
@@ -0,0 +1,424 @@
+## Main 100 MHz Clock
+NET "CLK_FPGA_P" LOC = "AA13" ;
+NET "CLK_FPGA_N" LOC = "Y13" ;
+
+## ADC
+NET "ADC_clkout_p" LOC = "P1" ;
+NET "ADC_clkout_n" LOC = "P2" ;
+NET "ADCA_12_p" LOC = "Y1" ;
+NET "ADCA_12_n" LOC = "Y2" ;
+NET "ADCA_10_p" LOC = "W3" ;
+NET "ADCA_10_n" LOC = "W4" ;
+NET "ADCA_8_p" LOC = "T7" ;
+NET "ADCA_8_n" LOC = "U6" ;
+NET "ADCA_6_p" LOC = "U5" ;
+NET "ADCA_6_n" LOC = "V5" ;
+NET "ADCA_4_p" LOC = "T10" ;
+NET "ADCA_4_n" LOC = "T9" ;
+NET "ADCA_2_p" LOC = "V1" ;
+NET "ADCA_2_n" LOC = "V2" ;
+NET "ADCA_0_p" LOC = "R8" ;
+NET "ADCA_0_n" LOC = "R7" ;
+NET "ADCB_2_p" LOC = "U7" ;
+NET "ADCB_2_n" LOC = "U8" ;
+NET "ADCB_0_p" LOC = "AA2" ;
+NET "ADCB_0_n" LOC = "AA3" ;
+NET "ADCB_4_p" LOC = "AE1" ;
+NET "ADCB_4_n" LOC = "AE2" ;
+NET "ADCB_6_p" LOC = "W1" ;
+NET "ADCB_6_n" LOC = "W2" ;
+NET "ADCB_8_p" LOC = "U3" ;
+NET "ADCB_8_n" LOC = "V4" ;
+NET "ADCB_10_p" LOC = "J1" ;
+NET "ADCB_10_n" LOC = "K1" ;
+NET "ADCB_12_p" LOC = "J3" ;
+NET "ADCB_12_n" LOC = "J2" ;
+
+## DAC
+NET "DAC_LOCK" LOC = "P4" ;
+NET "DACA<0>" LOC = "P8" ;
+NET "DACA<1>" LOC = "P9" ;
+NET "DACA<2>" LOC = "R5" ;
+NET "DACA<3>" LOC = "R6" ;
+NET "DACA<4>" LOC = "P7" ;
+NET "DACA<5>" LOC = "P6" ;
+NET "DACA<6>" LOC = "T3" ;
+NET "DACA<7>" LOC = "T4" ;
+NET "DACA<8>" LOC = "R3" ;
+NET "DACA<9>" LOC = "R4" ;
+NET "DACA<10>" LOC = "R2" ;
+NET "DACA<11>" LOC = "N1" ;
+NET "DACA<12>" LOC = "N2" ;
+NET "DACA<13>" LOC = "N5" ;
+NET "DACA<14>" LOC = "N4" ;
+NET "DACA<15>" LOC = "M2" ;
+NET "DACB<0>" LOC = "M5" ;
+NET "DACB<1>" LOC = "M6" ;
+NET "DACB<2>" LOC = "M4" ;
+NET "DACB<3>" LOC = "M3" ;
+NET "DACB<4>" LOC = "M8" ;
+NET "DACB<5>" LOC = "M7" ;
+NET "DACB<6>" LOC = "L4" ;
+NET "DACB<7>" LOC = "L3" ;
+NET "DACB<8>" LOC = "K3" ;
+NET "DACB<9>" LOC = "K2" ;
+NET "DACB<10>" LOC = "K5" ;
+NET "DACB<11>" LOC = "K4" ;
+NET "DACB<12>" LOC = "M10" ;
+NET "DACB<13>" LOC = "M9" ;
+NET "DACB<14>" LOC = "J5" ;
+NET "DACB<15>" LOC = "J4" ;
+
+## TX DB GPIO
+NET "io_tx<15>" LOC = "K6" ;
+NET "io_tx<14>" LOC = "L7" ;
+NET "io_tx<13>" LOC = "H2" ;
+NET "io_tx<12>" LOC = "H1" ;
+NET "io_tx<11>" LOC = "L10" ;
+NET "io_tx<10>" LOC = "L9" ;
+NET "io_tx<9>" LOC = "G3" ;
+NET "io_tx<8>" LOC = "F3" ;
+NET "io_tx<7>" LOC = "K7" ;
+NET "io_tx<6>" LOC = "J6" ;
+NET "io_tx<5>" LOC = "E1" ;
+NET "io_tx<4>" LOC = "F2" ;
+NET "io_tx<3>" LOC = "J7" ;
+NET "io_tx<2>" LOC = "H6" ;
+NET "io_tx<1>" LOC = "F5" ;
+NET "io_tx<0>" LOC = "G4" ;
+
+## RX DB GPIO
+NET "io_rx<15>" LOC = "AD1" ;
+NET "io_rx<14>" LOC = "AD2" ;
+NET "io_rx<13>" LOC = "AC2" ;
+NET "io_rx<12>" LOC = "AC3" ;
+NET "io_rx<11>" LOC = "W7" ;
+NET "io_rx<10>" LOC = "W6" ;
+NET "io_rx<9>" LOC = "U9" ;
+NET "io_rx<8>" LOC = "V8" ;
+NET "io_rx<7>" LOC = "AB1" ;
+NET "io_rx<6>" LOC = "AC1" ;
+NET "io_rx<5>" LOC = "V7" ;
+NET "io_rx<4>" LOC = "V6" ;
+NET "io_rx<3>" LOC = "Y5" ;
+NET "io_rx<2>" LOC = "R10" ;
+NET "io_rx<1>" LOC = "R1" ;
+NET "io_rx<0>" LOC = "M1" ;
+
+## MISC
+NET "leds<5>" LOC = "AF25" ;
+NET "leds<4>" LOC = "AE25" ;
+NET "leds<3>" LOC = "AF23" ;
+NET "leds<2>" LOC = "AE23" ;
+NET "leds<1>" LOC = "AB18" ;
+NET "FPGA_RESET" LOC = "K24" ;
+
+## Debug
+NET "debug_clk<0>" LOC = "AA10" ;
+NET "debug_clk<1>" LOC = "AD11" ;
+NET "debug<0>" LOC = "AC19" ;
+NET "debug<1>" LOC = "AF20" ;
+NET "debug<2>" LOC = "AE20" ;
+NET "debug<3>" LOC = "AC16" ;
+NET "debug<4>" LOC = "AB16" ;
+NET "debug<5>" LOC = "AF19" ;
+NET "debug<6>" LOC = "AE19" ;
+NET "debug<7>" LOC = "V15" ;
+NET "debug<8>" LOC = "U15" ;
+NET "debug<9>" LOC = "AE17" ;
+NET "debug<10>" LOC = "AD17" ;
+NET "debug<11>" LOC = "V14" ;
+NET "debug<12>" LOC = "W15" ;
+NET "debug<13>" LOC = "AC15" ;
+NET "debug<14>" LOC = "AD14" ;
+NET "debug<15>" LOC = "AC14" ;
+NET "debug<16>" LOC = "AC11" ;
+NET "debug<17>" LOC = "AB12" ;
+NET "debug<18>" LOC = "AC12" ;
+NET "debug<19>" LOC = "V13" ;
+NET "debug<20>" LOC = "W13" ;
+NET "debug<21>" LOC = "AE8" ;
+NET "debug<22>" LOC = "AF8" ;
+NET "debug<23>" LOC = "V12" ;
+NET "debug<24>" LOC = "W12" ;
+NET "debug<25>" LOC = "AB9" ;
+NET "debug<26>" LOC = "AC9" ;
+NET "debug<27>" LOC = "AC8" ;
+NET "debug<28>" LOC = "AB7" ;
+NET "debug<29>" LOC = "V11" ;
+NET "debug<30>" LOC = "U11" ;
+NET "debug<31>" LOC = "Y10" ;
+
+## UARTS
+NET "TXD<3>" LOC = "AD20" ;
+NET "TXD<2>" LOC = "AC20" ;
+NET "TXD<1>" LOC = "AD19" ;
+NET "RXD<3>" LOC = "AF17" ;
+NET "RXD<2>" LOC = "AF15" ;
+NET "RXD<1>" LOC = "AD12" ;
+
+## AD9510
+NET "clk_status" LOC = "AD22" ;
+NET "CLK_FUNC" LOC = "AC21" ;
+NET "clk_sel<0>" LOC = "AE21" ;
+NET "clk_sel<1>" LOC = "AD21" ;
+NET "clk_en<1>" LOC = "AA17" ;
+NET "clk_en<0>" LOC = "Y17" ;
+
+## I2C
+NET "SDA" LOC = "V16" ;
+NET "SCL" LOC = "U16" ;
+
+## Timing
+NET "PPS_IN" LOC = "AB6" ;
+NET "PPS2_IN" LOC = "AA20" ;
+
+## SPI
+NET "SEN_CLK" LOC = "AA18" ;
+NET "MOSI_CLK" LOC = "W17" ;
+NET "SCLK_CLK" LOC = "V17" ;
+NET "MISO_CLK" LOC = "AC10" ;
+
+NET "SEN_DAC" LOC = "AE7" ;
+NET "SCLK_DAC" LOC = "AF5" ;
+NET "MOSI_DAC" LOC = "AE6" ;
+NET "MISO_DAC" LOC = "Y3" ;
+
+NET "SCLK_ADC" LOC = "B1" ;
+NET "MOSI_ADC" LOC = "J8" ;
+NET "SEN_ADC" LOC = "J9" ;
+
+NET "MOSI_TX_ADC" LOC = "V10" ;
+NET "SEN_TX_ADC" LOC = "W10" ;
+NET "SCLK_TX_ADC" LOC = "AC6" ;
+NET "MISO_TX_ADC" LOC = "G1" ;
+
+NET "MOSI_TX_DAC" LOC = "AD6" ;
+NET "SEN_TX_DAC" LOC = "AE4" ;
+NET "SCLK_TX_DAC" LOC = "AF4" ;
+
+NET "SCLK_TX_DB" LOC = "AE3" ;
+NET "MOSI_TX_DB" LOC = "AF3" ;
+NET "SEN_TX_DB" LOC = "W9" ;
+NET "MISO_TX_DB" LOC = "AA5" ;
+
+NET "MOSI_RX_ADC" LOC = "E3" ;
+NET "SCLK_RX_ADC" LOC = "F4" ;
+NET "SEN_RX_ADC" LOC = "D3" ;
+NET "MISO_RX_ADC" LOC = "C1" ;
+
+NET "SCLK_RX_DAC" LOC = "E4" ;
+NET "SEN_RX_DAC" LOC = "K9" ;
+NET "MOSI_RX_DAC" LOC = "K8" ;
+
+NET "SCLK_RX_DB" LOC = "G6" ;
+NET "MOSI_RX_DB" LOC = "H7" ;
+NET "SEN_RX_DB" LOC = "B2" ;
+NET "MISO_RX_DB" LOC = "H4" ;
+
+## ETH PHY
+NET "CLK_TO_MAC" LOC = "P26" ;
+
+NET "GMII_TXD<7>" LOC = "G21" ;
+NET "GMII_TXD<6>" LOC = "C26" ;
+NET "GMII_TXD<5>" LOC = "C25" ;
+NET "GMII_TXD<4>" LOC = "J21" ;
+NET "GMII_TXD<3>" LOC = "H21" ;
+NET "GMII_TXD<2>" LOC = "D25" ;
+NET "GMII_TXD<1>" LOC = "D24" ;
+NET "GMII_TXD<0>" LOC = "E26" ;
+NET "GMII_TX_EN" LOC = "D26" ;
+NET "GMII_TX_ER" LOC = "J19" ;
+NET "GMII_GTX_CLK" LOC = "J20" ;
+NET "GMII_TX_CLK" LOC = "P25" ;
+
+NET "GMII_RX_CLK" LOC = "P21" ;
+NET "GMII_RXD<7>" LOC = "G22" ;
+NET "GMII_RXD<6>" LOC = "K19" ;
+NET "GMII_RXD<5>" LOC = "K18" ;
+NET "GMII_RXD<4>" LOC = "E24" ;
+NET "GMII_RXD<3>" LOC = "F23" ;
+NET "GMII_RXD<2>" LOC = "L18" ;
+NET "GMII_RXD<1>" LOC = "L17" ;
+NET "GMII_RXD<0>" LOC = "F25" ;
+NET "GMII_RX_DV" LOC = "F24" ;
+NET "GMII_RX_ER" LOC = "L20" ;
+NET "GMII_CRS" LOC = "K20" ;
+NET "GMII_COL" LOC = "G23" ;
+
+NET "PHY_INTn" LOC = "L22" ;
+NET "MDIO" LOC = "K21" ;
+NET "MDC" LOC = "J23" ;
+NET "PHY_RESETn" LOC = "J22" ;
+NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+
+## MIMO Interface
+NET "exp_time_out_p" LOC = "Y14" ;
+NET "exp_time_out_n" LOC = "AA14" ;
+NET "exp_time_in_p" LOC = "N18" ;
+NET "exp_time_in_n" LOC = "N17" ;
+NET "exp_user_out_p" LOC = "AF14" ;
+NET "exp_user_out_n" LOC = "AE14" ;
+NET "exp_user_in_p" LOC = "L24" ;
+NET "exp_user_in_n" LOC = "M23" ;
+
+## SERDES
+NET "ser_enable" LOC = "R20" ;
+NET "ser_prbsen" LOC = "U23" ;
+NET "ser_loopen" LOC = "R19" ;
+NET "ser_rx_en" LOC = "Y21" ;
+NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK
+NET "ser_t<15>" LOC = "V23" ;
+NET "ser_t<14>" LOC = "U22" ;
+NET "ser_t<13>" LOC = "V24" ;
+NET "ser_t<12>" LOC = "V25" ;
+NET "ser_t<11>" LOC = "W23" ;
+NET "ser_t<10>" LOC = "V22" ;
+NET "ser_t<9>" LOC = "T18" ;
+NET "ser_t<8>" LOC = "T17" ;
+NET "ser_t<7>" LOC = "Y24" ;
+NET "ser_t<6>" LOC = "Y25" ;
+NET "ser_t<5>" LOC = "U21" ;
+NET "ser_t<4>" LOC = "T20" ;
+NET "ser_t<3>" LOC = "Y22" ;
+NET "ser_t<2>" LOC = "Y23" ;
+NET "ser_t<1>" LOC = "U19" ;
+NET "ser_t<0>" LOC = "U18" ;
+NET "ser_tkmsb" LOC = "AA24" ;
+NET "ser_tklsb" LOC = "AA25" ;
+NET "ser_rx_clk" LOC = "P18" ;
+NET "ser_r<15>" LOC = "V21" ;
+NET "ser_r<14>" LOC = "U20" ;
+NET "ser_r<13>" LOC = "AA22" ;
+NET "ser_r<12>" LOC = "AA23" ;
+NET "ser_r<11>" LOC = "V18" ;
+NET "ser_r<10>" LOC = "V19" ;
+NET "ser_r<9>" LOC = "AB23" ;
+NET "ser_r<8>" LOC = "AC26" ;
+NET "ser_r<7>" LOC = "AB26" ;
+NET "ser_r<6>" LOC = "AD26" ;
+NET "ser_r<5>" LOC = "AC25" ;
+NET "ser_r<4>" LOC = "W20" ;
+NET "ser_r<3>" LOC = "W21" ;
+NET "ser_r<2>" LOC = "AC23" ;
+NET "ser_r<1>" LOC = "AC24" ;
+NET "ser_r<0>" LOC = "AE26" ;
+NET "ser_rkmsb" LOC = "AD25" ;
+NET "ser_rklsb" LOC = "Y20" ;
+
+## SRAM
+NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ;
+
+## SPI Flash
+NET "flash_miso" LOC = "AF24" ;
+NET "flash_clk" LOC = "AE24" ;
+NET "flash_mosi" LOC = "AB15" ;
+NET "flash_cs" LOC = "AA7" ;
+
+## MISC FPGA, unused for now
+#NET "PROG_B" LOC = "A2" ;
+#NET "PUDC_B" LOC = "G8" ;
+#NET "DONE" LOC = "AB21" ;
+#NET "INIT_B" LOC = "AA15" ;
+
+
+#NET "unnamed_net19" LOC = "AE9" ; # VS1
+#NET "unnamed_net18" LOC = "AF9" ; # VS0
+#NET "unnamed_net17" LOC = "AA12" ; # VS2
+#NET "unnamed_net16" LOC = "Y7" ; # M2
+#NET "unnamed_net15" LOC = "AC4" ; # M1
+#NET "unnamed_net14" LOC = "AD4" ; # M0
+#NET "unnamed_net13" LOC = "D4" ; # TMS
+#NET "unnamed_net12" LOC = "E23" ; # TDO
+#NET "unnamed_net11" LOC = "G7" ; # TDI
+#NET "unnamed_net10" LOC = "A25" ; # TCK
+#NET "unnamed_net20" LOC = "V20" ; # SUSPEND
+
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
+
+#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
+
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 23:01:41 +0000