3 files changed, 13 insertions, 23 deletions
diff --git a/fpga/usrp2/top/E1x0/u1e.ucf b/fpga/usrp2/top/E1x0/u1e.ucf
index 0c487a601..278fc289a 100644
--- a/fpga/usrp2/top/E1x0/u1e.ucf
+++ b/fpga/usrp2/top/E1x0/u1e.ucf
@@ -67,8 +67,10 @@ NET "overo_gpio170"  LOC = "E8"  ;  # MISC GPIO for debug
 NET "overo_gpio176"  LOC = "B4"  ;  # MISC GPIO for debug
 
 ## Overo UART
-#NET "overo_txd1"  LOC = "C6"  ;
-#NET "overo_rxd1"  LOC = "D6"  ;
+NET "overo_txd1"  LOC = "C6"  ;
+NET "overo_rxd1"  LOC = "D6"  ;
+NET "fpga_txd1"   LOC = "AB9" ;
+NET "fpga_rxd1"   LOC = "AB8" ;
 
 ## FTDI UART to USB converter
 NET "FPGA_TXD"  LOC = "G19"  ;
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v
index ff2e08394..903ef7a6f 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/u1e.v
@@ -22,6 +22,7 @@ module u1e
   (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input debug_pb, output FPGA_TXD, input FPGA_RXD,
+   output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1,
 
    // GPMC
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -59,6 +60,10 @@ module u1e
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
    // /////////////////////////////////////////////////////////////////////////
+   // UART level conversion
+   assign fpga_txd1 = overo_txd1;
+   assign overo_rxd1 = fpga_rxd1;
+   
    // SPI
    wire  mosi, sclk, miso;
    assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index 20dd98a36..e1bb50890 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -489,26 +489,9 @@ module u1e_core
    // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
 
-   assign debug_clk = { EM_CLK, clk_fpga };
-
-/*
-   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
-		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
-		    { EM_D } };
-
-*/
-   assign debug = debug_gpmc;
-
-   assign debug_gpio_0 = { {run_tx, 2'b0, strobe_rx0, tx_i[11:0]}, 
-			   {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
-
-   assign debug_gpio_1 = debug_vt;
+   assign debug_clk = 2'b00; //{ EM_CLK, clk_fpga };
+   assign debug = 0;
+   assign debug_gpio_0 = 0;
+   assign debug_gpio_1 = 0;
    
-/*   
-   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
-			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
-			   {2'b0, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
-			   {2'b0, bus_error, debug_gpmc[4:0] },
-			   {misc_gpio[7:0]} };
-  */ 
 endmodule // u1e_core