diff options
Diffstat (limited to 'fpga/usrp2/top/E1x0/u1e.v')
| -rw-r--r-- | fpga/usrp2/top/E1x0/u1e.v | 28 |
1 files changed, 3 insertions, 25 deletions
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v index dbd6173f3..ff2e08394 100644 --- a/fpga/usrp2/top/E1x0/u1e.v +++ b/fpga/usrp2/top/E1x0/u1e.v @@ -53,32 +53,10 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Clocking - wire clk_fpga, clk_fpga_in; - + wire clk_fpga; + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - wire clk_2x, dcm_rst, dcm_locked, clk_fb; - DCM #(.CLK_FEEDBACK ( "1X" ), - .CLKDV_DIVIDE ( 2 ), - .CLKFX_DIVIDE ( 2 ), - .CLKFX_MULTIPLY ( 2 ), - .CLKIN_DIVIDE_BY_2 ( "FALSE" ), - .CLKIN_PERIOD ( 15.625 ), - .CLKOUT_PHASE_SHIFT ( "NONE" ), - .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), - .DFS_FREQUENCY_MODE ( "LOW" ), - .DLL_FREQUENCY_MODE ( "LOW" ), - .DUTY_CYCLE_CORRECTION ( "TRUE" ), - .FACTORY_JF ( 16'h8080 ), - .PHASE_SHIFT ( 0 ), - .STARTUP_WAIT ( "FALSE" )) - clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), - .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), - .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(), .CLK2X180(), - .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), - .LOCKED(dcm_locked), .STATUS()); + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); // ///////////////////////////////////////////////////////////////////////// // SPI |