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-rw-r--r--fpga/usrp2/top/E1x0/timing.ucf13
1 files changed, 13 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
new file mode 100644
index 000000000..8df28c9d3
--- /dev/null
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -0,0 +1,13 @@
+
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+
+
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;